Differential D13660 Diff 37160 head/sys/dev/e1000/e1000_ich8lan.c

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head/sys/dev/e1000/e1000_ich8lan.c

Show First 20 Lines • Show All 339 Lines • ▼ Show 20 Lines	static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)

/* The MAC-PHY interconnect may be in SMBus mode. If the PHY is		/* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
* inaccessible and resetting the PHY is not blocked, toggle the		* inaccessible and resetting the PHY is not blocked, toggle the
* LANPHYPC Value bit to force the interconnect to PCIe mode.		* LANPHYPC Value bit to force the interconnect to PCIe mode.
*/		*/
switch (hw->mac.type) {		switch (hw->mac.type) {
case e1000_pch_lpt:		case e1000_pch_lpt:
case e1000_pch_spt:		case e1000_pch_spt:
		case e1000_pch_cnp:
if (e1000_phy_is_accessible_pchlan(hw))		if (e1000_phy_is_accessible_pchlan(hw))
break;		break;

/* Before toggling LANPHYPC, see if PHY is accessible by		/* Before toggling LANPHYPC, see if PHY is accessible by
* forcing MAC to SMBus mode first.		* forcing MAC to SMBus mode first.
*/		*/
mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);		mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
mac_reg \|= E1000_CTRL_EXT_FORCE_SMBUS;		mac_reg \|= E1000_CTRL_EXT_FORCE_SMBUS;
▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines	default:
if (ret_val)		if (ret_val)
return ret_val;		return ret_val;
if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))		if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
break;		break;
/* fall-through */		/* fall-through */
case e1000_pch2lan:		case e1000_pch2lan:
case e1000_pch_lpt:		case e1000_pch_lpt:
case e1000_pch_spt:		case e1000_pch_spt:
		case e1000_pch_cnp:
/* In case the PHY needs to be in mdio slow mode,		/* In case the PHY needs to be in mdio slow mode,
* set slow mode and try to get the PHY id again.		* set slow mode and try to get the PHY id again.
*/		*/
ret_val = e1000_set_mdio_slow_mode_hv(hw);		ret_val = e1000_set_mdio_slow_mode_hv(hw);
if (ret_val)		if (ret_val)
return ret_val;		return ret_val;
ret_val = e1000_get_phy_id(hw);		ret_val = e1000_get_phy_id(hw);
if (ret_val)		if (ret_val)
▲ Show 20 Lines • Show All 285 Lines • ▼ Show 20 Lines	case e1000_ich10lan:
mac->ops.led_off = e1000_led_off_ich8lan;		mac->ops.led_off = e1000_led_off_ich8lan;
break;		break;
case e1000_pch2lan:		case e1000_pch2lan:
mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;		mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
mac->ops.rar_set = e1000_rar_set_pch2lan;		mac->ops.rar_set = e1000_rar_set_pch2lan;
/* fall-through */		/* fall-through */
case e1000_pch_lpt:		case e1000_pch_lpt:
case e1000_pch_spt:		case e1000_pch_spt:
		case e1000_pch_cnp:
/* multicast address update for pch2 */		/* multicast address update for pch2 */
mac->ops.update_mc_addr_list =		mac->ops.update_mc_addr_list =
e1000_update_mc_addr_list_pch2lan;		e1000_update_mc_addr_list_pch2lan;
/* fall-through */		/* fall-through */
case e1000_pchlan:		case e1000_pchlan:
/* check management mode */		/* check management mode */
mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
/* ID LED init */		/* ID LED init */
▲ Show 20 Lines • Show All 1,021 Lines • ▼ Show 20 Lines	void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
case e1000_ich9lan:		case e1000_ich9lan:
case e1000_ich10lan:		case e1000_ich10lan:
hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;		hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
break;		break;
case e1000_pchlan:		case e1000_pchlan:
case e1000_pch2lan:		case e1000_pch2lan:
case e1000_pch_lpt:		case e1000_pch_lpt:
case e1000_pch_spt:		case e1000_pch_spt:
		case e1000_pch_cnp:
hw->phy.ops.init_params = e1000_init_phy_params_pchlan;		hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
break;		break;
default:		default:
break;		break;
}		}
}		}

/**		/**
▲ Show 20 Lines • Show All 448 Lines • ▼ Show 20 Lines	if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) \|\|
sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;		sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
break;		break;
}		}
/* Fall-thru */		/* Fall-thru */
case e1000_pchlan:		case e1000_pchlan:
case e1000_pch2lan:		case e1000_pch2lan:
case e1000_pch_lpt:		case e1000_pch_lpt:
case e1000_pch_spt:		case e1000_pch_spt:
		case e1000_pch_cnp:
sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;		sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
break;		break;
default:		default:
return ret_val;		return ret_val;
}		}

ret_val = hw->phy.ops.acquire(hw);		ret_val = hw->phy.ops.acquire(hw);
if (ret_val)		if (ret_val)
▲ Show 20 Lines • Show All 344 Lines • ▼ Show 20 Lines	static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
if (hw->phy.type == e1000_phy_82578) {		if (hw->phy.type == e1000_phy_82578) {
/* Return registers to default by doing a soft reset then		/* Return registers to default by doing a soft reset then
* writing 0x3140 to the control register.		* writing 0x3140 to the control register.
*/		*/
if (hw->phy.revision < 2) {		if (hw->phy.revision < 2) {
e1000_phy_sw_reset_generic(hw);		e1000_phy_sw_reset_generic(hw);
ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,		ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
0x3140);		0x3140);
		if (ret_val)
		return ret_val;
}		}
}		}

/* Select page 0 */		/* Select page 0 */
ret_val = hw->phy.ops.acquire(hw);		ret_val = hw->phy.ops.acquire(hw);
if (ret_val)		if (ret_val)
return ret_val;		return ret_val;

▲ Show 20 Lines • Show All 741 Lines • ▼ Show 20 Lines	static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw hw, u32 bank)
u32 nvm_dword = 0;		u32 nvm_dword = 0;
u8 sig_byte = 0;		u8 sig_byte = 0;
s32 ret_val;		s32 ret_val;

DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");		DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");

switch (hw->mac.type) {		switch (hw->mac.type) {
case e1000_pch_spt:		case e1000_pch_spt:
		case e1000_pch_cnp:
bank1_offset = nvm->flash_bank_size;		bank1_offset = nvm->flash_bank_size;
act_offset = E1000_ICH_NVM_SIG_WORD;		act_offset = E1000_ICH_NVM_SIG_WORD;

/* set bank to 0 in case flash read fails */		/* set bank to 0 in case flash read fails */
*bank = 0;		*bank = 0;

/* Check bank 0 */		/* Check bank 0 */
ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,		ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
▲ Show 20 Lines • Show All 959 Lines • ▼ Show 20 Lines	static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
/* Read NVM and check Invalid Image CSUM bit. If this bit is 0,		/* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
* the checksum needs to be fixed. This bit is an indication that		* the checksum needs to be fixed. This bit is an indication that
* the NVM was prepared by OEM software and did not calculate		* the NVM was prepared by OEM software and did not calculate
* the checksum...a likely scenario.		* the checksum...a likely scenario.
*/		*/
switch (hw->mac.type) {		switch (hw->mac.type) {
case e1000_pch_lpt:		case e1000_pch_lpt:
case e1000_pch_spt:		case e1000_pch_spt:
		case e1000_pch_cnp:
word = NVM_COMPAT;		word = NVM_COMPAT;
valid_csum_mask = NVM_COMPAT_VALID_CSUM;		valid_csum_mask = NVM_COMPAT_VALID_CSUM;
break;		break;
default:		default:
word = NVM_FUTURE_INIT_WORD1;		word = NVM_FUTURE_INIT_WORD1;
valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;		valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
break;		break;
}		}
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