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sys/dev/mii/rgephyreg.h
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* $FreeBSD$ | * $FreeBSD$ | ||||
*/ | */ | ||||
#ifndef _DEV_MII_RGEPHYREG_H_ | #ifndef _DEV_MII_RGEPHYREG_H_ | ||||
#define _DEV_MII_RGEPHYREG_H_ | #define _DEV_MII_RGEPHYREG_H_ | ||||
#define RGEPHY_8211B 2 | #define RGEPHY_8211B 2 | ||||
#define RGEPHY_8211C 3 | #define RGEPHY_8211C 3 | ||||
#define RGEPHY_8211E 5 | |||||
#define RGEPHY_8211F 6 | #define RGEPHY_8211F 6 | ||||
/* | /* | ||||
* RealTek 8169S/8110S gigE PHY registers | * RealTek 8169S/8110S gigE PHY registers | ||||
*/ | */ | ||||
#define RGEPHY_MII_BMCR 0x00 | #define RGEPHY_MII_BMCR 0x00 | ||||
#define RGEPHY_BMCR_RESET 0x8000 | #define RGEPHY_BMCR_RESET 0x8000 | ||||
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#define RGEPHY_SSR_SPD_MASK 0xc000 | #define RGEPHY_SSR_SPD_MASK 0xc000 | ||||
#define RGEPHY_SSR_FDX 0x2000 /* full duplex */ | #define RGEPHY_SSR_FDX 0x2000 /* full duplex */ | ||||
#define RGEPHY_SSR_PAGE_RECEIVED 0x1000 /* new page received */ | #define RGEPHY_SSR_PAGE_RECEIVED 0x1000 /* new page received */ | ||||
#define RGEPHY_SSR_SPD_DPLX_RESOLVED 0x0800 /* speed/duplex resolved */ | #define RGEPHY_SSR_SPD_DPLX_RESOLVED 0x0800 /* speed/duplex resolved */ | ||||
#define RGEPHY_SSR_LINK 0x0400 /* link up */ | #define RGEPHY_SSR_LINK 0x0400 /* link up */ | ||||
#define RGEPHY_SSR_MDI_XOVER 0x0040 /* MDI crossover */ | #define RGEPHY_SSR_MDI_XOVER 0x0040 /* MDI crossover */ | ||||
#define RGEPHY_SSR_ALDPS 0x0008 /* RTL8211C(L) only */ | #define RGEPHY_SSR_ALDPS 0x0008 /* RTL8211C(L) only */ | ||||
#define RGEPHY_SSR_JABBER 0x0001 /* Jabber */ | #define RGEPHY_SSR_JABBER 0x0001 /* Jabber */ | ||||
/* RTL8211E */ | |||||
#define RGEPHY_E_CONFREG 0x1C /* Configuration register */ | |||||
#define RGEPHY_E_CONFREG_TXD 0x0002 /* TXD Enabled */ | |||||
#define RGEPHY_E_CONFREG_RXD 0x0004 /* RXD Enabled */ | |||||
#define RGEPHY_E_CONFREG_MAGIC 0xb400 /* Undocumented */ | |||||
kevans: Only bits 0-9 of the configuration reg are documented; I have no idea what 0xb400 corresponds… | |||||
#define RGEPHY_E_EPAGSR 0x1E /* Extension page select register */ | |||||
#define RGEPHY_E_PAGSEL 0x1F /* Page select register */ | |||||
/* RTL8211F */ | /* RTL8211F */ | ||||
#define RGEPHY_F_MII_PCR1 0x18 /* PHY Specific control register 1 */ | #define RGEPHY_F_MII_PCR1 0x18 /* PHY Specific control register 1 */ | ||||
#define RGEPHY_F_PCR1_MDI_MM 0x0200 /* MDI / MDIX Manual Mode */ | #define RGEPHY_F_PCR1_MDI_MM 0x0200 /* MDI / MDIX Manual Mode */ | ||||
#define RGEPHY_F_PCR1_MDI_MODE 0x0100 /* MDI Mode (0=MDIX,1=MDI) */ | #define RGEPHY_F_PCR1_MDI_MODE 0x0100 /* MDI Mode (0=MDIX,1=MDI) */ | ||||
#define RGEPHY_F_PCR1_ALDPS_EN 0x0004 /* Link Down Power Saving Enable */ | #define RGEPHY_F_PCR1_ALDPS_EN 0x0004 /* Link Down Power Saving Enable */ | ||||
/* RTL8211F */ | /* RTL8211F */ | ||||
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Only bits 0-9 of the configuration reg are documented; I have no idea what 0xb400 corresponds to, and from the sounds of it the Pine64 team either doesn't know or can't reveal that. They have claimed that it comes from discussion with Realtek engineers, though.