Differential D13591 Diff 36920 sys/arm/allwinner/if_awg.c

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sys/arm/allwinner/if_awg.c

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#define EMAC_CLK_PIT (0x1 << 2)		#define EMAC_CLK_PIT (0x1 << 2)
#define EMAC_CLK_PIT_MII (0 << 2)		#define EMAC_CLK_PIT_MII (0 << 2)
#define EMAC_CLK_PIT_RGMII (1 << 2)		#define EMAC_CLK_PIT_RGMII (1 << 2)
#define EMAC_CLK_SRC (0x3 << 0)		#define EMAC_CLK_SRC (0x3 << 0)
#define EMAC_CLK_SRC_MII (0 << 0)		#define EMAC_CLK_SRC_MII (0 << 0)
#define EMAC_CLK_SRC_EXT_RGMII (1 << 0)		#define EMAC_CLK_SRC_EXT_RGMII (1 << 0)
#define EMAC_CLK_SRC_RGMII (2 << 0)		#define EMAC_CLK_SRC_RGMII (2 << 0)

		/* RTL PHY Registers */
		#define PHY_MAGIC 0x1c
		#define PHY_MAGIC_NORXDELAY 0xb591

		/* Extension Page Select */
		#define PHY_EPAGSR 0x1e
		#define PHY_EPAGSR_MASK 0xff
		#define PHY_EPAGSR_PAGE(n) ((n) & PHY_EPAGSR_MASK)
		/* Page Select */
		#define PHY_PAGSEL 0x1f
		#define PHY_PAGSEL_MASK 0x7
		#define PHY_PAGSEL_PAGE(n) ((n) & PHY_PAGSEL_MASK)
		#define PHY_PAGSEL_EXT 0x7


/* Burst length of RX and TX DMA transfers */		/* Burst length of RX and TX DMA transfers */
static int awg_burst_len = BURST_LEN_DEFAULT;		static int awg_burst_len = BURST_LEN_DEFAULT;
TUNABLE_INT("hw.awg.burst_len", &awg_burst_len);		TUNABLE_INT("hw.awg.burst_len", &awg_burst_len);

/* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */		/* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */
static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT;		static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT;
TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri);		TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri);

▲ Show 20 Lines • Show All 1,111 Lines • ▼ Show 20 Lines	if (sc->res[_RES_SYSCON] != NULL) {
}		}

/* Enable TX clock */		/* Enable TX clock */
error = clk_enable(clk_tx);		error = clk_enable(clk_tx);
if (error != 0) {		if (error != 0) {
device_printf(dev, "cannot enable tx clock\n");		device_printf(dev, "cannot enable tx clock\n");
goto fail;		goto fail;
}		}
		}

		if (sc->type == EMAC_A64 && strcmp(phy_type, "rgmii") == 0) {
		/*
		* The following sequence fixes gigabit functionality on the
		* PIne64; configuring it for no RX delay causes it to stop
		jmcneillUnsubmitted Not Done Inline Actions Typo in comment. jmcneill: Typo in comment.
		* frequently dropping packets, while still getting throughput.
		*/
		awg_miibus_writereg(dev, 1, PHY_PAGSEL, PHY_PAGSEL_EXT);
		awg_miibus_writereg(dev, 1, PHY_EPAGSR, PHY_EPAGSR_PAGE(0xa4));
		awg_miibus_writereg(dev, 1, PHY_MAGIC, PHY_MAGIC_NORXDELAY);
		awg_miibus_writereg(dev, 1, PHY_PAGSEL, PHY_PAGSEL_PAGE(0));
}		}

error = 0;		error = 0;

fail:		fail:
OF_prop_free(phy_type);		OF_prop_free(phy_type);
return (error);		return (error);
}		}
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