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sys/mips/mips/support.S
Show First 20 Lines • Show All 855 Lines • ▼ Show 20 Lines | #if !defined(__mips_n64) && !defined(__mips_n32) | ||||
* a0 unless the trapframe is 64-bit, which it just isn't with O32. | * a0 unless the trapframe is 64-bit, which it just isn't with O32. | ||||
* If we take any exception, not just an interrupt, the upper | * If we take any exception, not just an interrupt, the upper | ||||
* 32-bits will be clobbered. Use only N32 and N64 kernels if you | * 32-bits will be clobbered. Use only N32 and N64 kernels if you | ||||
* want to use 64-bit registers while interrupts are enabled or | * want to use 64-bit registers while interrupts are enabled or | ||||
* with memory operations. Since this isn't even using load-linked | * with memory operations. Since this isn't even using load-linked | ||||
* and store-conditional, perhaps it should just use two registers | * and store-conditional, perhaps it should just use two registers | ||||
* instead, as is right and good with the O32 ABI. | * instead, as is right and good with the O32 ABI. | ||||
*/ | */ | ||||
LEAF(atomic_store_64) | LEAF(atomic_store_64) | ||||
imp: Why don't these use the normal ll/sc loops?
Also, the interrupt disabling is bogus. The number… | |||||
kibAuthorUnsubmitted Not Done Inline ActionsHow can I use ll/sc for 64bit value on 32bit mips ? According to the architecture specification, only one ll/sc sequence can be active, and second ll terminates the monitor armed by the first ll. I already mentioned llx which indeed allows to load two 32bit values atomically, but llx is only available on r6. Interrupt disabling was there in the version before my changes. Sure it is bogus. Feel free to use more appropriate interrupt control. kib: How can I use ll/sc for 64bit value on 32bit mips ? According to the architecture… | |||||
mfc0 t1, MIPS_COP_0_STATUS | mfc0 t1, MIPS_COP_0_STATUS | ||||
and t2, t1, ~MIPS_SR_INT_IE | and t2, t1, ~MIPS_SR_INT_IE | ||||
mtc0 t2, MIPS_COP_0_STATUS | mtc0 t2, MIPS_COP_0_STATUS | ||||
nop | nop | ||||
nop | nop | ||||
nop | nop | ||||
nop | nop | ||||
ld t0, (a1) | sw a3,4(a0) | ||||
impUnsubmitted Not Done Inline Actionswhere do we load the actual value now? imp: where do we load the actual value now?
| |||||
kibAuthorUnsubmitted Not Done Inline ActionsSomewhere in the caller. kib: Somewhere in the caller. | |||||
kibAuthorUnsubmitted Not Done Inline ActionsI later realized that your question clearly indicates the missed context. Please see r327074. kib: I later realized that your question clearly indicates the missed context. Please see r327074. | |||||
nop | nop | ||||
nop | nop | ||||
sd t0, (a0) | sw a2,0(a0) | ||||
nop | nop | ||||
nop | nop | ||||
mtc0 t1,MIPS_COP_0_STATUS | mtc0 t1,MIPS_COP_0_STATUS | ||||
nop | nop | ||||
nop | nop | ||||
nop | nop | ||||
nop | nop | ||||
j ra | j ra | ||||
nop | nop | ||||
END(atomic_store_64) | END(atomic_store_64) | ||||
LEAF(atomic_load_64) | LEAF(atomic_load_64) | ||||
mfc0 t1, MIPS_COP_0_STATUS | mfc0 t1, MIPS_COP_0_STATUS | ||||
and t2, t1, ~MIPS_SR_INT_IE | and t2, t1, ~MIPS_SR_INT_IE | ||||
mtc0 t2, MIPS_COP_0_STATUS | mtc0 t2, MIPS_COP_0_STATUS | ||||
nop | nop | ||||
nop | nop | ||||
nop | nop | ||||
nop | nop | ||||
ld t0, (a0) | lw v1,4(a0) | ||||
nop | nop | ||||
nop | nop | ||||
sd t0, (a1) | lw v0,0(a0) | ||||
nop | nop | ||||
nop | nop | ||||
mtc0 t1,MIPS_COP_0_STATUS | mtc0 t1,MIPS_COP_0_STATUS | ||||
nop | nop | ||||
nop | nop | ||||
nop | nop | ||||
nop | nop | ||||
j ra | j ra | ||||
▲ Show 20 Lines • Show All 193 Lines • Show Last 20 Lines |
Why don't these use the normal ll/sc loops?
Also, the interrupt disabling is bogus. The number of NOP hazards vary from CPU to CPU and newer mips32 instructions allow one to do this without the raciness of the read / modify / write of the STATUS register. This is a fairly heavyweight operation.