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head/sys/dev/sfxge/common/efx_regs_ef10.h
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/*- | /*- | ||||
* Copyright 2007-2010 Solarflare Communications Inc. All rights reserved. | * Copyright (c) 2007-2015 Solarflare Communications Inc. | ||||
* All rights reserved. | |||||
* | * | ||||
* Redistribution and use in source and binary forms, with or without | * Redistribution and use in source and binary forms, with or without | ||||
* modification, are permitted provided that the following conditions | * modification, are permitted provided that the following conditions are met: | ||||
* are met: | |||||
* 1. Redistributions of source code must retain the above copyright | |||||
* notice, this list of conditions and the following disclaimer. | |||||
* 2. Redistributions in binary form must reproduce the above copyright | |||||
* notice, this list of conditions and the following disclaimer in the | |||||
* documentation and/or other materials provided with the distribution. | |||||
* | * | ||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND | * 1. Redistributions of source code must retain the above copyright notice, | ||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | * this list of conditions and the following disclaimer. | ||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | * 2. Redistributions in binary form must reproduce the above copyright notice, | ||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | * this list of conditions and the following disclaimer in the documentation | ||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | * and/or other materials provided with the distribution. | ||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |||||
* SUCH DAMAGE. | |||||
* | * | ||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; | |||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | |||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR | |||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, | |||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |||||
* | |||||
* The views and conclusions contained in the software and documentation are | |||||
* those of the authors and should not be interpreted as representing official | |||||
* policies, either expressed or implied, of the FreeBSD Project. | |||||
* | |||||
* $FreeBSD$ | * $FreeBSD$ | ||||
*/ | */ | ||||
#ifndef _SYS_EFX_EF10_REGS_H | #ifndef _SYS_EFX_EF10_REGS_H | ||||
#define _SYS_EFX_EF10_REGS_H | #define _SYS_EFX_EF10_REGS_H | ||||
#ifdef __cplusplus | #ifdef __cplusplus | ||||
extern "C" { | extern "C" { | ||||
#endif | #endif | ||||
/* | /* | ||||
* BIU_HW_REV_ID_REG(32bit): | * BIU_HW_REV_ID_REG(32bit): | ||||
* | * | ||||
*/ | */ | ||||
#define ER_DZ_BIU_HW_REV_ID_REG 0x00000000 | #define ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000 | ||||
/* hunta0=pcie_pf_bar2 */ | /* hunta0=pcie_pf_bar2 */ | ||||
#define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face | |||||
#define ERF_DZ_HW_REV_ID_LBN 0 | #define ERF_DZ_HW_REV_ID_LBN 0 | ||||
#define ERF_DZ_HW_REV_ID_WIDTH 32 | #define ERF_DZ_HW_REV_ID_WIDTH 32 | ||||
/* | /* | ||||
* BIU_MC_SFT_STATUS_REG(32bit): | * BIU_MC_SFT_STATUS_REG(32bit): | ||||
* | * | ||||
*/ | */ | ||||
#define ER_DZ_BIU_MC_SFT_STATUS_REG 0x00000010 | #define ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010 | ||||
/* hunta0=pcie_pf_bar2 */ | /* hunta0=pcie_pf_bar2 */ | ||||
#define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4 | #define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4 | ||||
#define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8 | #define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8 | ||||
#define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face | |||||
#define ERF_DZ_MC_SFT_STATUS_LBN 0 | #define ERF_DZ_MC_SFT_STATUS_LBN 0 | ||||
#define ERF_DZ_MC_SFT_STATUS_WIDTH 32 | #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 | ||||
/* | /* | ||||
* BIU_INT_ISR_REG(32bit): | * BIU_INT_ISR_REG(32bit): | ||||
* | * | ||||
*/ | */ | ||||
#define ER_DZ_BIU_INT_ISR_REG 0x00000090 | #define ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090 | ||||
/* hunta0=pcie_pf_bar2 */ | /* hunta0=pcie_pf_bar2 */ | ||||
#define ER_DZ_BIU_INT_ISR_REG_RESET 0x0 | |||||
#define ERF_DZ_ISR_REG_LBN 0 | #define ERF_DZ_ISR_REG_LBN 0 | ||||
#define ERF_DZ_ISR_REG_WIDTH 32 | #define ERF_DZ_ISR_REG_WIDTH 32 | ||||
/* | /* | ||||
* MC_DB_LWRD_REG(32bit): | * MC_DB_LWRD_REG(32bit): | ||||
* | * | ||||
*/ | */ | ||||
#define ER_DZ_MC_DB_LWRD_REG 0x00000200 | #define ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200 | ||||
/* hunta0=pcie_pf_bar2 */ | /* hunta0=pcie_pf_bar2 */ | ||||
#define ER_DZ_MC_DB_LWRD_REG_RESET 0x0 | |||||
#define ERF_DZ_MC_DOORBELL_L_LBN 0 | #define ERF_DZ_MC_DOORBELL_L_LBN 0 | ||||
#define ERF_DZ_MC_DOORBELL_L_WIDTH 32 | #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 | ||||
/* | /* | ||||
* MC_DB_HWRD_REG(32bit): | * MC_DB_HWRD_REG(32bit): | ||||
* | * | ||||
*/ | */ | ||||
#define ER_DZ_MC_DB_HWRD_REG 0x00000204 | #define ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204 | ||||
/* hunta0=pcie_pf_bar2 */ | /* hunta0=pcie_pf_bar2 */ | ||||
#define ER_DZ_MC_DB_HWRD_REG_RESET 0x0 | |||||
#define ERF_DZ_MC_DOORBELL_H_LBN 0 | #define ERF_DZ_MC_DOORBELL_H_LBN 0 | ||||
#define ERF_DZ_MC_DOORBELL_H_WIDTH 32 | #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 | ||||
/* | /* | ||||
* EVQ_RPTR_REG(32bit): | * EVQ_RPTR_REG(32bit): | ||||
* | * | ||||
*/ | */ | ||||
#define ER_DZ_EVQ_RPTR_REG 0x00000400 | #define ER_DZ_EVQ_RPTR_REG_OFST 0x00000400 | ||||
/* hunta0=pcie_pf_bar2 */ | /* hunta0=pcie_pf_bar2 */ | ||||
#define ER_DZ_EVQ_RPTR_REG_STEP 4096 | #define ER_DZ_EVQ_RPTR_REG_STEP 8192 | ||||
#define ER_DZ_EVQ_RPTR_REG_ROWS 2048 | #define ER_DZ_EVQ_RPTR_REG_ROWS 2048 | ||||
#define ER_DZ_EVQ_RPTR_REG_RESET 0x0 | |||||
#define ERF_DZ_EVQ_RPTR_VLD_LBN 15 | #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 | ||||
#define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 | #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 | ||||
#define ERF_DZ_EVQ_RPTR_LBN 0 | #define ERF_DZ_EVQ_RPTR_LBN 0 | ||||
#define ERF_DZ_EVQ_RPTR_WIDTH 15 | #define ERF_DZ_EVQ_RPTR_WIDTH 15 | ||||
/* | /* | ||||
* EVQ_TMR_REG(32bit): | * EVQ_TMR_REG(32bit): | ||||
* | * | ||||
*/ | */ | ||||
#define ER_DZ_EVQ_TMR_REG 0x00000420 | #define ER_DZ_EVQ_TMR_REG_OFST 0x00000420 | ||||
/* hunta0=pcie_pf_bar2 */ | /* hunta0=pcie_pf_bar2 */ | ||||
#define ER_DZ_EVQ_TMR_REG_STEP 4096 | #define ER_DZ_EVQ_TMR_REG_STEP 8192 | ||||
#define ER_DZ_EVQ_TMR_REG_ROWS 2048 | #define ER_DZ_EVQ_TMR_REG_ROWS 2048 | ||||
#define ER_DZ_EVQ_TMR_REG_RESET 0x0 | |||||
#define ERF_DZ_TC_TIMER_MODE_LBN 14 | #define ERF_DZ_TC_TIMER_MODE_LBN 14 | ||||
#define ERF_DZ_TC_TIMER_MODE_WIDTH 2 | #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 | ||||
#define ERF_DZ_TC_TIMER_VAL_LBN 0 | #define ERF_DZ_TC_TIMER_VAL_LBN 0 | ||||
#define ERF_DZ_TC_TIMER_VAL_WIDTH 14 | #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 | ||||
/* | /* | ||||
* RX_DESC_UPD_REG(32bit): | * RX_DESC_UPD_REG(32bit): | ||||
* | * | ||||
*/ | */ | ||||
#define ER_DZ_RX_DESC_UPD_REG 0x00000830 | #define ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830 | ||||
/* hunta0=pcie_pf_bar2 */ | /* hunta0=pcie_pf_bar2 */ | ||||
#define ER_DZ_RX_DESC_UPD_REG_STEP 4096 | #define ER_DZ_RX_DESC_UPD_REG_STEP 8192 | ||||
#define ER_DZ_RX_DESC_UPD_REG_ROWS 2048 | #define ER_DZ_RX_DESC_UPD_REG_ROWS 2048 | ||||
#define ER_DZ_RX_DESC_UPD_REG_RESET 0x0 | |||||
#define ERF_DZ_RX_DESC_WPTR_LBN 0 | #define ERF_DZ_RX_DESC_WPTR_LBN 0 | ||||
#define ERF_DZ_RX_DESC_WPTR_WIDTH 12 | #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 | ||||
/* | /* | ||||
* TX_DESC_UPD_REG(76bit): | * TX_DESC_UPD_REG(96bit): | ||||
* | * | ||||
*/ | */ | ||||
#define ER_DZ_TX_DESC_UPD_REG 0x00000a10 | #define ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10 | ||||
/* hunta0=pcie_pf_bar2 */ | /* hunta0=pcie_pf_bar2 */ | ||||
#define ER_DZ_TX_DESC_UPD_REG_STEP 4096 | #define ER_DZ_TX_DESC_UPD_REG_STEP 8192 | ||||
#define ER_DZ_TX_DESC_UPD_REG_ROWS 2048 | #define ER_DZ_TX_DESC_UPD_REG_ROWS 2048 | ||||
#define ER_DZ_TX_DESC_UPD_REG_RESET 0x0 | |||||
#define ERF_DZ_RSVD_LBN 76 | |||||
#define ERF_DZ_RSVD_WIDTH 20 | |||||
#define ERF_DZ_TX_DESC_WPTR_LBN 64 | #define ERF_DZ_TX_DESC_WPTR_LBN 64 | ||||
#define ERF_DZ_TX_DESC_WPTR_WIDTH 12 | #define ERF_DZ_TX_DESC_WPTR_WIDTH 12 | ||||
#define ERF_DZ_TX_DESC_HWORD_LBN 32 | #define ERF_DZ_TX_DESC_HWORD_LBN 32 | ||||
#define ERF_DZ_TX_DESC_HWORD_WIDTH 32 | #define ERF_DZ_TX_DESC_HWORD_WIDTH 32 | ||||
#define ERF_DZ_TX_DESC_LWORD_LBN 0 | #define ERF_DZ_TX_DESC_LWORD_LBN 0 | ||||
#define ERF_DZ_TX_DESC_LWORD_WIDTH 32 | #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 | ||||
/* | |||||
* The workaround for bug 35388 requires multiplexing writes through | |||||
* the ERF_DZ_TX_DESC_WPTR address. | |||||
* TX_DESC_UPD: 0ppppppppppp (bit 11 lost) | |||||
* EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) | |||||
* EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) | |||||
*/ | |||||
#define ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4) | |||||
#define ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP | |||||
#define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 | |||||
#define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 | |||||
#define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 | |||||
#define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 | |||||
#define ERF_DD_EVQ_IND_RPTR_LBN 0 | |||||
#define ERF_DD_EVQ_IND_RPTR_WIDTH 8 | |||||
#define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 | |||||
#define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 | |||||
#define EFE_DD_EVQ_IND_TIMER_FLAGS 3 | |||||
#define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 | |||||
#define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 | |||||
#define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 | |||||
#define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 | |||||
/* ES_DRIVER_EV */ | /* ES_DRIVER_EV */ | ||||
#define ESF_DZ_DRV_CODE_LBN 60 | #define ESF_DZ_DRV_CODE_LBN 60 | ||||
#define ESF_DZ_DRV_CODE_WIDTH 4 | #define ESF_DZ_DRV_CODE_WIDTH 4 | ||||
#define ESF_DZ_DRV_SUB_CODE_LBN 56 | #define ESF_DZ_DRV_SUB_CODE_LBN 56 | ||||
#define ESF_DZ_DRV_SUB_CODE_WIDTH 4 | #define ESF_DZ_DRV_SUB_CODE_WIDTH 4 | ||||
#define ESE_DZ_DRV_TIMER_EV 10 | #define ESE_DZ_DRV_TIMER_EV 3 | ||||
#define ESE_DZ_DRV_WAKE_UP_EV 6 | #define ESE_DZ_DRV_START_UP_EV 2 | ||||
#define ESE_DZ_DRV_WAKE_UP_EV 1 | |||||
#define ESF_DZ_DRV_SUB_DATA_DW0_LBN 0 | #define ESF_DZ_DRV_SUB_DATA_DW0_LBN 0 | ||||
#define ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32 | #define ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32 | ||||
#define ESF_DZ_DRV_SUB_DATA_DW1_LBN 32 | #define ESF_DZ_DRV_SUB_DATA_DW1_LBN 32 | ||||
#define ESF_DZ_DRV_SUB_DATA_DW1_WIDTH 24 | #define ESF_DZ_DRV_SUB_DATA_DW1_WIDTH 24 | ||||
#define ESF_DZ_DRV_SUB_DATA_LBN 0 | #define ESF_DZ_DRV_SUB_DATA_LBN 0 | ||||
#define ESF_DZ_DRV_SUB_DATA_WIDTH 56 | #define ESF_DZ_DRV_SUB_DATA_WIDTH 56 | ||||
#define ESF_DZ_DRV_EVQ_ID_LBN 0 | #define ESF_DZ_DRV_EVQ_ID_LBN 0 | ||||
#define ESF_DZ_DRV_EVQ_ID_WIDTH 14 | #define ESF_DZ_DRV_EVQ_ID_WIDTH 14 | ||||
Show All 13 Lines | |||||
#define ESF_DZ_EV_DATA_DW0_WIDTH 32 | #define ESF_DZ_EV_DATA_DW0_WIDTH 32 | ||||
#define ESF_DZ_EV_DATA_DW1_LBN 32 | #define ESF_DZ_EV_DATA_DW1_LBN 32 | ||||
#define ESF_DZ_EV_DATA_DW1_WIDTH 28 | #define ESF_DZ_EV_DATA_DW1_WIDTH 28 | ||||
#define ESF_DZ_EV_DATA_LBN 0 | #define ESF_DZ_EV_DATA_LBN 0 | ||||
#define ESF_DZ_EV_DATA_WIDTH 60 | #define ESF_DZ_EV_DATA_WIDTH 60 | ||||
/* ES_FF_UMSG_CPU2DL_DESC_FETCH */ | /* ES_FF_UMSG_CPU2DL_DESC_FETCH */ | ||||
#define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_LBN 112 | #define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_LBN 208 | ||||
#define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_WIDTH 6 | #define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_WIDTH 6 | ||||
#define ESF_DZ_C2DDF_QID_LBN 96 | #define ESF_DZ_C2DDF_QID_LBN 160 | ||||
#define ESF_DZ_C2DDF_QID_WIDTH 11 | #define ESF_DZ_C2DDF_QID_WIDTH 11 | ||||
#define ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_LBN 64 | #define ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_LBN 64 | ||||
#define ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_WIDTH 18 | #define ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_WIDTH 18 | ||||
#define ESF_DZ_C2DDF_DSCR_HW_RPTR_LBN 48 | #define ESF_DZ_C2DDF_DSCR_HW_RPTR_LBN 48 | ||||
#define ESF_DZ_C2DDF_DSCR_HW_RPTR_WIDTH 12 | #define ESF_DZ_C2DDF_DSCR_HW_RPTR_WIDTH 12 | ||||
#define ESF_DZ_C2DDF_DSCR_HW_WPTR_LBN 32 | #define ESF_DZ_C2DDF_DSCR_HW_WPTR_LBN 32 | ||||
#define ESF_DZ_C2DDF_DSCR_HW_WPTR_WIDTH 12 | #define ESF_DZ_C2DDF_DSCR_HW_WPTR_WIDTH 12 | ||||
#define ESF_DZ_C2DDF_OID_LBN 16 | #define ESF_DZ_C2DDF_OID_LBN 16 | ||||
#define ESF_DZ_C2DDF_OID_WIDTH 12 | #define ESF_DZ_C2DDF_OID_WIDTH 12 | ||||
#define ESF_DZ_C2DDF_DSCR_SIZE_LBN 13 | #define ESF_DZ_C2DDF_DSCR_SIZE_LBN 13 | ||||
#define ESF_DZ_C2DDF_DSCR_SIZE_WIDTH 3 | #define ESF_DZ_C2DDF_DSCR_SIZE_WIDTH 3 | ||||
#define ESE_DZ_C2DDF_DSCR_SIZE_512 7 | #define ESE_DZ_C2DDF_DSCR_SIZE_512 7 | ||||
#define ESE_DZ_C2DDF_DSCR_SIZE_1K 6 | #define ESE_DZ_C2DDF_DSCR_SIZE_1K 6 | ||||
#define ESE_DZ_C2DDF_DSCR_SIZE_2K 5 | #define ESE_DZ_C2DDF_DSCR_SIZE_2K 5 | ||||
#define ESE_DZ_C2DDF_DSCR_SIZE_4K 4 | #define ESE_DZ_C2DDF_DSCR_SIZE_4K 4 | ||||
#define ESF_DZ_C2DDF_BIU_ARGS_LBN 0 | #define ESF_DZ_C2DDF_BIU_ARGS_LBN 0 | ||||
#define ESF_DZ_C2DDF_BIU_ARGS_WIDTH 13 | #define ESF_DZ_C2DDF_BIU_ARGS_WIDTH 13 | ||||
/* ES_FF_UMSG_CPU2DL_DESC_PUSH */ | /* ES_FF_UMSG_CPU2DL_DESC_PUSH */ | ||||
#define ESF_DZ_C2DDP_DSCR_HW_RPTR_LBN 224 | |||||
#define ESF_DZ_C2DDP_DSCR_HW_RPTR_WIDTH 12 | |||||
#define ESF_DZ_C2DDP_DESC_DW0_LBN 128 | #define ESF_DZ_C2DDP_DESC_DW0_LBN 128 | ||||
#define ESF_DZ_C2DDP_DESC_DW0_WIDTH 32 | #define ESF_DZ_C2DDP_DESC_DW0_WIDTH 32 | ||||
#define ESF_DZ_C2DDP_DESC_DW1_LBN 160 | #define ESF_DZ_C2DDP_DESC_DW1_LBN 160 | ||||
#define ESF_DZ_C2DDP_DESC_DW1_WIDTH 32 | #define ESF_DZ_C2DDP_DESC_DW1_WIDTH 32 | ||||
#define ESF_DZ_C2DDP_DESC_LBN 128 | #define ESF_DZ_C2DDP_DESC_LBN 128 | ||||
#define ESF_DZ_C2DDP_DESC_WIDTH 64 | #define ESF_DZ_C2DDP_DESC_WIDTH 64 | ||||
#define ESF_DZ_C2DDP_QID_LBN 96 | #define ESF_DZ_C2DDP_QID_LBN 64 | ||||
#define ESF_DZ_C2DDP_QID_WIDTH 11 | #define ESF_DZ_C2DDP_QID_WIDTH 11 | ||||
#define ESF_DZ_C2DDP_DSCR_HW_RPTR_LBN 48 | |||||
#define ESF_DZ_C2DDP_DSCR_HW_RPTR_WIDTH 12 | |||||
#define ESF_DZ_C2DDP_DSCR_HW_WPTR_LBN 32 | #define ESF_DZ_C2DDP_DSCR_HW_WPTR_LBN 32 | ||||
#define ESF_DZ_C2DDP_DSCR_HW_WPTR_WIDTH 12 | #define ESF_DZ_C2DDP_DSCR_HW_WPTR_WIDTH 12 | ||||
#define ESF_DZ_C2DDP_OID_LBN 16 | #define ESF_DZ_C2DDP_OID_LBN 16 | ||||
#define ESF_DZ_C2DDP_OID_WIDTH 12 | #define ESF_DZ_C2DDP_OID_WIDTH 12 | ||||
#define ESF_DZ_C2DDP_DSCR_SIZE_LBN 0 | #define ESF_DZ_C2DDP_DSCR_SIZE_LBN 0 | ||||
#define ESF_DZ_C2DDP_DSCR_SIZE_WIDTH 3 | #define ESF_DZ_C2DDP_DSCR_SIZE_WIDTH 3 | ||||
#define ESE_DZ_C2DDF_DSCR_SIZE_512 7 | #define ESE_DZ_C2DDF_DSCR_SIZE_512 7 | ||||
#define ESE_DZ_C2DDF_DSCR_SIZE_1K 6 | #define ESE_DZ_C2DDF_DSCR_SIZE_1K 6 | ||||
Show All 15 Lines | |||||
/* ES_FF_UMSG_CPU2EV_SOFT */ | /* ES_FF_UMSG_CPU2EV_SOFT */ | ||||
#define ESF_DZ_C2ES_TBD_LBN 0 | #define ESF_DZ_C2ES_TBD_LBN 0 | ||||
#define ESF_DZ_C2ES_TBD_WIDTH 1 | #define ESF_DZ_C2ES_TBD_WIDTH 1 | ||||
/* ES_FF_UMSG_CPU2EV_TXCMPLT */ | /* ES_FF_UMSG_CPU2EV_TXCMPLT */ | ||||
#define ESF_DZ_C2ET_EV_SOFT0_LBN 32 | #define ESF_DZ_C2ET_EV_SOFT2_LBN 48 | ||||
#define ESF_DZ_C2ET_EV_SOFT0_WIDTH 16 | #define ESF_DZ_C2ET_EV_SOFT2_WIDTH 16 | ||||
#define ESF_DZ_C2ET_EV_CODE_LBN 42 | |||||
#define ESF_DZ_C2ET_EV_CODE_WIDTH 4 | |||||
#define ESF_DZ_C2ET_EV_OVERRIDE_HOLDOFF_LBN 41 | |||||
#define ESF_DZ_C2ET_EV_OVERRIDE_HOLDOFF_WIDTH 1 | |||||
#define ESF_DZ_C2ET_EV_DROP_EVENT_LBN 40 | |||||
#define ESF_DZ_C2ET_EV_DROP_EVENT_WIDTH 1 | |||||
#define ESF_DZ_C2ET_EV_CAN_MERGE_LBN 39 | |||||
#define ESF_DZ_C2ET_EV_CAN_MERGE_WIDTH 1 | |||||
#define ESF_DZ_C2ET_EV_SOFT1_LBN 32 | |||||
#define ESF_DZ_C2ET_EV_SOFT1_WIDTH 7 | |||||
#define ESF_DZ_C2ET_DSCR_IDX_LBN 16 | #define ESF_DZ_C2ET_DSCR_IDX_LBN 16 | ||||
#define ESF_DZ_C2ET_DSCR_IDX_WIDTH 16 | #define ESF_DZ_C2ET_DSCR_IDX_WIDTH 16 | ||||
#define ESF_DZ_C2ET_EV_QID_LBN 5 | #define ESF_DZ_C2ET_EV_QID_LBN 5 | ||||
#define ESF_DZ_C2ET_EV_QID_WIDTH 11 | #define ESF_DZ_C2ET_EV_QID_WIDTH 11 | ||||
#define ESF_DZ_C2ET_EV_QLABEL_LBN 0 | #define ESF_DZ_C2ET_EV_QLABEL_LBN 0 | ||||
#define ESF_DZ_C2ET_EV_QLABEL_WIDTH 5 | #define ESF_DZ_C2ET_EV_QLABEL_WIDTH 5 | ||||
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#define ESF_DZ_C2RIP_EV_SOFT_LBN 188 | #define ESF_DZ_C2RIP_EV_SOFT_LBN 188 | ||||
#define ESF_DZ_C2RIP_EV_SOFT_WIDTH 3 | #define ESF_DZ_C2RIP_EV_SOFT_WIDTH 3 | ||||
#define ESF_DZ_C2RIP_EV_DESC_PTR_LBN 176 | #define ESF_DZ_C2RIP_EV_DESC_PTR_LBN 176 | ||||
#define ESF_DZ_C2RIP_EV_DESC_PTR_WIDTH 12 | #define ESF_DZ_C2RIP_EV_DESC_PTR_WIDTH 12 | ||||
#define ESF_DZ_C2RIP_EV_ARG1_LBN 160 | #define ESF_DZ_C2RIP_EV_ARG1_LBN 160 | ||||
#define ESF_DZ_C2RIP_EV_ARG1_WIDTH 16 | #define ESF_DZ_C2RIP_EV_ARG1_WIDTH 16 | ||||
#define ESF_DZ_C2RIP_UPD_CRC_MODE_LBN 157 | #define ESF_DZ_C2RIP_UPD_CRC_MODE_LBN 157 | ||||
#define ESF_DZ_C2RIP_UPD_CRC_MODE_WIDTH 3 | #define ESF_DZ_C2RIP_UPD_CRC_MODE_WIDTH 3 | ||||
#define ESE_DZ_C2RIP_FCOIP_MPA 5 | |||||
#define ESE_DZ_C2RIP_FCOIP_FCOE 4 | #define ESE_DZ_C2RIP_FCOIP_FCOE 4 | ||||
#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 | #define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 | ||||
#define ESE_DZ_C2RIP_ISCSI_HDR 2 | #define ESE_DZ_C2RIP_ISCSI_HDR 2 | ||||
#define ESE_DZ_C2RIP_FCOE 1 | #define ESE_DZ_C2RIP_FCOE 1 | ||||
#define ESE_DZ_C2RIP_OFF 0 | #define ESE_DZ_C2RIP_OFF 0 | ||||
#define ESF_DZ_C2RIP_BIU_ARGS_LBN 144 | #define ESF_DZ_C2RIP_BIU_ARGS_LBN 144 | ||||
#define ESF_DZ_C2RIP_BIU_ARGS_WIDTH 13 | #define ESF_DZ_C2RIP_BIU_ARGS_WIDTH 13 | ||||
#define ESF_DZ_C2RIP_EV_QID_LBN 133 | #define ESF_DZ_C2RIP_EV_QID_LBN 133 | ||||
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines | |||||
#define ESF_DZ_C2SD_LEN_LBN 112 | #define ESF_DZ_C2SD_LEN_LBN 112 | ||||
#define ESF_DZ_C2SD_LEN_WIDTH 14 | #define ESF_DZ_C2SD_LEN_WIDTH 14 | ||||
#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW0_LBN 64 | #define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW0_LBN 64 | ||||
#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW0_WIDTH 32 | #define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW0_WIDTH 32 | ||||
#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_LBN 96 | #define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_LBN 96 | ||||
#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_WIDTH 16 | #define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_WIDTH 16 | ||||
#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_LBN 64 | #define ESF_DZ_C2SD_ENCODED_HOST_ADDR_LBN 64 | ||||
#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_WIDTH 48 | #define ESF_DZ_C2SD_ENCODED_HOST_ADDR_WIDTH 48 | ||||
#define ESF_DZ_C2SD_OFFSET_LBN 48 | #define ESF_DZ_C2SD_OFFSET_LBN 80 | ||||
#define ESF_DZ_C2SD_OFFSET_WIDTH 8 | #define ESF_DZ_C2SD_OFFSET_WIDTH 8 | ||||
#define ESF_DZ_C2SD_QID_LBN 32 | #define ESF_DZ_C2SD_QID_LBN 32 | ||||
#define ESF_DZ_C2SD_QID_WIDTH 11 | #define ESF_DZ_C2SD_QID_WIDTH 11 | ||||
#define ESF_DZ_C2SD_CONT_LBN 16 | #define ESF_DZ_C2SD_CONT_LBN 16 | ||||
#define ESF_DZ_C2SD_CONT_WIDTH 1 | #define ESF_DZ_C2SD_CONT_WIDTH 1 | ||||
#define ESF_DZ_C2SD_TYPE_LBN 0 | #define ESF_DZ_C2SD_TYPE_LBN 0 | ||||
#define ESF_DZ_C2SD_TYPE_WIDTH 1 | #define ESF_DZ_C2SD_TYPE_WIDTH 1 | ||||
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#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_LBN 128 | #define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_LBN 128 | ||||
#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_WIDTH 48 | #define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_WIDTH 48 | ||||
#define ESF_DZ_C2TDB_SOFT_LBN 112 | #define ESF_DZ_C2TDB_SOFT_LBN 112 | ||||
#define ESF_DZ_C2TDB_SOFT_WIDTH 14 | #define ESF_DZ_C2TDB_SOFT_WIDTH 14 | ||||
#define ESF_DZ_C2TDB_DESC_IDX_LBN 96 | #define ESF_DZ_C2TDB_DESC_IDX_LBN 96 | ||||
#define ESF_DZ_C2TDB_DESC_IDX_WIDTH 16 | #define ESF_DZ_C2TDB_DESC_IDX_WIDTH 16 | ||||
#define ESF_DZ_C2TDB_UPD_CRC_MODE_LBN 93 | #define ESF_DZ_C2TDB_UPD_CRC_MODE_LBN 93 | ||||
#define ESF_DZ_C2TDB_UPD_CRC_MODE_WIDTH 3 | #define ESF_DZ_C2TDB_UPD_CRC_MODE_WIDTH 3 | ||||
#define ESE_DZ_C2RIP_FCOIP_MPA 5 | |||||
#define ESE_DZ_C2RIP_FCOIP_FCOE 4 | #define ESE_DZ_C2RIP_FCOIP_FCOE 4 | ||||
#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 | #define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 | ||||
#define ESE_DZ_C2RIP_ISCSI_HDR 2 | #define ESE_DZ_C2RIP_ISCSI_HDR 2 | ||||
#define ESE_DZ_C2RIP_FCOE 1 | #define ESE_DZ_C2RIP_FCOE 1 | ||||
#define ESE_DZ_C2RIP_OFF 0 | #define ESE_DZ_C2RIP_OFF 0 | ||||
#define ESF_DZ_C2TDB_BIU_ARGS_LBN 80 | #define ESF_DZ_C2TDB_BIU_ARGS_LBN 80 | ||||
#define ESF_DZ_C2TDB_BIU_ARGS_WIDTH 13 | #define ESF_DZ_C2TDB_BIU_ARGS_WIDTH 13 | ||||
#define ESF_DZ_C2TDB_CONT_LBN 64 | #define ESF_DZ_C2TDB_CONT_LBN 64 | ||||
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#define ESF_DZ_C2TDS_SOFT2_WIDTH 16 | #define ESF_DZ_C2TDS_SOFT2_WIDTH 16 | ||||
#define ESF_DZ_C2TDS_SOFT1_LBN 16 | #define ESF_DZ_C2TDS_SOFT1_LBN 16 | ||||
#define ESF_DZ_C2TDS_SOFT1_WIDTH 16 | #define ESF_DZ_C2TDS_SOFT1_WIDTH 16 | ||||
#define ESF_DZ_C2TDS_SOFT0_LBN 0 | #define ESF_DZ_C2TDS_SOFT0_LBN 0 | ||||
#define ESF_DZ_C2TDS_SOFT0_WIDTH 16 | #define ESF_DZ_C2TDS_SOFT0_WIDTH 16 | ||||
/* ES_FF_UMSG_CPU2TXDP_EGR */ | /* ES_FF_UMSG_CPU2TXDP_EGR */ | ||||
#define ESF_DZ_C2TE_RMON_SOFT_LBN 240 | |||||
#define ESF_DZ_C2TE_RMON_SOFT_WIDTH 1 | |||||
#define ESF_DZ_C2TE_VLAN_PRIO_LBN 224 | |||||
#define ESF_DZ_C2TE_VLAN_PRIO_WIDTH 3 | |||||
#define ESF_DZ_C2TE_VLAN_LBN 208 | |||||
#define ESF_DZ_C2TE_VLAN_WIDTH 1 | |||||
#define ESF_DZ_C2TE_QID_LBN 192 | |||||
#define ESF_DZ_C2TE_QID_WIDTH 11 | |||||
#define ESF_DZ_C2TE_PEDIT_DELTA_LBN 168 | #define ESF_DZ_C2TE_PEDIT_DELTA_LBN 168 | ||||
#define ESF_DZ_C2TE_PEDIT_DELTA_WIDTH 8 | #define ESF_DZ_C2TE_PEDIT_DELTA_WIDTH 8 | ||||
#define ESF_DZ_C2TE_PYLOAD_OFST_LBN 160 | #define ESF_DZ_C2TE_PYLOAD_OFST_LBN 160 | ||||
#define ESF_DZ_C2TE_PYLOAD_OFST_WIDTH 8 | #define ESF_DZ_C2TE_PYLOAD_OFST_WIDTH 8 | ||||
#define ESF_DZ_C2TE_L4_HDR_OFST_LBN 152 | #define ESF_DZ_C2TE_L4_HDR_OFST_LBN 152 | ||||
#define ESF_DZ_C2TE_L4_HDR_OFST_WIDTH 8 | #define ESF_DZ_C2TE_L4_HDR_OFST_WIDTH 8 | ||||
#define ESF_DZ_C2TE_L3_HDR_OFST_LBN 144 | #define ESF_DZ_C2TE_L3_HDR_OFST_LBN 144 | ||||
#define ESF_DZ_C2TE_L3_HDR_OFST_WIDTH 8 | #define ESF_DZ_C2TE_L3_HDR_OFST_WIDTH 8 | ||||
#define ESF_DZ_C2TE_IS_UDP_LBN 133 | #define ESF_DZ_C2TE_IS_UDP_LBN 133 | ||||
#define ESF_DZ_C2TE_IS_UDP_WIDTH 1 | #define ESF_DZ_C2TE_IS_UDP_WIDTH 1 | ||||
#define ESF_DZ_C2TE_IS_TCP_LBN 132 | #define ESF_DZ_C2TE_IS_TCP_LBN 132 | ||||
#define ESF_DZ_C2TE_IS_TCP_WIDTH 1 | #define ESF_DZ_C2TE_IS_TCP_WIDTH 1 | ||||
#define ESF_DZ_C2TE_IS_IPV6_LBN 131 | #define ESF_DZ_C2TE_IS_IPV6_LBN 131 | ||||
#define ESF_DZ_C2TE_IS_IPV6_WIDTH 1 | #define ESF_DZ_C2TE_IS_IPV6_WIDTH 1 | ||||
#define ESF_DZ_C2TE_IS_IPV4_LBN 130 | #define ESF_DZ_C2TE_IS_IPV4_LBN 130 | ||||
#define ESF_DZ_C2TE_IS_IPV4_WIDTH 1 | #define ESF_DZ_C2TE_IS_IPV4_WIDTH 1 | ||||
#define ESF_DZ_C2TE_IS_FCOE_LBN 129 | #define ESF_DZ_C2TE_IS_FCOE_LBN 129 | ||||
#define ESF_DZ_C2TE_IS_FCOE_WIDTH 1 | #define ESF_DZ_C2TE_IS_FCOE_WIDTH 1 | ||||
#define ESF_DZ_C2TE_PARSE_INCOMP_LBN 128 | #define ESF_DZ_C2TE_PARSE_INCOMP_LBN 128 | ||||
#define ESF_DZ_C2TE_PARSE_INCOMP_WIDTH 1 | #define ESF_DZ_C2TE_PARSE_INCOMP_WIDTH 1 | ||||
#define ESF_DZ_C2TE_PKT_LEN_LBN 112 | #define ESF_DZ_C2TE_UPD_CRC_MODE_LBN 98 | ||||
#define ESF_DZ_C2TE_PKT_LEN_WIDTH 16 | |||||
#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_LBN 97 | |||||
#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_WIDTH 1 | |||||
#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_LBN 96 | |||||
#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_WIDTH 1 | |||||
#define ESF_DZ_C2TE_UPD_CRC_MODE_LBN 93 | |||||
#define ESF_DZ_C2TE_UPD_CRC_MODE_WIDTH 3 | #define ESF_DZ_C2TE_UPD_CRC_MODE_WIDTH 3 | ||||
#define ESE_DZ_C2RIP_FCOIP_MPA 5 | |||||
#define ESE_DZ_C2RIP_FCOIP_FCOE 4 | #define ESE_DZ_C2RIP_FCOIP_FCOE 4 | ||||
#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 | #define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 | ||||
#define ESE_DZ_C2RIP_ISCSI_HDR 2 | #define ESE_DZ_C2RIP_ISCSI_HDR 2 | ||||
#define ESE_DZ_C2RIP_FCOE 1 | #define ESE_DZ_C2RIP_FCOE 1 | ||||
#define ESE_DZ_C2RIP_OFF 0 | #define ESE_DZ_C2RIP_OFF 0 | ||||
#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_LBN 97 | |||||
#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_WIDTH 1 | |||||
#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_LBN 96 | |||||
#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_WIDTH 1 | |||||
#define ESF_DZ_C2TE_PKT_LEN_LBN 64 | |||||
#define ESF_DZ_C2TE_PKT_LEN_WIDTH 16 | |||||
#define ESF_DZ_C2TE_FINFO_WRD3_LBN 48 | #define ESF_DZ_C2TE_FINFO_WRD3_LBN 48 | ||||
#define ESF_DZ_C2TE_FINFO_WRD3_WIDTH 16 | #define ESF_DZ_C2TE_FINFO_WRD3_WIDTH 16 | ||||
#define ESF_DZ_C2TE_FINFO_WRD2_LBN 32 | #define ESF_DZ_C2TE_FINFO_WRD2_LBN 32 | ||||
#define ESF_DZ_C2TE_FINFO_WRD2_WIDTH 16 | #define ESF_DZ_C2TE_FINFO_WRD2_WIDTH 16 | ||||
#define ESF_DZ_C2TE_FINFO_WRD1_LBN 16 | #define ESF_DZ_C2TE_FINFO_WRD1_LBN 16 | ||||
#define ESF_DZ_C2TE_FINFO_WRD1_WIDTH 16 | #define ESF_DZ_C2TE_FINFO_WRD1_WIDTH 16 | ||||
#define ESF_DZ_C2TE_FINFO_SRCDST_LBN 0 | #define ESF_DZ_C2TE_FINFO_SRCDST_LBN 0 | ||||
#define ESF_DZ_C2TE_FINFO_SRCDST_WIDTH 16 | #define ESF_DZ_C2TE_FINFO_SRCDST_WIDTH 16 | ||||
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#define ESF_DZ_FRM_LEN_LBN 16 | #define ESF_DZ_FRM_LEN_LBN 16 | ||||
#define ESF_DZ_FRM_LEN_WIDTH 15 | #define ESF_DZ_FRM_LEN_WIDTH 15 | ||||
#define ESF_DZ_TXQ_ID_LBN 0 | #define ESF_DZ_TXQ_ID_LBN 0 | ||||
#define ESF_DZ_TXQ_ID_WIDTH 10 | #define ESF_DZ_TXQ_ID_WIDTH 10 | ||||
/* ES_FF_UMSG_PACER_BKT_TBL_RD_REQ */ | /* ES_FF_UMSG_PACER_BKT_TBL_RD_REQ */ | ||||
#define ESF_DZ_BKT_ID_LBN 0 | #define ESF_DZ_BKT_ID_LBN 0 | ||||
#define ESF_DZ_BKT_ID_WIDTH 9 | #define ESF_DZ_BKT_ID_WIDTH 10 | ||||
/* ES_FF_UMSG_PACER_BKT_TBL_RD_RSP */ | /* ES_FF_UMSG_PACER_BKT_TBL_RD_RSP */ | ||||
#define ESF_DZ_DUE_TIME_LBN 80 | #define ESF_DZ_DUE_TIME_LBN 80 | ||||
#define ESF_DZ_DUE_TIME_WIDTH 16 | #define ESF_DZ_DUE_TIME_WIDTH 16 | ||||
#define ESF_DZ_LAST_FILL_TIME_LBN 64 | #define ESF_DZ_LAST_FILL_TIME_LBN 64 | ||||
#define ESF_DZ_LAST_FILL_TIME_WIDTH 16 | #define ESF_DZ_LAST_FILL_TIME_WIDTH 16 | ||||
#define ESF_DZ_RATE_REC_LBN 48 | #define ESF_DZ_RATE_REC_LBN 48 | ||||
#define ESF_DZ_RATE_REC_WIDTH 16 | #define ESF_DZ_RATE_REC_WIDTH 16 | ||||
#define ESF_DZ_RATE_LBN 32 | #define ESF_DZ_RATE_LBN 32 | ||||
#define ESF_DZ_RATE_WIDTH 16 | #define ESF_DZ_RATE_WIDTH 16 | ||||
#define ESF_DZ_FILL_LEVEL_LBN 16 | #define ESF_DZ_FILL_LEVEL_LBN 16 | ||||
#define ESF_DZ_FILL_LEVEL_WIDTH 16 | #define ESF_DZ_FILL_LEVEL_WIDTH 16 | ||||
#define ESF_DZ_IDLE_LBN 15 | #define ESF_DZ_IDLE_LBN 15 | ||||
#define ESF_DZ_IDLE_WIDTH 1 | #define ESF_DZ_IDLE_WIDTH 1 | ||||
#define ESF_DZ_USED_LBN 14 | #define ESF_DZ_USED_LBN 14 | ||||
#define ESF_DZ_USED_WIDTH 1 | #define ESF_DZ_USED_WIDTH 1 | ||||
#define ESF_DZ_MAX_FILL_REG_LBN 12 | #define ESF_DZ_MAX_FILL_REG_LBN 12 | ||||
#define ESF_DZ_MAX_FILL_REG_WIDTH 2 | #define ESF_DZ_MAX_FILL_REG_WIDTH 2 | ||||
#define ESF_DZ_BKT_ID_LBN 0 | #define ESF_DZ_BKT_ID_LBN 0 | ||||
#define ESF_DZ_BKT_ID_WIDTH 9 | #define ESF_DZ_BKT_ID_WIDTH 10 | ||||
/* ES_FF_UMSG_PACER_BKT_TBL_WR_REQ */ | /* ES_FF_UMSG_PACER_BKT_TBL_WR_REQ */ | ||||
#define ESF_DZ_RATE_REC_LBN 48 | #define ESF_DZ_RATE_REC_LBN 48 | ||||
#define ESF_DZ_RATE_REC_WIDTH 16 | #define ESF_DZ_RATE_REC_WIDTH 16 | ||||
#define ESF_DZ_RATE_LBN 32 | #define ESF_DZ_RATE_LBN 32 | ||||
#define ESF_DZ_RATE_WIDTH 16 | #define ESF_DZ_RATE_WIDTH 16 | ||||
#define ESF_DZ_FILL_LEVEL_LBN 16 | #define ESF_DZ_FILL_LEVEL_LBN 16 | ||||
#define ESF_DZ_FILL_LEVEL_WIDTH 16 | #define ESF_DZ_FILL_LEVEL_WIDTH 16 | ||||
#define ESF_DZ_IDLE_LBN 15 | #define ESF_DZ_IDLE_LBN 15 | ||||
#define ESF_DZ_IDLE_WIDTH 1 | #define ESF_DZ_IDLE_WIDTH 1 | ||||
#define ESF_DZ_USED_LBN 14 | #define ESF_DZ_USED_LBN 14 | ||||
#define ESF_DZ_USED_WIDTH 1 | #define ESF_DZ_USED_WIDTH 1 | ||||
#define ESF_DZ_MAX_FILL_REG_LBN 12 | #define ESF_DZ_MAX_FILL_REG_LBN 12 | ||||
#define ESF_DZ_MAX_FILL_REG_WIDTH 2 | #define ESF_DZ_MAX_FILL_REG_WIDTH 2 | ||||
#define ESF_DZ_BKT_ID_LBN 0 | #define ESF_DZ_BKT_ID_LBN 0 | ||||
#define ESF_DZ_BKT_ID_WIDTH 9 | #define ESF_DZ_BKT_ID_WIDTH 10 | ||||
/* ES_FF_UMSG_PACER_TXQ_TBL_RD_REQ */ | /* ES_FF_UMSG_PACER_TXQ_TBL_RD_REQ */ | ||||
#define ESF_DZ_TXQ_ID_LBN 0 | #define ESF_DZ_TXQ_ID_LBN 0 | ||||
#define ESF_DZ_TXQ_ID_WIDTH 10 | #define ESF_DZ_TXQ_ID_WIDTH 10 | ||||
/* ES_FF_UMSG_PACER_TXQ_TBL_RD_RSP */ | /* ES_FF_UMSG_PACER_TXQ_TBL_RD_RSP */ | ||||
#define ESF_DZ_MAX_BKT2_LBN 112 | #define ESF_DZ_MAX_BKT2_LBN 112 | ||||
#define ESF_DZ_MAX_BKT2_WIDTH 9 | #define ESF_DZ_MAX_BKT2_WIDTH 10 | ||||
#define ESF_DZ_MAX_BKT1_LBN 96 | #define ESF_DZ_MAX_BKT1_LBN 96 | ||||
#define ESF_DZ_MAX_BKT1_WIDTH 9 | #define ESF_DZ_MAX_BKT1_WIDTH 10 | ||||
#define ESF_DZ_MAX_BKT0_LBN 80 | #define ESF_DZ_MAX_BKT0_LBN 80 | ||||
#define ESF_DZ_MAX_BKT0_WIDTH 9 | #define ESF_DZ_MAX_BKT0_WIDTH 10 | ||||
#define ESF_DZ_MIN_BKT_LBN 64 | #define ESF_DZ_MIN_BKT_LBN 64 | ||||
#define ESF_DZ_MIN_BKT_WIDTH 9 | #define ESF_DZ_MIN_BKT_WIDTH 10 | ||||
#define ESF_DZ_LABEL_LBN 48 | #define ESF_DZ_LABEL_LBN 48 | ||||
#define ESF_DZ_LABEL_WIDTH 4 | #define ESF_DZ_LABEL_WIDTH 4 | ||||
#define ESF_DZ_PQ_FLAGS_LBN 32 | #define ESF_DZ_PQ_FLAGS_LBN 32 | ||||
#define ESF_DZ_PQ_FLAGS_WIDTH 3 | #define ESF_DZ_PQ_FLAGS_WIDTH 3 | ||||
#define ESF_DZ_DSBL_LBN 16 | #define ESF_DZ_DSBL_LBN 16 | ||||
#define ESF_DZ_DSBL_WIDTH 1 | #define ESF_DZ_DSBL_WIDTH 1 | ||||
#define ESF_DZ_TXQ_ID_LBN 0 | #define ESF_DZ_TXQ_ID_LBN 0 | ||||
#define ESF_DZ_TXQ_ID_WIDTH 10 | #define ESF_DZ_TXQ_ID_WIDTH 10 | ||||
/* ES_FF_UMSG_PACER_TXQ_TBL_WR_REQ */ | /* ES_FF_UMSG_PACER_TXQ_TBL_WR_REQ */ | ||||
#define ESF_DZ_MAX_BKT2_LBN 112 | #define ESF_DZ_MAX_BKT2_LBN 112 | ||||
#define ESF_DZ_MAX_BKT2_WIDTH 9 | #define ESF_DZ_MAX_BKT2_WIDTH 10 | ||||
#define ESF_DZ_MAX_BKT1_LBN 96 | #define ESF_DZ_MAX_BKT1_LBN 96 | ||||
#define ESF_DZ_MAX_BKT1_WIDTH 9 | #define ESF_DZ_MAX_BKT1_WIDTH 10 | ||||
#define ESF_DZ_MAX_BKT0_LBN 80 | #define ESF_DZ_MAX_BKT0_LBN 80 | ||||
#define ESF_DZ_MAX_BKT0_WIDTH 9 | #define ESF_DZ_MAX_BKT0_WIDTH 10 | ||||
#define ESF_DZ_MIN_BKT_LBN 64 | #define ESF_DZ_MIN_BKT_LBN 64 | ||||
#define ESF_DZ_MIN_BKT_WIDTH 9 | #define ESF_DZ_MIN_BKT_WIDTH 10 | ||||
#define ESF_DZ_LABEL_LBN 48 | #define ESF_DZ_LABEL_LBN 48 | ||||
#define ESF_DZ_LABEL_WIDTH 4 | #define ESF_DZ_LABEL_WIDTH 4 | ||||
#define ESF_DZ_PQ_FLAGS_LBN 32 | #define ESF_DZ_PQ_FLAGS_LBN 32 | ||||
#define ESF_DZ_PQ_FLAGS_WIDTH 3 | #define ESF_DZ_PQ_FLAGS_WIDTH 3 | ||||
#define ESF_DZ_DSBL_LBN 16 | #define ESF_DZ_DSBL_LBN 16 | ||||
#define ESF_DZ_DSBL_WIDTH 1 | #define ESF_DZ_DSBL_WIDTH 1 | ||||
#define ESF_DZ_TXQ_ID_LBN 0 | #define ESF_DZ_TXQ_ID_LBN 0 | ||||
#define ESF_DZ_TXQ_ID_WIDTH 10 | #define ESF_DZ_TXQ_ID_WIDTH 10 | ||||
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#define ESF_DZ_RE2CS_SOFT2_WIDTH 16 | #define ESF_DZ_RE2CS_SOFT2_WIDTH 16 | ||||
#define ESF_DZ_RE2CS_SOFT1_LBN 16 | #define ESF_DZ_RE2CS_SOFT1_LBN 16 | ||||
#define ESF_DZ_RE2CS_SOFT1_WIDTH 16 | #define ESF_DZ_RE2CS_SOFT1_WIDTH 16 | ||||
#define ESF_DZ_RE2CS_SOFT0_LBN 0 | #define ESF_DZ_RE2CS_SOFT0_LBN 0 | ||||
#define ESF_DZ_RE2CS_SOFT0_WIDTH 16 | #define ESF_DZ_RE2CS_SOFT0_WIDTH 16 | ||||
/* ES_FF_UMSG_RXDP_INGR2CPU */ | /* ES_FF_UMSG_RXDP_INGR2CPU */ | ||||
#define ESF_DZ_RI2C_QUEUE_ID_LBN 224 | |||||
#define ESF_DZ_RI2C_QUEUE_ID_WIDTH 11 | |||||
#define ESF_DZ_RI2C_LEN_LBN 208 | #define ESF_DZ_RI2C_LEN_LBN 208 | ||||
#define ESF_DZ_RI2C_LEN_WIDTH 16 | #define ESF_DZ_RI2C_LEN_WIDTH 16 | ||||
#define ESF_DZ_RI2C_L4_CLASS_LBN 202 | #define ESF_DZ_RI2C_L4_CLASS_LBN 205 | ||||
#define ESF_DZ_RI2C_L4_CLASS_WIDTH 3 | #define ESF_DZ_RI2C_L4_CLASS_WIDTH 3 | ||||
#define ESF_DZ_RI2C_L3_CLASS_LBN 199 | #define ESF_DZ_RI2C_L3_CLASS_LBN 202 | ||||
#define ESF_DZ_RI2C_L3_CLASS_WIDTH 3 | #define ESF_DZ_RI2C_L3_CLASS_WIDTH 3 | ||||
#define ESF_DZ_RI2C_ETHTAG_CLASS_LBN 196 | #define ESF_DZ_RI2C_ETHTAG_CLASS_LBN 199 | ||||
#define ESF_DZ_RI2C_ETHTAG_CLASS_WIDTH 3 | #define ESF_DZ_RI2C_ETHTAG_CLASS_WIDTH 3 | ||||
#define ESF_DZ_RI2C_ETHBASE_CLASS_LBN 193 | #define ESF_DZ_RI2C_ETHBASE_CLASS_LBN 196 | ||||
#define ESF_DZ_RI2C_ETHBASE_CLASS_WIDTH 3 | #define ESF_DZ_RI2C_ETHBASE_CLASS_WIDTH 3 | ||||
#define ESF_DZ_RI2C_MAC_CLASS_LBN 192 | #define ESF_DZ_RI2C_MAC_CLASS_LBN 195 | ||||
#define ESF_DZ_RI2C_MAC_CLASS_WIDTH 1 | #define ESF_DZ_RI2C_MAC_CLASS_WIDTH 1 | ||||
#define ESF_DZ_RI2C_PKT_OFST_LBN 176 | #define ESF_DZ_RI2C_PKT_OFST_LBN 176 | ||||
#define ESF_DZ_RI2C_PKT_OFST_WIDTH 16 | #define ESF_DZ_RI2C_PKT_OFST_WIDTH 16 | ||||
#define ESF_DZ_RI2C_PEDIT_DELTA_LBN 168 | #define ESF_DZ_RI2C_PEDIT_DELTA_LBN 168 | ||||
#define ESF_DZ_RI2C_PEDIT_DELTA_WIDTH 8 | #define ESF_DZ_RI2C_PEDIT_DELTA_WIDTH 8 | ||||
#define ESF_DZ_RI2C_PYLOAD_OFST_LBN 160 | #define ESF_DZ_RI2C_PYLOAD_OFST_LBN 160 | ||||
#define ESF_DZ_RI2C_PYLOAD_OFST_WIDTH 8 | #define ESF_DZ_RI2C_PYLOAD_OFST_WIDTH 8 | ||||
#define ESF_DZ_RI2C_L4_HDR_OFST_LBN 152 | #define ESF_DZ_RI2C_L4_HDR_OFST_LBN 152 | ||||
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines | |||||
#define ESF_DZ_TD2CP_L3_CLASS_LBN 247 | #define ESF_DZ_TD2CP_L3_CLASS_LBN 247 | ||||
#define ESF_DZ_TD2CP_L3_CLASS_WIDTH 3 | #define ESF_DZ_TD2CP_L3_CLASS_WIDTH 3 | ||||
#define ESF_DZ_TD2CP_ETHTAG_CLASS_LBN 244 | #define ESF_DZ_TD2CP_ETHTAG_CLASS_LBN 244 | ||||
#define ESF_DZ_TD2CP_ETHTAG_CLASS_WIDTH 3 | #define ESF_DZ_TD2CP_ETHTAG_CLASS_WIDTH 3 | ||||
#define ESF_DZ_TD2CP_ETHBASE_CLASS_LBN 241 | #define ESF_DZ_TD2CP_ETHBASE_CLASS_LBN 241 | ||||
#define ESF_DZ_TD2CP_ETHBASE_CLASS_WIDTH 3 | #define ESF_DZ_TD2CP_ETHBASE_CLASS_WIDTH 3 | ||||
#define ESF_DZ_TD2CP_MAC_CLASS_LBN 240 | #define ESF_DZ_TD2CP_MAC_CLASS_LBN 240 | ||||
#define ESF_DZ_TD2CP_MAC_CLASS_WIDTH 1 | #define ESF_DZ_TD2CP_MAC_CLASS_WIDTH 1 | ||||
#define ESF_DZ_TD2CP_SOFT_LBN 226 | #define ESF_DZ_TD2CP_PCIE_ERR_OR_ABORT_LBN 239 | ||||
#define ESF_DZ_TD2CP_SOFT_WIDTH 14 | #define ESF_DZ_TD2CP_PCIE_ERR_OR_ABORT_WIDTH 1 | ||||
#define ESF_DZ_TD2CP_PKT_ABORT_LBN 225 | #define ESF_DZ_TD2CP_PKT_ABORT_LBN 238 | ||||
#define ESF_DZ_TD2CP_PKT_ABORT_WIDTH 1 | #define ESF_DZ_TD2CP_PKT_ABORT_WIDTH 1 | ||||
#define ESF_DZ_TD2CP_PCIE_ERR_LBN 224 | #define ESF_DZ_TD2CP_SOFT_LBN 224 | ||||
#define ESF_DZ_TD2CP_PCIE_ERR_WIDTH 1 | #define ESF_DZ_TD2CP_SOFT_WIDTH 14 | ||||
#define ESF_DZ_TD2CP_DESC_IDX_LBN 208 | #define ESF_DZ_TD2CP_DESC_IDX_LBN 208 | ||||
#define ESF_DZ_TD2CP_DESC_IDX_WIDTH 16 | #define ESF_DZ_TD2CP_DESC_IDX_WIDTH 16 | ||||
#define ESF_DZ_TD2CP_PKT_LEN_LBN 192 | #define ESF_DZ_TD2CP_PKT_LEN_LBN 192 | ||||
#define ESF_DZ_TD2CP_PKT_LEN_WIDTH 16 | #define ESF_DZ_TD2CP_PKT_LEN_WIDTH 16 | ||||
#define ESF_DZ_TD2CP_PKT_OFFST_OR_FIRST_DESC_IDX_LBN 176 | #define ESF_DZ_TD2CP_PKT_OFFST_OR_FIRST_DESC_IDX_LBN 176 | ||||
#define ESF_DZ_TD2CP_PKT_OFFST_OR_FIRST_DESC_IDX_WIDTH 7 | #define ESF_DZ_TD2CP_PKT_OFFST_OR_FIRST_DESC_IDX_WIDTH 7 | ||||
#define ESF_DZ_TD2CP_PEDIT_DELTA_LBN 168 | #define ESF_DZ_TD2CP_PEDIT_DELTA_LBN 168 | ||||
#define ESF_DZ_TD2CP_PEDIT_DELTA_WIDTH 8 | #define ESF_DZ_TD2CP_PEDIT_DELTA_WIDTH 8 | ||||
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines | |||||
#define ESF_DZ_V2C_NEW_DSCR_WPTR_LBN 32 | #define ESF_DZ_V2C_NEW_DSCR_WPTR_LBN 32 | ||||
#define ESF_DZ_V2C_NEW_DSCR_WPTR_WIDTH 12 | #define ESF_DZ_V2C_NEW_DSCR_WPTR_WIDTH 12 | ||||
#define ESF_DZ_V2C_DESC_PUSH_LBN 16 | #define ESF_DZ_V2C_DESC_PUSH_LBN 16 | ||||
#define ESF_DZ_V2C_DESC_PUSH_WIDTH 1 | #define ESF_DZ_V2C_DESC_PUSH_WIDTH 1 | ||||
/* ES_LUE_DB_MATCH_ENTRY */ | /* ES_LUE_DB_MATCH_ENTRY */ | ||||
#define ESF_DZ_LUE_DSCRMNTR_LBN 140 | #define ESF_DZ_LUE_DSCRMNTR_LBN 140 | ||||
#define ESF_DZ_LUE_DSCRMNTR_WIDTH 4 | #define ESF_DZ_LUE_DSCRMNTR_WIDTH 6 | ||||
#define ESF_DZ_LUE_MATCH_VAL_DW0_LBN 44 | #define ESF_DZ_LUE_MATCH_VAL_DW0_LBN 44 | ||||
#define ESF_DZ_LUE_MATCH_VAL_DW0_WIDTH 32 | #define ESF_DZ_LUE_MATCH_VAL_DW0_WIDTH 32 | ||||
#define ESF_DZ_LUE_MATCH_VAL_DW1_LBN 76 | #define ESF_DZ_LUE_MATCH_VAL_DW1_LBN 76 | ||||
#define ESF_DZ_LUE_MATCH_VAL_DW1_WIDTH 32 | #define ESF_DZ_LUE_MATCH_VAL_DW1_WIDTH 32 | ||||
#define ESF_DZ_LUE_MATCH_VAL_DW2_LBN 108 | #define ESF_DZ_LUE_MATCH_VAL_DW2_LBN 108 | ||||
#define ESF_DZ_LUE_MATCH_VAL_DW2_WIDTH 32 | #define ESF_DZ_LUE_MATCH_VAL_DW2_WIDTH 32 | ||||
#define ESF_DZ_LUE_MATCH_VAL_LBN 44 | #define ESF_DZ_LUE_MATCH_VAL_LBN 44 | ||||
#define ESF_DZ_LUE_MATCH_VAL_WIDTH 96 | #define ESF_DZ_LUE_MATCH_VAL_WIDTH 96 | ||||
#define ESF_DZ_LUE_ME_SOFT_LBN 35 | #define ESF_DZ_LUE_ME_SOFT_LBN 35 | ||||
#define ESF_DZ_LUE_ME_SOFT_WIDTH 9 | #define ESF_DZ_LUE_ME_SOFT_WIDTH 9 | ||||
#define ESF_DZ_LUE_TX_MCAST_LBN 33 | #define ESF_DZ_LUE_TX_MCAST_LBN 33 | ||||
#define ESF_DZ_LUE_TX_MCAST_WIDTH 2 | #define ESF_DZ_LUE_TX_MCAST_WIDTH 2 | ||||
#define ESF_DZ_LUE_TX_DOMAIN_LBN 25 | #define ESF_DZ_LUE_TX_DOMAIN_LBN 25 | ||||
#define ESF_DZ_LUE_TX_DOMAIN_WIDTH 8 | #define ESF_DZ_LUE_TX_DOMAIN_WIDTH 8 | ||||
#define ESF_DZ_LUE_RX_MCAST_LBN 24 | #define ESF_DZ_LUE_RX_MCAST_LBN 24 | ||||
#define ESF_DZ_LUE_RX_MCAST_WIDTH 1 | #define ESF_DZ_LUE_RX_MCAST_WIDTH 1 | ||||
#define ESE_DZ_LUE_MULTI 1 | #define ESE_DZ_LUE_MULTI 1 | ||||
#define ESE_DZ_LUE_SINGLE 0 | #define ESE_DZ_LUE_SINGLE 0 | ||||
#define ESF_DZ_LUE_RCPNTR_LBN 0 | #define ESF_DZ_LUE_RCPNTR_LBN 0 | ||||
#define ESF_DZ_LUE_RCPNTR_WIDTH 24 | #define ESF_DZ_LUE_RCPNTR_WIDTH 24 | ||||
#define ESF_DZ_LUE_RCPNTR_ME_PTR_LBN 0 | |||||
#define ESF_DZ_LUE_RCPNTR_ME_PTR_WIDTH 14 | |||||
/* ES_LUE_DB_NONMATCH_ENTRY */ | /* ES_LUE_DB_NONMATCH_ENTRY */ | ||||
#define ESF_DZ_LUE_DSCRMNTR_LBN 140 | #define ESF_DZ_LUE_DSCRMNTR_LBN 140 | ||||
#define ESF_DZ_LUE_DSCRMNTR_WIDTH 4 | #define ESF_DZ_LUE_DSCRMNTR_WIDTH 6 | ||||
#define ESF_DZ_LUE_TERMINAL_LBN 139 | #define ESF_DZ_LUE_TERMINAL_LBN 139 | ||||
#define ESF_DZ_LUE_TERMINAL_WIDTH 1 | #define ESF_DZ_LUE_TERMINAL_WIDTH 1 | ||||
#define ESF_DZ_LUE_LAST_LBN 138 | #define ESF_DZ_LUE_LAST_LBN 138 | ||||
#define ESF_DZ_LUE_LAST_WIDTH 1 | #define ESF_DZ_LUE_LAST_WIDTH 1 | ||||
#define ESF_DZ_LUE_NE_SOFT_LBN 137 | #define ESF_DZ_LUE_NE_SOFT_LBN 137 | ||||
#define ESF_DZ_LUE_NE_SOFT_WIDTH 1 | #define ESF_DZ_LUE_NE_SOFT_WIDTH 1 | ||||
#define ESF_DZ_LUE_RCPNTR_NUM_LBN 134 | #define ESF_DZ_LUE_RCPNTR_NUM_LBN 134 | ||||
#define ESF_DZ_LUE_RCPNTR_NUM_WIDTH 3 | #define ESF_DZ_LUE_RCPNTR_NUM_WIDTH 3 | ||||
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#define ESF_DZ_MC2L_DR_PAD_DW0_WIDTH 32 | #define ESF_DZ_MC2L_DR_PAD_DW0_WIDTH 32 | ||||
#define ESF_DZ_MC2L_DR_PAD_DW1_LBN 54 | #define ESF_DZ_MC2L_DR_PAD_DW1_LBN 54 | ||||
#define ESF_DZ_MC2L_DR_PAD_DW1_WIDTH 32 | #define ESF_DZ_MC2L_DR_PAD_DW1_WIDTH 32 | ||||
#define ESF_DZ_MC2L_DR_PAD_DW2_LBN 86 | #define ESF_DZ_MC2L_DR_PAD_DW2_LBN 86 | ||||
#define ESF_DZ_MC2L_DR_PAD_DW2_WIDTH 32 | #define ESF_DZ_MC2L_DR_PAD_DW2_WIDTH 32 | ||||
#define ESF_DZ_MC2L_DR_PAD_DW3_LBN 118 | #define ESF_DZ_MC2L_DR_PAD_DW3_LBN 118 | ||||
#define ESF_DZ_MC2L_DR_PAD_DW3_WIDTH 32 | #define ESF_DZ_MC2L_DR_PAD_DW3_WIDTH 32 | ||||
#define ESF_DZ_MC2L_DR_PAD_DW4_LBN 150 | #define ESF_DZ_MC2L_DR_PAD_DW4_LBN 150 | ||||
#define ESF_DZ_MC2L_DR_PAD_DW4_WIDTH 16 | #define ESF_DZ_MC2L_DR_PAD_DW4_WIDTH 18 | ||||
#define ESF_DZ_MC2L_DR_PAD_LBN 22 | #define ESF_DZ_MC2L_DR_PAD_LBN 22 | ||||
#define ESF_DZ_MC2L_DR_PAD_WIDTH 144 | #define ESF_DZ_MC2L_DR_PAD_WIDTH 146 | ||||
#define ESF_DZ_MC2L_DR_ADDR_LBN 8 | #define ESF_DZ_MC2L_DR_ADDR_LBN 8 | ||||
#define ESF_DZ_MC2L_DR_ADDR_WIDTH 14 | #define ESF_DZ_MC2L_DR_ADDR_WIDTH 14 | ||||
#define ESF_DZ_MC2L_DR_THREAD_ID_LBN 5 | #define ESF_DZ_MC2L_DR_THREAD_ID_LBN 5 | ||||
#define ESF_DZ_MC2L_DR_THREAD_ID_WIDTH 3 | #define ESF_DZ_MC2L_DR_THREAD_ID_WIDTH 3 | ||||
#define ESF_DZ_MC2L_DR_CLIENT_ID_LBN 2 | #define ESF_DZ_MC2L_DR_CLIENT_ID_LBN 2 | ||||
#define ESF_DZ_MC2L_DR_CLIENT_ID_WIDTH 3 | #define ESF_DZ_MC2L_DR_CLIENT_ID_WIDTH 3 | ||||
#define ESF_DZ_MC2L_DR_OP_LBN 0 | #define ESF_DZ_MC2L_DR_OP_LBN 0 | ||||
#define ESF_DZ_MC2L_DR_OP_WIDTH 2 | #define ESF_DZ_MC2L_DR_OP_WIDTH 2 | ||||
#define ESE_DZ_LUE_GP_WR 3 | #define ESE_DZ_LUE_GP_WR 3 | ||||
#define ESE_DZ_LUE_GP_RD 2 | #define ESE_DZ_LUE_GP_RD 2 | ||||
#define ESE_DZ_LUE_DIR_REQ 1 | #define ESE_DZ_LUE_DIR_REQ 1 | ||||
#define ESE_DZ_LUE_MATCH_REQ 0 | #define ESE_DZ_LUE_MATCH_REQ 0 | ||||
/* ES_LUE_MC_DIRECT_RESPONSE_MSG */ | /* ES_LUE_MC_DIRECT_RESPONSE_MSG */ | ||||
#define ESF_DZ_L2MC_DR_PAD_LBN 146 | #define ESF_DZ_L2MC_DR_PAD_LBN 146 | ||||
#define ESF_DZ_L2MC_DR_PAD_WIDTH 6 | #define ESF_DZ_L2MC_DR_PAD_WIDTH 8 | ||||
#define ESF_DZ_L2MC_DR_RCPNT_PTR_LBN 132 | #define ESF_DZ_L2MC_DR_RCPNT_PTR_LBN 132 | ||||
#define ESF_DZ_L2MC_DR_RCPNT_PTR_WIDTH 14 | #define ESF_DZ_L2MC_DR_RCPNT_PTR_WIDTH 14 | ||||
#define ESF_DZ_L2MC_DR_RCPNT4_LBN 108 | #define ESF_DZ_L2MC_DR_RCPNT4_LBN 108 | ||||
#define ESF_DZ_L2MC_DR_RCPNT4_WIDTH 24 | #define ESF_DZ_L2MC_DR_RCPNT4_WIDTH 24 | ||||
#define ESF_DZ_L2MC_DR_RCPNT3_LBN 84 | #define ESF_DZ_L2MC_DR_RCPNT3_LBN 84 | ||||
#define ESF_DZ_L2MC_DR_RCPNT3_WIDTH 24 | #define ESF_DZ_L2MC_DR_RCPNT3_WIDTH 24 | ||||
#define ESF_DZ_L2MC_DR_RCPNT2_LBN 60 | #define ESF_DZ_L2MC_DR_RCPNT2_LBN 60 | ||||
#define ESF_DZ_L2MC_DR_RCPNT2_WIDTH 24 | #define ESF_DZ_L2MC_DR_RCPNT2_WIDTH 24 | ||||
Show All 22 Lines | |||||
#define ESF_DZ_MC2L_GPR_PAD_DW0_WIDTH 32 | #define ESF_DZ_MC2L_GPR_PAD_DW0_WIDTH 32 | ||||
#define ESF_DZ_MC2L_GPR_PAD_DW1_LBN 54 | #define ESF_DZ_MC2L_GPR_PAD_DW1_LBN 54 | ||||
#define ESF_DZ_MC2L_GPR_PAD_DW1_WIDTH 32 | #define ESF_DZ_MC2L_GPR_PAD_DW1_WIDTH 32 | ||||
#define ESF_DZ_MC2L_GPR_PAD_DW2_LBN 86 | #define ESF_DZ_MC2L_GPR_PAD_DW2_LBN 86 | ||||
#define ESF_DZ_MC2L_GPR_PAD_DW2_WIDTH 32 | #define ESF_DZ_MC2L_GPR_PAD_DW2_WIDTH 32 | ||||
#define ESF_DZ_MC2L_GPR_PAD_DW3_LBN 118 | #define ESF_DZ_MC2L_GPR_PAD_DW3_LBN 118 | ||||
#define ESF_DZ_MC2L_GPR_PAD_DW3_WIDTH 32 | #define ESF_DZ_MC2L_GPR_PAD_DW3_WIDTH 32 | ||||
#define ESF_DZ_MC2L_GPR_PAD_DW4_LBN 150 | #define ESF_DZ_MC2L_GPR_PAD_DW4_LBN 150 | ||||
#define ESF_DZ_MC2L_GPR_PAD_DW4_WIDTH 16 | #define ESF_DZ_MC2L_GPR_PAD_DW4_WIDTH 18 | ||||
#define ESF_DZ_MC2L_GPR_PAD_LBN 22 | #define ESF_DZ_MC2L_GPR_PAD_LBN 22 | ||||
#define ESF_DZ_MC2L_GPR_PAD_WIDTH 144 | #define ESF_DZ_MC2L_GPR_PAD_WIDTH 146 | ||||
#define ESF_DZ_MC2L_GPR_ADDR_LBN 8 | #define ESF_DZ_MC2L_GPR_ADDR_LBN 8 | ||||
#define ESF_DZ_MC2L_GPR_ADDR_WIDTH 14 | #define ESF_DZ_MC2L_GPR_ADDR_WIDTH 14 | ||||
#define ESF_DZ_MC2L_GPR_THREAD_ID_LBN 5 | #define ESF_DZ_MC2L_GPR_THREAD_ID_LBN 5 | ||||
#define ESF_DZ_MC2L_GPR_THREAD_ID_WIDTH 3 | #define ESF_DZ_MC2L_GPR_THREAD_ID_WIDTH 3 | ||||
#define ESF_DZ_MC2L_GPR_CLIENT_ID_LBN 2 | #define ESF_DZ_MC2L_GPR_CLIENT_ID_LBN 2 | ||||
#define ESF_DZ_MC2L_GPR_CLIENT_ID_WIDTH 3 | #define ESF_DZ_MC2L_GPR_CLIENT_ID_WIDTH 3 | ||||
#define ESF_DZ_MC2L_GPR_OP_LBN 0 | #define ESF_DZ_MC2L_GPR_OP_LBN 0 | ||||
#define ESF_DZ_MC2L_GPR_OP_WIDTH 2 | #define ESF_DZ_MC2L_GPR_OP_WIDTH 2 | ||||
#define ESE_DZ_LUE_GP_WR 3 | #define ESE_DZ_LUE_GP_WR 3 | ||||
#define ESE_DZ_LUE_GP_RD 2 | #define ESE_DZ_LUE_GP_RD 2 | ||||
#define ESE_DZ_LUE_DIR_REQ 1 | #define ESE_DZ_LUE_DIR_REQ 1 | ||||
#define ESE_DZ_LUE_MATCH_REQ 0 | #define ESE_DZ_LUE_MATCH_REQ 0 | ||||
/* ES_LUE_MC_GP_RD_RESPONSE_MSG */ | /* ES_LUE_MC_GP_RD_RESPONSE_MSG */ | ||||
#define ESF_DZ_L2MC_GPR_DATA_DW0_LBN 8 | #define ESF_DZ_L2MC_GPR_DATA_DW0_LBN 8 | ||||
#define ESF_DZ_L2MC_GPR_DATA_DW0_WIDTH 32 | #define ESF_DZ_L2MC_GPR_DATA_DW0_WIDTH 32 | ||||
#define ESF_DZ_L2MC_GPR_DATA_DW1_LBN 40 | #define ESF_DZ_L2MC_GPR_DATA_DW1_LBN 40 | ||||
#define ESF_DZ_L2MC_GPR_DATA_DW1_WIDTH 32 | #define ESF_DZ_L2MC_GPR_DATA_DW1_WIDTH 32 | ||||
#define ESF_DZ_L2MC_GPR_DATA_DW2_LBN 72 | #define ESF_DZ_L2MC_GPR_DATA_DW2_LBN 72 | ||||
#define ESF_DZ_L2MC_GPR_DATA_DW2_WIDTH 32 | #define ESF_DZ_L2MC_GPR_DATA_DW2_WIDTH 32 | ||||
#define ESF_DZ_L2MC_GPR_DATA_DW3_LBN 104 | #define ESF_DZ_L2MC_GPR_DATA_DW3_LBN 104 | ||||
#define ESF_DZ_L2MC_GPR_DATA_DW3_WIDTH 32 | #define ESF_DZ_L2MC_GPR_DATA_DW3_WIDTH 32 | ||||
#define ESF_DZ_L2MC_GPR_DATA_DW4_LBN 136 | #define ESF_DZ_L2MC_GPR_DATA_DW4_LBN 136 | ||||
#define ESF_DZ_L2MC_GPR_DATA_DW4_WIDTH 16 | #define ESF_DZ_L2MC_GPR_DATA_DW4_WIDTH 18 | ||||
#define ESF_DZ_L2MC_GPR_DATA_LBN 8 | #define ESF_DZ_L2MC_GPR_DATA_LBN 8 | ||||
#define ESF_DZ_L2MC_GPR_DATA_WIDTH 144 | #define ESF_DZ_L2MC_GPR_DATA_WIDTH 146 | ||||
#define ESF_DZ_L2MC_GPR_THREAD_ID_LBN 5 | #define ESF_DZ_L2MC_GPR_THREAD_ID_LBN 5 | ||||
#define ESF_DZ_L2MC_GPR_THREAD_ID_WIDTH 3 | #define ESF_DZ_L2MC_GPR_THREAD_ID_WIDTH 3 | ||||
#define ESF_DZ_L2MC_GPR_CLIENT_ID_LBN 2 | #define ESF_DZ_L2MC_GPR_CLIENT_ID_LBN 2 | ||||
#define ESF_DZ_L2MC_GPR_CLIENT_ID_WIDTH 3 | #define ESF_DZ_L2MC_GPR_CLIENT_ID_WIDTH 3 | ||||
#define ESF_DZ_L2MC_GPR_OP_LBN 0 | #define ESF_DZ_L2MC_GPR_OP_LBN 0 | ||||
#define ESF_DZ_L2MC_GPR_OP_WIDTH 2 | #define ESF_DZ_L2MC_GPR_OP_WIDTH 2 | ||||
#define ESE_DZ_LUE_GP_WR 3 | #define ESE_DZ_LUE_GP_WR 3 | ||||
#define ESE_DZ_LUE_GP_RD 2 | #define ESE_DZ_LUE_GP_RD 2 | ||||
#define ESE_DZ_LUE_DIR_REQ 1 | #define ESE_DZ_LUE_DIR_REQ 1 | ||||
#define ESE_DZ_LUE_MATCH_REQ 0 | #define ESE_DZ_LUE_MATCH_REQ 0 | ||||
/* ES_LUE_MC_GP_WR_REQUEST_MSG */ | /* ES_LUE_MC_GP_WR_REQUEST_MSG */ | ||||
#define ESF_DZ_MC2L_GPW_DATA_DW0_LBN 22 | #define ESF_DZ_MC2L_GPW_DATA_DW0_LBN 22 | ||||
#define ESF_DZ_MC2L_GPW_DATA_DW0_WIDTH 32 | #define ESF_DZ_MC2L_GPW_DATA_DW0_WIDTH 32 | ||||
#define ESF_DZ_MC2L_GPW_DATA_DW1_LBN 54 | #define ESF_DZ_MC2L_GPW_DATA_DW1_LBN 54 | ||||
#define ESF_DZ_MC2L_GPW_DATA_DW1_WIDTH 32 | #define ESF_DZ_MC2L_GPW_DATA_DW1_WIDTH 32 | ||||
#define ESF_DZ_MC2L_GPW_DATA_DW2_LBN 86 | #define ESF_DZ_MC2L_GPW_DATA_DW2_LBN 86 | ||||
#define ESF_DZ_MC2L_GPW_DATA_DW2_WIDTH 32 | #define ESF_DZ_MC2L_GPW_DATA_DW2_WIDTH 32 | ||||
#define ESF_DZ_MC2L_GPW_DATA_DW3_LBN 118 | #define ESF_DZ_MC2L_GPW_DATA_DW3_LBN 118 | ||||
#define ESF_DZ_MC2L_GPW_DATA_DW3_WIDTH 32 | #define ESF_DZ_MC2L_GPW_DATA_DW3_WIDTH 32 | ||||
#define ESF_DZ_MC2L_GPW_DATA_DW4_LBN 150 | #define ESF_DZ_MC2L_GPW_DATA_DW4_LBN 150 | ||||
#define ESF_DZ_MC2L_GPW_DATA_DW4_WIDTH 16 | #define ESF_DZ_MC2L_GPW_DATA_DW4_WIDTH 18 | ||||
#define ESF_DZ_MC2L_GPW_DATA_LBN 22 | #define ESF_DZ_MC2L_GPW_DATA_LBN 22 | ||||
#define ESF_DZ_MC2L_GPW_DATA_WIDTH 144 | #define ESF_DZ_MC2L_GPW_DATA_WIDTH 146 | ||||
#define ESF_DZ_MC2L_GPW_ADDR_LBN 8 | #define ESF_DZ_MC2L_GPW_ADDR_LBN 8 | ||||
#define ESF_DZ_MC2L_GPW_ADDR_WIDTH 14 | #define ESF_DZ_MC2L_GPW_ADDR_WIDTH 14 | ||||
#define ESF_DZ_MC2L_GPW_THREAD_ID_LBN 5 | #define ESF_DZ_MC2L_GPW_THREAD_ID_LBN 5 | ||||
#define ESF_DZ_MC2L_GPW_THREAD_ID_WIDTH 3 | #define ESF_DZ_MC2L_GPW_THREAD_ID_WIDTH 3 | ||||
#define ESF_DZ_MC2L_GPW_CLIENT_ID_LBN 2 | #define ESF_DZ_MC2L_GPW_CLIENT_ID_LBN 2 | ||||
#define ESF_DZ_MC2L_GPW_CLIENT_ID_WIDTH 3 | #define ESF_DZ_MC2L_GPW_CLIENT_ID_WIDTH 3 | ||||
#define ESF_DZ_MC2L_GPW_OP_LBN 0 | #define ESF_DZ_MC2L_GPW_OP_LBN 0 | ||||
#define ESF_DZ_MC2L_GPW_OP_WIDTH 2 | #define ESF_DZ_MC2L_GPW_OP_WIDTH 2 | ||||
#define ESE_DZ_LUE_GP_WR 3 | #define ESE_DZ_LUE_GP_WR 3 | ||||
#define ESE_DZ_LUE_GP_RD 2 | #define ESE_DZ_LUE_GP_RD 2 | ||||
#define ESE_DZ_LUE_DIR_REQ 1 | #define ESE_DZ_LUE_DIR_REQ 1 | ||||
#define ESE_DZ_LUE_MATCH_REQ 0 | #define ESE_DZ_LUE_MATCH_REQ 0 | ||||
/* ES_LUE_MC_MATCH_REQUEST_MSG */ | /* ES_LUE_MC_MATCH_REQUEST_MSG */ | ||||
#define ESF_DZ_MC2L_MR_PAD_LBN 135 | #define ESF_DZ_MC2L_MR_PAD_LBN 137 | ||||
#define ESF_DZ_MC2L_MR_PAD_WIDTH 31 | #define ESF_DZ_MC2L_MR_PAD_WIDTH 31 | ||||
#define ESF_DZ_MC2L_MR_HASH2_LBN 122 | #define ESF_DZ_MC2L_MR_HASH2_LBN 124 | ||||
#define ESF_DZ_MC2L_MR_HASH2_WIDTH 13 | #define ESF_DZ_MC2L_MR_HASH2_WIDTH 13 | ||||
#define ESF_DZ_MC2L_MR_HASH1_LBN 108 | #define ESF_DZ_MC2L_MR_HASH1_LBN 110 | ||||
#define ESF_DZ_MC2L_MR_HASH1_WIDTH 14 | #define ESF_DZ_MC2L_MR_HASH1_WIDTH 14 | ||||
#define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_LBN 12 | #define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_LBN 14 | ||||
#define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_WIDTH 32 | #define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_WIDTH 32 | ||||
#define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_LBN 44 | #define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_LBN 46 | ||||
#define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_WIDTH 32 | #define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_WIDTH 32 | ||||
#define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_LBN 76 | #define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_LBN 78 | ||||
#define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_WIDTH 32 | #define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_WIDTH 32 | ||||
#define ESF_DZ_MC2L_MR_MATCH_BITS_LBN 12 | #define ESF_DZ_MC2L_MR_MATCH_BITS_LBN 14 | ||||
#define ESF_DZ_MC2L_MR_MATCH_BITS_WIDTH 96 | #define ESF_DZ_MC2L_MR_MATCH_BITS_WIDTH 96 | ||||
#define ESF_DZ_MC2L_MR_DSCRMNTR_LBN 8 | #define ESF_DZ_MC2L_MR_DSCRMNTR_LBN 8 | ||||
#define ESF_DZ_MC2L_MR_DSCRMNTR_WIDTH 4 | #define ESF_DZ_MC2L_MR_DSCRMNTR_WIDTH 6 | ||||
#define ESF_DZ_MC2L_MR_THREAD_ID_LBN 5 | #define ESF_DZ_MC2L_MR_THREAD_ID_LBN 5 | ||||
#define ESF_DZ_MC2L_MR_THREAD_ID_WIDTH 3 | #define ESF_DZ_MC2L_MR_THREAD_ID_WIDTH 3 | ||||
#define ESF_DZ_MC2L_MR_CLIENT_ID_LBN 2 | #define ESF_DZ_MC2L_MR_CLIENT_ID_LBN 2 | ||||
#define ESF_DZ_MC2L_MR_CLIENT_ID_WIDTH 3 | #define ESF_DZ_MC2L_MR_CLIENT_ID_WIDTH 3 | ||||
#define ESF_DZ_MC2L_MR_OP_LBN 0 | #define ESF_DZ_MC2L_MR_OP_LBN 0 | ||||
#define ESF_DZ_MC2L_MR_OP_WIDTH 2 | #define ESF_DZ_MC2L_MR_OP_WIDTH 2 | ||||
#define ESE_DZ_LUE_GP_WR 3 | #define ESE_DZ_LUE_GP_WR 3 | ||||
#define ESE_DZ_LUE_GP_RD 2 | #define ESE_DZ_LUE_GP_RD 2 | ||||
#define ESE_DZ_LUE_DIR_REQ 1 | #define ESE_DZ_LUE_DIR_REQ 1 | ||||
#define ESE_DZ_LUE_MATCH_REQ 0 | #define ESE_DZ_LUE_MATCH_REQ 0 | ||||
/* ES_LUE_MC_MATCH_RESPONSE_MSG */ | /* ES_LUE_MC_MATCH_RESPONSE_MSG */ | ||||
#define ESF_DZ_L2MC_MR_PAD_DW0_LBN 53 | #define ESF_DZ_L2MC_MR_PAD_DW0_LBN 53 | ||||
#define ESF_DZ_L2MC_MR_PAD_DW0_WIDTH 32 | #define ESF_DZ_L2MC_MR_PAD_DW0_WIDTH 32 | ||||
#define ESF_DZ_L2MC_MR_PAD_DW1_LBN 85 | #define ESF_DZ_L2MC_MR_PAD_DW1_LBN 85 | ||||
#define ESF_DZ_L2MC_MR_PAD_DW1_WIDTH 32 | #define ESF_DZ_L2MC_MR_PAD_DW1_WIDTH 32 | ||||
#define ESF_DZ_L2MC_MR_PAD_DW2_LBN 117 | #define ESF_DZ_L2MC_MR_PAD_DW2_LBN 117 | ||||
#define ESF_DZ_L2MC_MR_PAD_DW2_WIDTH 32 | #define ESF_DZ_L2MC_MR_PAD_DW2_WIDTH 32 | ||||
#define ESF_DZ_L2MC_MR_PAD_DW3_LBN 149 | #define ESF_DZ_L2MC_MR_PAD_DW3_LBN 149 | ||||
#define ESF_DZ_L2MC_MR_PAD_DW3_WIDTH 3 | #define ESF_DZ_L2MC_MR_PAD_DW3_WIDTH 5 | ||||
#define ESF_DZ_L2MC_MR_PAD_LBN 53 | #define ESF_DZ_L2MC_MR_PAD_LBN 53 | ||||
#define ESF_DZ_L2MC_MR_PAD_WIDTH 99 | #define ESF_DZ_L2MC_MR_PAD_WIDTH 101 | ||||
#define ESF_DZ_L2MC_MR_LUE_RCPNT_LBN 29 | #define ESF_DZ_L2MC_MR_LUE_RCPNT_LBN 29 | ||||
#define ESF_DZ_L2MC_MR_LUE_RCPNT_WIDTH 24 | #define ESF_DZ_L2MC_MR_LUE_RCPNT_WIDTH 24 | ||||
#define ESF_DZ_L2MC_MR_RX_MCAST_LBN 28 | #define ESF_DZ_L2MC_MR_RX_MCAST_LBN 28 | ||||
#define ESF_DZ_L2MC_MR_RX_MCAST_WIDTH 1 | #define ESF_DZ_L2MC_MR_RX_MCAST_WIDTH 1 | ||||
#define ESF_DZ_L2MC_MR_TX_DOMAIN_LBN 20 | #define ESF_DZ_L2MC_MR_TX_DOMAIN_LBN 20 | ||||
#define ESF_DZ_L2MC_MR_TX_DOMAIN_WIDTH 8 | #define ESF_DZ_L2MC_MR_TX_DOMAIN_WIDTH 8 | ||||
#define ESF_DZ_L2MC_MR_TX_MCAST_LBN 18 | #define ESF_DZ_L2MC_MR_TX_MCAST_LBN 18 | ||||
#define ESF_DZ_L2MC_MR_TX_MCAST_WIDTH 2 | #define ESF_DZ_L2MC_MR_TX_MCAST_WIDTH 2 | ||||
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#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW0_WIDTH 32 | #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW0_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW1_LBN 40 | #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW1_LBN 40 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW1_WIDTH 32 | #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW1_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW2_LBN 72 | #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW2_LBN 72 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW2_WIDTH 32 | #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW2_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_LBN 104 | #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_LBN 104 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_WIDTH 32 | #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_LBN 136 | #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_LBN 136 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_WIDTH 30 | #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_LBN 8 | #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_LBN 8 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_WIDTH 158 | #define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_WIDTH 160 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_LBN 5 | #define ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_LBN 5 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_WIDTH 3 | #define ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_WIDTH 3 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_LBN 2 | #define ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_LBN 2 | ||||
#define ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_WIDTH 3 | #define ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_WIDTH 3 | ||||
#define ESE_DZ_LUE_MC_ID 7 | #define ESE_DZ_LUE_MC_ID 7 | ||||
#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 | #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 | ||||
#define ESE_DZ_LUE_TX_DICPU_ID 1 | #define ESE_DZ_LUE_TX_DICPU_ID 1 | ||||
#define ESE_DZ_LUE_RX_DICPU_ID 0 | #define ESE_DZ_LUE_RX_DICPU_ID 0 | ||||
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#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW0_WIDTH 32 | #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW0_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW1_LBN 40 | #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW1_LBN 40 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW1_WIDTH 32 | #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW1_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW2_LBN 72 | #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW2_LBN 72 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW2_WIDTH 32 | #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW2_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_LBN 104 | #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_LBN 104 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_WIDTH 32 | #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_LBN 136 | #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_LBN 136 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_WIDTH 16 | #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_WIDTH 18 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_LBN 8 | #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_LBN 8 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_WIDTH 144 | #define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_WIDTH 146 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_LBN 5 | #define ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_LBN 5 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_WIDTH 3 | #define ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_WIDTH 3 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_LBN 2 | #define ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_LBN 2 | ||||
#define ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_WIDTH 3 | #define ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_WIDTH 3 | ||||
#define ESE_DZ_LUE_MC_ID 7 | #define ESE_DZ_LUE_MC_ID 7 | ||||
#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 | #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 | ||||
#define ESE_DZ_LUE_TX_DICPU_ID 1 | #define ESE_DZ_LUE_TX_DICPU_ID 1 | ||||
#define ESE_DZ_LUE_RX_DICPU_ID 0 | #define ESE_DZ_LUE_RX_DICPU_ID 0 | ||||
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#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW0_WIDTH 32 | #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW0_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW1_LBN 40 | #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW1_LBN 40 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW1_WIDTH 32 | #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW1_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW2_LBN 72 | #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW2_LBN 72 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW2_WIDTH 32 | #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW2_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW3_LBN 104 | #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW3_LBN 104 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW3_WIDTH 32 | #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW3_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_LBN 136 | #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_LBN 136 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_WIDTH 16 | #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_WIDTH 18 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_LBN 8 | #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_LBN 8 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_WIDTH 144 | #define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_WIDTH 146 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_THREAD_ID_LBN 5 | #define ESF_DZ_LUE_HW_RSP_GPRD_THREAD_ID_LBN 5 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_THREAD_ID_WIDTH 3 | #define ESF_DZ_LUE_HW_RSP_GPRD_THREAD_ID_WIDTH 3 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_CLIENT_ID_LBN 2 | #define ESF_DZ_LUE_HW_RSP_GPRD_CLIENT_ID_LBN 2 | ||||
#define ESF_DZ_LUE_HW_RSP_GPRD_CLIENT_ID_WIDTH 3 | #define ESF_DZ_LUE_HW_RSP_GPRD_CLIENT_ID_WIDTH 3 | ||||
#define ESE_DZ_LUE_MC_ID 7 | #define ESE_DZ_LUE_MC_ID 7 | ||||
#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 | #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 | ||||
#define ESE_DZ_LUE_TX_DICPU_ID 1 | #define ESE_DZ_LUE_TX_DICPU_ID 1 | ||||
#define ESE_DZ_LUE_RX_DICPU_ID 0 | #define ESE_DZ_LUE_RX_DICPU_ID 0 | ||||
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#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW0_WIDTH 32 | #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW0_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW1_LBN 54 | #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW1_LBN 54 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW1_WIDTH 32 | #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW1_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW2_LBN 86 | #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW2_LBN 86 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW2_WIDTH 32 | #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW2_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW3_LBN 118 | #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW3_LBN 118 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW3_WIDTH 32 | #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW3_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_LBN 150 | #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_LBN 150 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_WIDTH 16 | #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_WIDTH 18 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_LBN 22 | #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_LBN 22 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_WIDTH 144 | #define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_WIDTH 146 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_ADDR_LBN 8 | #define ESF_DZ_LUE_HW_REQ_GPWR_ADDR_LBN 8 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_ADDR_WIDTH 14 | #define ESF_DZ_LUE_HW_REQ_GPWR_ADDR_WIDTH 14 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_THREAD_ID_LBN 5 | #define ESF_DZ_LUE_HW_REQ_GPWR_THREAD_ID_LBN 5 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_THREAD_ID_WIDTH 3 | #define ESF_DZ_LUE_HW_REQ_GPWR_THREAD_ID_WIDTH 3 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_CLIENT_ID_LBN 2 | #define ESF_DZ_LUE_HW_REQ_GPWR_CLIENT_ID_LBN 2 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_CLIENT_ID_WIDTH 3 | #define ESF_DZ_LUE_HW_REQ_GPWR_CLIENT_ID_WIDTH 3 | ||||
#define ESE_DZ_LUE_MC_ID 7 | #define ESE_DZ_LUE_MC_ID 7 | ||||
#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 | #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 | ||||
#define ESE_DZ_LUE_TX_DICPU_ID 1 | #define ESE_DZ_LUE_TX_DICPU_ID 1 | ||||
#define ESE_DZ_LUE_RX_DICPU_ID 0 | #define ESE_DZ_LUE_RX_DICPU_ID 0 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_OP_LBN 0 | #define ESF_DZ_LUE_HW_REQ_GPWR_OP_LBN 0 | ||||
#define ESF_DZ_LUE_HW_REQ_GPWR_OP_WIDTH 2 | #define ESF_DZ_LUE_HW_REQ_GPWR_OP_WIDTH 2 | ||||
#define ESE_DZ_LUE_GP_WR 3 | #define ESE_DZ_LUE_GP_WR 3 | ||||
#define ESE_DZ_LUE_GP_RD 2 | #define ESE_DZ_LUE_GP_RD 2 | ||||
#define ESE_DZ_LUE_DIR_REQ 1 | #define ESE_DZ_LUE_DIR_REQ 1 | ||||
#define ESE_DZ_LUE_MATCH_REQ 0 | #define ESE_DZ_LUE_MATCH_REQ 0 | ||||
/* ES_LUE_MSG_MATCH_REQ */ | /* ES_LUE_MSG_MATCH_REQ */ | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_LBN 135 | #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_LBN 137 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_WIDTH 6 | #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_WIDTH 8 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_HASH2_LBN 122 | #define ESF_DZ_LUE_HW_REQ_MATCH_HASH2_LBN 124 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_HASH2_WIDTH 13 | #define ESF_DZ_LUE_HW_REQ_MATCH_HASH2_WIDTH 13 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_HASH1_LBN 108 | #define ESF_DZ_LUE_HW_REQ_MATCH_HASH1_LBN 110 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_HASH1_WIDTH 14 | #define ESF_DZ_LUE_HW_REQ_MATCH_HASH1_WIDTH 14 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_LBN 12 | #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_LBN 14 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_WIDTH 32 | #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_LBN 44 | #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_LBN 46 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_WIDTH 32 | #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_LBN 76 | #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_LBN 78 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_WIDTH 32 | #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_WIDTH 32 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_LBN 12 | #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_LBN 14 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_WIDTH 96 | #define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_WIDTH 96 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_LBN 8 | #define ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_LBN 8 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_WIDTH 4 | #define ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_WIDTH 6 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_THREAD_ID_LBN 5 | #define ESF_DZ_LUE_HW_REQ_MATCH_THREAD_ID_LBN 5 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_THREAD_ID_WIDTH 3 | #define ESF_DZ_LUE_HW_REQ_MATCH_THREAD_ID_WIDTH 3 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_CLIENT_ID_LBN 2 | #define ESF_DZ_LUE_HW_REQ_MATCH_CLIENT_ID_LBN 2 | ||||
#define ESF_DZ_LUE_HW_REQ_MATCH_CLIENT_ID_WIDTH 3 | #define ESF_DZ_LUE_HW_REQ_MATCH_CLIENT_ID_WIDTH 3 | ||||
#define ESE_DZ_LUE_MC_ID 7 | #define ESE_DZ_LUE_MC_ID 7 | ||||
#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 | #define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 | ||||
#define ESE_DZ_LUE_TX_DICPU_ID 1 | #define ESE_DZ_LUE_TX_DICPU_ID 1 | ||||
#define ESE_DZ_LUE_RX_DICPU_ID 0 | #define ESE_DZ_LUE_RX_DICPU_ID 0 | ||||
▲ Show 20 Lines • Show All 216 Lines • ▼ Show 20 Lines | |||||
/* ES_RX_EVENT */ | /* ES_RX_EVENT */ | ||||
#define ESF_DZ_RX_CODE_LBN 60 | #define ESF_DZ_RX_CODE_LBN 60 | ||||
#define ESF_DZ_RX_CODE_WIDTH 4 | #define ESF_DZ_RX_CODE_WIDTH 4 | ||||
#define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 | #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 | ||||
#define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 | #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 | ||||
#define ESF_DZ_RX_DROP_EVENT_LBN 58 | #define ESF_DZ_RX_DROP_EVENT_LBN 58 | ||||
#define ESF_DZ_RX_DROP_EVENT_WIDTH 1 | #define ESF_DZ_RX_DROP_EVENT_WIDTH 1 | ||||
#define ESF_DZ_RX_EV_RSVD2_LBN 55 | #define ESF_DZ_RX_EV_RSVD2_LBN 54 | ||||
#define ESF_DZ_RX_EV_RSVD2_WIDTH 3 | #define ESF_DZ_RX_EV_RSVD2_WIDTH 4 | ||||
#define ESF_DZ_RX_EV_SOFT2_LBN 52 | #define ESF_DZ_RX_EV_SOFT2_LBN 52 | ||||
#define ESF_DZ_RX_EV_SOFT2_WIDTH 3 | #define ESF_DZ_RX_EV_SOFT2_WIDTH 2 | ||||
#define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 | #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 | ||||
#define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 | #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 | ||||
#define ESF_DZ_RX_L4_CLASS_LBN 45 | #define ESF_DZ_RX_L4_CLASS_LBN 45 | ||||
#define ESF_DZ_RX_L4_CLASS_WIDTH 3 | #define ESF_DZ_RX_L4_CLASS_WIDTH 3 | ||||
#define ESE_DZ_L4_CLASS_RSVD7 7 | #define ESE_DZ_L4_CLASS_RSVD7 7 | ||||
#define ESE_DZ_L4_CLASS_RSVD6 6 | #define ESE_DZ_L4_CLASS_RSVD6 6 | ||||
#define ESE_DZ_L4_CLASS_RSVD5 5 | #define ESE_DZ_L4_CLASS_RSVD5 5 | ||||
#define ESE_DZ_L4_CLASS_RSVD4 4 | #define ESE_DZ_L4_CLASS_RSVD4 4 | ||||
Show All 27 Lines | |||||
#define ESE_DZ_ETH_BASE_CLASS_LLC 1 | #define ESE_DZ_ETH_BASE_CLASS_LLC 1 | ||||
#define ESE_DZ_ETH_BASE_CLASS_ETH2 0 | #define ESE_DZ_ETH_BASE_CLASS_ETH2 0 | ||||
#define ESF_DZ_RX_MAC_CLASS_LBN 35 | #define ESF_DZ_RX_MAC_CLASS_LBN 35 | ||||
#define ESF_DZ_RX_MAC_CLASS_WIDTH 1 | #define ESF_DZ_RX_MAC_CLASS_WIDTH 1 | ||||
#define ESE_DZ_MAC_CLASS_MCAST 1 | #define ESE_DZ_MAC_CLASS_MCAST 1 | ||||
#define ESE_DZ_MAC_CLASS_UCAST 0 | #define ESE_DZ_MAC_CLASS_UCAST 0 | ||||
#define ESF_DZ_RX_EV_SOFT1_LBN 32 | #define ESF_DZ_RX_EV_SOFT1_LBN 32 | ||||
#define ESF_DZ_RX_EV_SOFT1_WIDTH 3 | #define ESF_DZ_RX_EV_SOFT1_WIDTH 3 | ||||
#define ESF_DZ_RX_EV_RSVD1_LBN 30 | #define ESF_DZ_RX_EV_RSVD1_LBN 31 | ||||
#define ESF_DZ_RX_EV_RSVD1_WIDTH 2 | #define ESF_DZ_RX_EV_RSVD1_WIDTH 1 | ||||
#define ESF_DZ_RX_ABORT_LBN 30 | |||||
#define ESF_DZ_RX_ABORT_WIDTH 1 | |||||
#define ESF_DZ_RX_ECC_ERR_LBN 29 | #define ESF_DZ_RX_ECC_ERR_LBN 29 | ||||
#define ESF_DZ_RX_ECC_ERR_WIDTH 1 | #define ESF_DZ_RX_ECC_ERR_WIDTH 1 | ||||
#define ESF_DZ_RX_CRC1_ERR_LBN 28 | #define ESF_DZ_RX_CRC1_ERR_LBN 28 | ||||
#define ESF_DZ_RX_CRC1_ERR_WIDTH 1 | #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 | ||||
#define ESF_DZ_RX_CRC0_ERR_LBN 27 | #define ESF_DZ_RX_CRC0_ERR_LBN 27 | ||||
#define ESF_DZ_RX_CRC0_ERR_WIDTH 1 | #define ESF_DZ_RX_CRC0_ERR_WIDTH 1 | ||||
#define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 | #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 | ||||
#define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 | #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 | ||||
#define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 | #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 | ||||
#define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 | #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 | ||||
#define ESF_DZ_RX_ECRC_ERR_LBN 24 | #define ESF_DZ_RX_ECRC_ERR_LBN 24 | ||||
#define ESF_DZ_RX_ECRC_ERR_WIDTH 1 | #define ESF_DZ_RX_ECRC_ERR_WIDTH 1 | ||||
#define ESF_DZ_RX_QLABEL_LBN 16 | #define ESF_DZ_RX_QLABEL_LBN 16 | ||||
#define ESF_DZ_RX_QLABEL_WIDTH 8 | #define ESF_DZ_RX_QLABEL_WIDTH 5 | ||||
#define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 | #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 | ||||
#define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 | #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 | ||||
#define ESF_DZ_RX_CONT_LBN 14 | #define ESF_DZ_RX_CONT_LBN 14 | ||||
#define ESF_DZ_RX_CONT_WIDTH 1 | #define ESF_DZ_RX_CONT_WIDTH 1 | ||||
#define ESF_DZ_RX_BYTES_LBN 0 | #define ESF_DZ_RX_BYTES_LBN 0 | ||||
#define ESF_DZ_RX_BYTES_WIDTH 14 | #define ESF_DZ_RX_BYTES_WIDTH 14 | ||||
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines | |||||
#define ESF_DZ_RX_U_DATA_ACTIVE_LBN 69 | #define ESF_DZ_RX_U_DATA_ACTIVE_LBN 69 | ||||
#define ESF_DZ_RX_U_DATA_ACTIVE_WIDTH 1 | #define ESF_DZ_RX_U_DATA_ACTIVE_WIDTH 1 | ||||
#define ESF_DZ_RX_U_SOFT1_B1R0_5_LBN 69 | #define ESF_DZ_RX_U_SOFT1_B1R0_5_LBN 69 | ||||
#define ESF_DZ_RX_U_SOFT1_B1R0_5_WIDTH 1 | #define ESF_DZ_RX_U_SOFT1_B1R0_5_WIDTH 1 | ||||
#define ESF_DZ_RX_U_FAST_PATH_LBN 68 | #define ESF_DZ_RX_U_FAST_PATH_LBN 68 | ||||
#define ESF_DZ_RX_U_FAST_PATH_WIDTH 1 | #define ESF_DZ_RX_U_FAST_PATH_WIDTH 1 | ||||
#define ESF_DZ_RX_U_SOFT1_B1R0_4_LBN 68 | #define ESF_DZ_RX_U_SOFT1_B1R0_4_LBN 68 | ||||
#define ESF_DZ_RX_U_SOFT1_B1R0_4_WIDTH 1 | #define ESF_DZ_RX_U_SOFT1_B1R0_4_WIDTH 1 | ||||
#define ESF_DZ_RX_U_NO_FLUSH_LBN 67 | #define ESF_DZ_RX_U_CHAIN_LBN 67 | ||||
#define ESF_DZ_RX_U_NO_FLUSH_WIDTH 1 | #define ESF_DZ_RX_U_CHAIN_WIDTH 1 | ||||
#define ESF_DZ_RX_U_SOFT1_B1R0_3_LBN 67 | #define ESF_DZ_RX_U_SOFT1_B1R0_3_LBN 67 | ||||
#define ESF_DZ_RX_U_SOFT1_B1R0_3_WIDTH 1 | #define ESF_DZ_RX_U_SOFT1_B1R0_3_WIDTH 1 | ||||
#define ESF_DZ_RX_U_DESC_ACTIVE_LBN 66 | #define ESF_DZ_RX_U_DESC_ACTIVE_LBN 66 | ||||
#define ESF_DZ_RX_U_DESC_ACTIVE_WIDTH 1 | #define ESF_DZ_RX_U_DESC_ACTIVE_WIDTH 1 | ||||
#define ESF_DZ_RX_U_SOFT1_B1R0_2_LBN 66 | #define ESF_DZ_RX_U_SOFT1_B1R0_2_LBN 66 | ||||
#define ESF_DZ_RX_U_SOFT1_B1R0_2_WIDTH 1 | #define ESF_DZ_RX_U_SOFT1_B1R0_2_WIDTH 1 | ||||
#define ESF_DZ_RX_U_HDR_SPLIT_LBN 65 | #define ESF_DZ_RX_U_TIMESTAMP_LBN 65 | ||||
#define ESF_DZ_RX_U_HDR_SPLIT_WIDTH 1 | #define ESF_DZ_RX_U_TIMESTAMP_WIDTH 1 | ||||
#define ESF_DZ_RX_U_SOFT1_B1R0_1_LBN 65 | #define ESF_DZ_RX_U_SOFT1_B1R0_1_LBN 65 | ||||
#define ESF_DZ_RX_U_SOFT1_B1R0_1_WIDTH 1 | #define ESF_DZ_RX_U_SOFT1_B1R0_1_WIDTH 1 | ||||
#define ESF_DZ_RX_U_Q_ENABLE_LBN 64 | #define ESF_DZ_RX_U_Q_ENABLE_LBN 64 | ||||
#define ESF_DZ_RX_U_Q_ENABLE_WIDTH 1 | #define ESF_DZ_RX_U_Q_ENABLE_WIDTH 1 | ||||
#define ESF_DZ_RX_U_SOFT1_B1R0_0_LBN 64 | #define ESF_DZ_RX_U_SOFT1_B1R0_0_LBN 64 | ||||
#define ESF_DZ_RX_U_SOFT1_B1R0_0_WIDTH 1 | #define ESF_DZ_RX_U_SOFT1_B1R0_0_WIDTH 1 | ||||
#define ESF_DZ_RX_U_UPD_CRC_MODE_LBN 29 | #define ESF_DZ_RX_U_UPD_CRC_MODE_LBN 29 | ||||
#define ESF_DZ_RX_U_UPD_CRC_MODE_WIDTH 3 | #define ESF_DZ_RX_U_UPD_CRC_MODE_WIDTH 3 | ||||
Show All 15 Lines | |||||
#define ESF_DZ_RX_U_EV_QLABEL_WIDTH 5 | #define ESF_DZ_RX_U_EV_QLABEL_WIDTH 5 | ||||
/* ES_RX_U_QSTATE_TBL1_ENTRY */ | /* ES_RX_U_QSTATE_TBL1_ENTRY */ | ||||
#define ESF_DZ_RX_U_DSCR_BASE_PAGE_ID_LBN 64 | #define ESF_DZ_RX_U_DSCR_BASE_PAGE_ID_LBN 64 | ||||
#define ESF_DZ_RX_U_DSCR_BASE_PAGE_ID_WIDTH 18 | #define ESF_DZ_RX_U_DSCR_BASE_PAGE_ID_WIDTH 18 | ||||
#define ESF_DZ_RX_U_SOFT18_B1R0_0_LBN 64 | #define ESF_DZ_RX_U_SOFT18_B1R0_0_LBN 64 | ||||
#define ESF_DZ_RX_U_SOFT18_B1R0_0_WIDTH 18 | #define ESF_DZ_RX_U_SOFT18_B1R0_0_WIDTH 18 | ||||
#define ESF_DZ_RX_U_QST1_SPARE_LBN 52 | #define ESF_DZ_RX_U_QST1_SPARE_LBN 53 | ||||
#define ESF_DZ_RX_U_QST1_SPARE_WIDTH 12 | #define ESF_DZ_RX_U_QST1_SPARE_WIDTH 11 | ||||
#define ESF_DZ_RX_U_SOFT16_B0R3_0_LBN 48 | #define ESF_DZ_RX_U_SOFT16_B0R3_0_LBN 48 | ||||
#define ESF_DZ_RX_U_SOFT16_B0R3_0_WIDTH 16 | #define ESF_DZ_RX_U_SOFT16_B0R3_0_WIDTH 16 | ||||
#define ESF_DZ_RX_U_TIMESTAMP_LBN 51 | #define ESF_DZ_RX_U_NO_FLUSH_LBN 52 | ||||
#define ESF_DZ_RX_U_TIMESTAMP_WIDTH 1 | #define ESF_DZ_RX_U_NO_FLUSH_WIDTH 1 | ||||
#define ESF_DZ_RX_U_HDR_SPLIT_LBN 51 | |||||
#define ESF_DZ_RX_U_HDR_SPLIT_WIDTH 1 | |||||
#define ESF_DZ_RX_U_DOORBELL_ENABLED_LBN 50 | #define ESF_DZ_RX_U_DOORBELL_ENABLED_LBN 50 | ||||
#define ESF_DZ_RX_U_DOORBELL_ENABLED_WIDTH 1 | #define ESF_DZ_RX_U_DOORBELL_ENABLED_WIDTH 1 | ||||
#define ESF_DZ_RX_U_WORK_PENDING_LBN 49 | #define ESF_DZ_RX_U_WORK_PENDING_LBN 49 | ||||
#define ESF_DZ_RX_U_WORK_PENDING_WIDTH 1 | #define ESF_DZ_RX_U_WORK_PENDING_WIDTH 1 | ||||
#define ESF_DZ_RX_U_ERROR_LBN 48 | #define ESF_DZ_RX_U_ERROR_LBN 48 | ||||
#define ESF_DZ_RX_U_ERROR_WIDTH 1 | #define ESF_DZ_RX_U_ERROR_WIDTH 1 | ||||
#define ESF_DZ_RX_U_DSCR_SW_WPTR_LBN 32 | #define ESF_DZ_RX_U_DSCR_SW_WPTR_LBN 32 | ||||
#define ESF_DZ_RX_U_DSCR_SW_WPTR_WIDTH 12 | #define ESF_DZ_RX_U_DSCR_SW_WPTR_WIDTH 12 | ||||
#define ESF_DZ_RX_U_SOFT12_B0R2_0_LBN 32 | #define ESF_DZ_RX_U_SOFT12_B0R2_0_LBN 32 | ||||
#define ESF_DZ_RX_U_SOFT12_B0R2_0_WIDTH 12 | #define ESF_DZ_RX_U_SOFT12_B0R2_0_WIDTH 12 | ||||
#define ESF_DZ_RX_U_OWNER_ID_LBN 16 | #define ESF_DZ_RX_U_OWNER_ID_LBN 16 | ||||
#define ESF_DZ_RX_U_OWNER_ID_WIDTH 12 | #define ESF_DZ_RX_U_OWNER_ID_WIDTH 12 | ||||
#define ESF_DZ_RX_U_SOFT12_B0R1_0_LBN 16 | #define ESF_DZ_RX_U_SOFT12_B0R1_0_LBN 16 | ||||
#define ESF_DZ_RX_U_SOFT12_B0R1_0_WIDTH 12 | #define ESF_DZ_RX_U_SOFT12_B0R1_0_WIDTH 12 | ||||
#define ESF_DZ_RX_U_DSCR_SIZE_LBN 0 | #define ESF_DZ_RX_U_DSCR_SIZE_LBN 0 | ||||
#define ESF_DZ_RX_U_DSCR_SIZE_WIDTH 3 | #define ESF_DZ_RX_U_DSCR_SIZE_WIDTH 3 | ||||
#define ESE_DZ_RX_DSCR_SIZE_512 7 | #define ESE_DZ_RX_DSCR_SIZE_512 7 | ||||
#define ESE_DZ_RX_DSCR_SIZE_1K 6 | #define ESE_DZ_RX_DSCR_SIZE_1K 6 | ||||
#define ESE_DZ_RX_DSCR_SIZE_2K 5 | #define ESE_DZ_RX_DSCR_SIZE_2K 5 | ||||
#define ESE_DZ_RX_DSCR_SIZE_4K 4 | #define ESE_DZ_RX_DSCR_SIZE_4K 4 | ||||
#define ESF_DZ_RX_U_SOFT3_B0R0_0_LBN 0 | #define ESF_DZ_RX_U_SOFT3_B0R0_0_LBN 0 | ||||
#define ESF_DZ_RX_U_SOFT3_B0R0_0_WIDTH 3 | #define ESF_DZ_RX_U_SOFT3_B0R0_0_WIDTH 3 | ||||
/* ES_SGMII_DEV_PTNR_ABILITY_1000BX_MD */ | |||||
#define ESF_DZ_SGMII_DPA_NXT_PG_LBN 15 | |||||
#define ESF_DZ_SGMII_DPA_NXT_PG_WIDTH 1 | |||||
#define ESF_DZ_SGMII_DPA_ACK_LBN 14 | |||||
#define ESF_DZ_SGMII_DPA_ACK_WIDTH 1 | |||||
#define ESF_DZ_SGMII_DPA_REMOTE_FLT_LBN 12 | |||||
#define ESF_DZ_SGMII_DPA_REMOTE_FLT_WIDTH 2 | |||||
#define ESE_DZ_SGMII_DPA_RF_AN_ERR 3 | |||||
#define ESE_DZ_SGMII_DPA_RF_OFFLINE 2 | |||||
#define ESE_DZ_SGMII_DPA_RF_LINK_FAIL 1 | |||||
#define ESE_DZ_SGMII_DPA_RF_NONE 0 | |||||
#define ESF_DZ_SGMII_DPA_PS_LBN 7 | |||||
#define ESF_DZ_SGMII_DPA_PS_WIDTH 2 | |||||
#define ESF_DZ_SGMII_DPA_HD_LBN 6 | |||||
#define ESF_DZ_SGMII_DPA_HD_WIDTH 1 | |||||
#define ESF_DZ_SGMII_DPA_FD_LBN 5 | |||||
#define ESF_DZ_SGMII_DPA_FD_WIDTH 1 | |||||
/* ES_SGMII_DEV_PTNR_ABILITY_SGMII_MD */ | |||||
#define ESF_DZ_SGMII_DPA_CPR_LINK_STATE_LBN 15 | |||||
#define ESF_DZ_SGMII_DPA_CPR_LINK_STATE_WIDTH 1 | |||||
#define ESF_DZ_SGMII_DPA_ACK_LBN 14 | |||||
#define ESF_DZ_SGMII_DPA_ACK_WIDTH 1 | |||||
#define ESF_DZ_SGMII_CPR_BPLX_STS_LBN 12 | |||||
#define ESF_DZ_SGMII_CPR_BPLX_STS_WIDTH 1 | |||||
#define ESF_DZ_SGMII_DPA_COPPER_SPEED_LBN 10 | |||||
#define ESF_DZ_SGMII_DPA_COPPER_SPEED_WIDTH 2 | |||||
#define ESE_DZ_SGMII_DPA_CPR_1GBS 2 | |||||
#define ESE_DZ_SGMII_DPA_CPR_100MBS 1 | |||||
#define ESE_DZ_SGMII_DPA_CPR_10MBS 0 | |||||
/* ES_SMC_BUFTBL_CNTRL_ENTRY */ | /* ES_SMC_BUFTBL_CNTRL_ENTRY */ | ||||
#define ESF_DZ_SMC_SW_CNTXT_DW0_LBN 16 | #define ESF_DZ_SMC_SW_CNTXT_DW0_LBN 16 | ||||
#define ESF_DZ_SMC_SW_CNTXT_DW0_WIDTH 32 | #define ESF_DZ_SMC_SW_CNTXT_DW0_WIDTH 32 | ||||
#define ESF_DZ_SMC_SW_CNTXT_DW1_LBN 48 | #define ESF_DZ_SMC_SW_CNTXT_DW1_LBN 48 | ||||
#define ESF_DZ_SMC_SW_CNTXT_DW1_WIDTH 24 | #define ESF_DZ_SMC_SW_CNTXT_DW1_WIDTH 24 | ||||
#define ESF_DZ_SMC_SW_CNTXT_LBN 16 | #define ESF_DZ_SMC_SW_CNTXT_LBN 16 | ||||
#define ESF_DZ_SMC_SW_CNTXT_WIDTH 56 | #define ESF_DZ_SMC_SW_CNTXT_WIDTH 56 | ||||
#define ESF_DZ_SMC_PAGE_SIZE_LBN 12 | #define ESF_DZ_SMC_PAGE_SIZE_LBN 12 | ||||
▲ Show 20 Lines • Show All 413 Lines • ▼ Show 20 Lines | |||||
#define ESF_DZ_S2MC_WR_OP_WIDTH 3 | #define ESF_DZ_S2MC_WR_OP_WIDTH 3 | ||||
#define ESE_DZ_SMC_REQ_WR 4 | #define ESE_DZ_SMC_REQ_WR 4 | ||||
#define ESE_DZ_SMC_REQ_RD 3 | #define ESE_DZ_SMC_REQ_RD 3 | ||||
#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 | #define ESE_DZ_SMC_REQ_DSCR_WRITE 2 | ||||
#define ESE_DZ_SMC_REQ_DSCR_READ 1 | #define ESE_DZ_SMC_REQ_DSCR_READ 1 | ||||
#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 | #define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 | ||||
/* ES_TX_CSUM_TSTAMP_DESC */ | |||||
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 | |||||
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 | |||||
#define ESF_DZ_TX_OPTION_TYPE_LBN 60 | |||||
#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 | |||||
#define ESE_DZ_TX_OPTION_DESC_TSO 7 | |||||
#define ESE_DZ_TX_OPTION_DESC_VLAN 6 | |||||
#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 | |||||
#define ESF_DZ_TX_TIMESTAMP_LBN 5 | |||||
#define ESF_DZ_TX_TIMESTAMP_WIDTH 1 | |||||
#define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 | |||||
#define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 | |||||
#define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 | |||||
#define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 | |||||
#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 | |||||
#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 | |||||
#define ESE_DZ_TX_OPTION_CRC_FCOE 1 | |||||
#define ESE_DZ_TX_OPTION_CRC_OFF 0 | |||||
#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 | |||||
#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 | |||||
#define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 | |||||
#define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 | |||||
/* ES_TX_EVENT */ | /* ES_TX_EVENT */ | ||||
#define ESF_DZ_TX_CODE_LBN 60 | #define ESF_DZ_TX_CODE_LBN 60 | ||||
#define ESF_DZ_TX_CODE_WIDTH 4 | #define ESF_DZ_TX_CODE_WIDTH 4 | ||||
#define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 | #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 | ||||
#define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 | #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 | ||||
#define ESF_DZ_TX_DROP_EVENT_LBN 58 | #define ESF_DZ_TX_DROP_EVENT_LBN 58 | ||||
#define ESF_DZ_TX_DROP_EVENT_WIDTH 1 | #define ESF_DZ_TX_DROP_EVENT_WIDTH 1 | ||||
#define ESF_DZ_TX_EV_RSVD_LBN 48 | #define ESF_DZ_TX_EV_RSVD_LBN 48 | ||||
#define ESF_DZ_TX_EV_RSVD_WIDTH 10 | #define ESF_DZ_TX_EV_RSVD_WIDTH 10 | ||||
#define ESF_DZ_TX_SOFT2_LBN 32 | #define ESF_DZ_TX_SOFT2_LBN 32 | ||||
#define ESF_DZ_TX_SOFT2_WIDTH 16 | #define ESF_DZ_TX_SOFT2_WIDTH 16 | ||||
#define ESF_DZ_TX_CAN_MERGE_LBN 31 | |||||
#define ESF_DZ_TX_CAN_MERGE_WIDTH 1 | |||||
#define ESF_DZ_TX_SOFT1_LBN 24 | #define ESF_DZ_TX_SOFT1_LBN 24 | ||||
#define ESF_DZ_TX_SOFT1_WIDTH 8 | #define ESF_DZ_TX_SOFT1_WIDTH 7 | ||||
#define ESF_DZ_TX_QLABEL_LBN 16 | #define ESF_DZ_TX_QLABEL_LBN 16 | ||||
#define ESF_DZ_TX_QLABEL_WIDTH 8 | #define ESF_DZ_TX_QLABEL_WIDTH 5 | ||||
#define ESF_DZ_TX_DESCR_INDX_LBN 0 | #define ESF_DZ_TX_DESCR_INDX_LBN 0 | ||||
#define ESF_DZ_TX_DESCR_INDX_WIDTH 16 | #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 | ||||
/* ES_TX_KER_DESC */ | /* ES_TX_KER_DESC */ | ||||
#define ESF_DZ_TX_KER_TYPE_LBN 63 | #define ESF_DZ_TX_KER_TYPE_LBN 63 | ||||
#define ESF_DZ_TX_KER_TYPE_WIDTH 1 | #define ESF_DZ_TX_KER_TYPE_WIDTH 1 | ||||
#define ESF_DZ_TX_KER_CONT_LBN 62 | #define ESF_DZ_TX_KER_CONT_LBN 62 | ||||
#define ESF_DZ_TX_KER_CONT_WIDTH 1 | #define ESF_DZ_TX_KER_CONT_WIDTH 1 | ||||
#define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 | #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 | ||||
#define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 | #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 | ||||
#define ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0 | #define ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0 | ||||
#define ESF_DZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 | #define ESF_DZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 | ||||
#define ESF_DZ_TX_KER_BUF_ADDR_DW1_LBN 32 | #define ESF_DZ_TX_KER_BUF_ADDR_DW1_LBN 32 | ||||
#define ESF_DZ_TX_KER_BUF_ADDR_DW1_WIDTH 16 | #define ESF_DZ_TX_KER_BUF_ADDR_DW1_WIDTH 16 | ||||
#define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 | #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 | ||||
#define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 | #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 | ||||
/* ES_TX_OPTION_DESC */ | /* ES_TX_PIO_DESC */ | ||||
#define ESF_DZ_TX_PIO_TYPE_LBN 63 | |||||
#define ESF_DZ_TX_PIO_TYPE_WIDTH 1 | |||||
#define ESF_DZ_TX_PIO_OPT_LBN 60 | |||||
#define ESF_DZ_TX_PIO_OPT_WIDTH 3 | |||||
#define ESF_DZ_TX_PIO_CONT_LBN 59 | |||||
#define ESF_DZ_TX_PIO_CONT_WIDTH 1 | |||||
#define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 | |||||
#define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 | |||||
#define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 | |||||
#define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 | |||||
/* ES_TX_TSO_DESC */ | |||||
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 | #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 | ||||
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 | #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 | ||||
#define ESF_DZ_TX_OPTION_TYPE_LBN 60 | #define ESF_DZ_TX_OPTION_TYPE_LBN 60 | ||||
#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 | #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 | ||||
#define ESE_DZ_TX_OPTION_DESC_TSO 4 | #define ESE_DZ_TX_OPTION_DESC_TSO 7 | ||||
#define ESE_DZ_TX_OPTION_DESC_VLAN 6 | |||||
#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 | #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 | ||||
#define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 | #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 | ||||
#define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 | #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 | ||||
#define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 | #define ESF_DZ_TX_TSO_IP_ID_LBN 32 | ||||
#define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 | #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 | ||||
#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 | #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 | ||||
#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 | #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 | ||||
#define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 | |||||
#define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 | |||||
#define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 | |||||
#define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 | |||||
#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 | |||||
#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 | |||||
#define ESE_DZ_TX_OPTION_CRC_FCOE 1 | |||||
#define ESE_DZ_TX_OPTION_CRC_OFF 0 | |||||
#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 | |||||
#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 | |||||
#define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 | |||||
#define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 | |||||
/* ES_TX_PACER_BASE_MSG */ | |||||
#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW0_LBN 11 | |||||
#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW0_WIDTH 32 | |||||
#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW1_LBN 43 | |||||
#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW1_WIDTH 32 | |||||
#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW2_LBN 75 | |||||
#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW2_WIDTH 23 | |||||
#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_LBN 11 | |||||
#define ESF_DZ_TXP_BASE_REQ_MSG_DATA_WIDTH 87 | |||||
#define ESF_DZ_TXP_BASE_OP_LBN 2 | |||||
#define ESF_DZ_TXP_BASE_OP_WIDTH 3 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 | |||||
#define ESF_DZ_TXP_BASE_CLIENT_ID_LBN 0 | |||||
#define ESF_DZ_TXP_BASE_CLIENT_ID_WIDTH 2 | |||||
#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 | |||||
#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 | |||||
#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 | |||||
/* ES_TX_PACER_BKT_D_R_REQ */ | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_FRM_LEN_LBN 45 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_FRM_LEN_WIDTH 14 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT2_LBN 35 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT2_WIDTH 10 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT1_LBN 25 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT1_WIDTH 10 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT0_LBN 15 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT0_WIDTH 10 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_MIN_BKT_LBN 5 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_MIN_BKT_WIDTH 10 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_OP_LBN 2 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_OP_WIDTH 3 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_CLIENT_ID_LBN 0 | |||||
#define ESF_DZ_TXP_BKT_D_R_REQ_CLIENT_ID_WIDTH 2 | |||||
#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 | |||||
#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 | |||||
#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 | |||||
/* ES_TX_PACER_BKT_TBL_D_R_RSP */ | |||||
#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_DUE_TIME_WITH_MIN_BKT_LBN 21 | |||||
#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_DUE_TIME_WITH_MIN_BKT_WIDTH 26 | |||||
#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_DUE_TIME_LBN 5 | |||||
#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_DUE_TIME_WIDTH 16 | |||||
#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_OP_LBN 2 | |||||
#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_OP_WIDTH 3 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 | |||||
#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_CLIENT_ID_LBN 0 | |||||
#define ESF_DZ_TXP_BKT_TBL_D_R_RSP_CLIENT_ID_WIDTH 2 | |||||
#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 | |||||
#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 | |||||
#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 | |||||
/* ES_TX_PACER_BKT_TBL_RD_REQ */ | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_REQ_BKT_ID_LBN 5 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_REQ_BKT_ID_WIDTH 10 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_REQ_OP_LBN 2 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_REQ_OP_WIDTH 3 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_REQ_CLIENT_ID_LBN 0 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_REQ_CLIENT_ID_WIDTH 2 | |||||
#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 | |||||
#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 | |||||
#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 | |||||
/* ES_TX_PACER_BKT_TBL_RD_RSP */ | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_IDLE_LBN 97 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_IDLE_WIDTH 1 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_USED_LBN 96 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_USED_WIDTH 1 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_MAX_FILL_REG_LBN 94 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_MAX_FILL_REG_WIDTH 2 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_RATE_REC_LBN 78 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_RATE_REC_WIDTH 16 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_RATE_LBN 62 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_RATE_WIDTH 16 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_FILL_LEVEL_LBN 47 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_FILL_LEVEL_WIDTH 15 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_DUE_TIME_LBN 31 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_DUE_TIME_WIDTH 16 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_LAST_FILL_TIME_LBN 15 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_LAST_FILL_TIME_WIDTH 16 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_BKT_ID_LBN 5 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_BKT_ID_WIDTH 10 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_OP_LBN 2 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_OP_WIDTH 3 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_CLIENT_ID_LBN 0 | |||||
#define ESF_DZ_TXP_BKT_TBL_RD_RSP_CLIENT_ID_WIDTH 2 | |||||
#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 | |||||
#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 | |||||
#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 | |||||
/* ES_TX_PACER_BKT_TBL_WR_REQ */ | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_IDLE_LBN 65 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_IDLE_WIDTH 1 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_USED_LBN 64 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_USED_WIDTH 1 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_MAX_FILL_REG_LBN 62 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_MAX_FILL_REG_WIDTH 2 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_RATE_REC_LBN 46 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_RATE_REC_WIDTH 16 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_RATE_LBN 30 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_RATE_WIDTH 16 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_FILL_LEVEL_LBN 15 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_FILL_LEVEL_WIDTH 15 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_BKT_ID_LBN 5 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_BKT_ID_WIDTH 10 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_OP_LBN 2 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_OP_WIDTH 3 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_CLIENT_ID_LBN 0 | |||||
#define ESF_DZ_TXP_BKT_TBL_WR_REQ_CLIENT_ID_WIDTH 2 | |||||
#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 | |||||
#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 | |||||
#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 | |||||
/* ES_TX_PACER_TXQ_D_R_I_REQ */ | |||||
#define ESF_DZ_TXP_TXQ_D_R_I_REQ_FRM_LEN_LBN 15 | |||||
#define ESF_DZ_TXP_TXQ_D_R_I_REQ_FRM_LEN_WIDTH 14 | |||||
#define ESF_DZ_TXP_TXQ_D_R_I_REQ_TXQ_ID_LBN 5 | |||||
#define ESF_DZ_TXP_TXQ_D_R_I_REQ_TXQ_ID_WIDTH 10 | |||||
#define ESF_DZ_TXP_TXQ_D_R_I_REQ_OP_LBN 2 | |||||
#define ESF_DZ_TXP_TXQ_D_R_I_REQ_OP_WIDTH 3 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 | |||||
#define ESF_DZ_TXP_TXQ_D_R_I_REQ_CLIENT_ID_LBN 0 | |||||
#define ESF_DZ_TXP_TXQ_D_R_I_REQ_CLIENT_ID_WIDTH 2 | |||||
#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 | |||||
#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 | |||||
#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 | |||||
/* ES_TX_PACER_TXQ_TBL_RD_REQ */ | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_REQ_TXQ_ID_LBN 5 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_REQ_TXQ_ID_WIDTH 10 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_REQ_OP_LBN 2 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_REQ_OP_WIDTH 3 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_REQ_CLIENT_ID_LBN 0 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_REQ_CLIENT_ID_WIDTH 2 | |||||
#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 | |||||
#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 | |||||
#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 | |||||
/* ES_TX_PACER_TXQ_TBL_RD_RSP */ | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT2_LBN 53 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT2_WIDTH 10 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT1_LBN 43 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT1_WIDTH 10 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT0_LBN 33 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT0_WIDTH 10 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MIN_BKT_LBN 23 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_MIN_BKT_WIDTH 10 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_LABEL_LBN 19 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_LABEL_WIDTH 4 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_PQ_FLAGS_LBN 16 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_PQ_FLAGS_WIDTH 3 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_DSBL_LBN 15 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_DSBL_WIDTH 1 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_TXQ_ID_LBN 5 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_TXQ_ID_WIDTH 10 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_OP_LBN 2 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_OP_WIDTH 3 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_CLIENT_ID_LBN 0 | |||||
#define ESF_DZ_TXP_TXQ_TBL_RD_RSP_CLIENT_ID_WIDTH 2 | |||||
#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 | |||||
#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 | |||||
#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 | |||||
/* ES_TX_PACER_TXQ_TBL_WR_REQ */ | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT2_LBN 53 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT2_WIDTH 10 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT1_LBN 43 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT1_WIDTH 10 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT0_LBN 33 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT0_WIDTH 10 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MIN_BKT_LBN 23 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_MIN_BKT_WIDTH 10 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_LABEL_LBN 19 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_LABEL_WIDTH 4 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_PQ_FLAGS_LBN 16 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_PQ_FLAGS_WIDTH 3 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_DSBL_LBN 15 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_DSBL_WIDTH 1 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_TXQ_ID_LBN 5 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_TXQ_ID_WIDTH 10 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_OP_LBN 2 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_OP_WIDTH 3 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3 | |||||
#define ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1 | |||||
#define ESE_DZ_DPCPU_PACER_BKT_D_RD 0 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_CLIENT_ID_LBN 0 | |||||
#define ESF_DZ_TXP_TXQ_TBL_WR_REQ_CLIENT_ID_WIDTH 2 | |||||
#define ESE_DZ_DPCPU_PACER_CPU_CLIENT 2 | |||||
#define ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1 | |||||
#define ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0 | |||||
/* ES_TX_USER_DESC */ | /* ES_TX_USER_DESC */ | ||||
#define ESF_DZ_TX_USR_TYPE_LBN 63 | #define ESF_DZ_TX_USR_TYPE_LBN 63 | ||||
#define ESF_DZ_TX_USR_TYPE_WIDTH 1 | #define ESF_DZ_TX_USR_TYPE_WIDTH 1 | ||||
#define ESF_DZ_TX_USR_CONT_LBN 62 | #define ESF_DZ_TX_USR_CONT_LBN 62 | ||||
#define ESF_DZ_TX_USR_CONT_WIDTH 1 | #define ESF_DZ_TX_USR_CONT_WIDTH 1 | ||||
#define ESF_DZ_TX_USR_BYTE_CNT_LBN 48 | #define ESF_DZ_TX_USR_BYTE_CNT_LBN 48 | ||||
#define ESF_DZ_TX_USR_BYTE_CNT_WIDTH 14 | #define ESF_DZ_TX_USR_BYTE_CNT_WIDTH 14 | ||||
#define ESF_DZ_TX_USR_BUF_PAGE_SIZE_LBN 44 | #define ESF_DZ_TX_USR_BUF_PAGE_SIZE_LBN 44 | ||||
Show All 34 Lines | |||||
#define ESF_DZ_TX_U_DSCR_HW_RPTR_LBN 96 | #define ESF_DZ_TX_U_DSCR_HW_RPTR_LBN 96 | ||||
#define ESF_DZ_TX_U_DSCR_HW_RPTR_WIDTH 12 | #define ESF_DZ_TX_U_DSCR_HW_RPTR_WIDTH 12 | ||||
#define ESF_DZ_TX_U_SOFT12_B1R2_LBN 96 | #define ESF_DZ_TX_U_SOFT12_B1R2_LBN 96 | ||||
#define ESF_DZ_TX_U_SOFT12_B1R2_WIDTH 12 | #define ESF_DZ_TX_U_SOFT12_B1R2_WIDTH 12 | ||||
#define ESF_DZ_TX_U_DC_RPTR_LBN 80 | #define ESF_DZ_TX_U_DC_RPTR_LBN 80 | ||||
#define ESF_DZ_TX_U_DC_RPTR_WIDTH 6 | #define ESF_DZ_TX_U_DC_RPTR_WIDTH 6 | ||||
#define ESF_DZ_TX_U_SOFT6_B1R1_LBN 80 | #define ESF_DZ_TX_U_SOFT6_B1R1_LBN 80 | ||||
#define ESF_DZ_TX_U_SOFT6_B1R1_WIDTH 6 | #define ESF_DZ_TX_U_SOFT6_B1R1_WIDTH 6 | ||||
#define ESF_DZ_TX_U_CNTAG_LBN 68 | |||||
#define ESF_DZ_TX_U_CNTAG_WIDTH 1 | |||||
#define ESF_DZ_TX_U_SOFT5_B1R0_LBN 64 | #define ESF_DZ_TX_U_SOFT5_B1R0_LBN 64 | ||||
#define ESF_DZ_TX_U_SOFT5_B1R0_WIDTH 5 | #define ESF_DZ_TX_U_SOFT5_B1R0_WIDTH 5 | ||||
#define ESF_DZ_TX_U_TIMESTAMP_LBN 67 | |||||
#define ESF_DZ_TX_U_TIMESTAMP_WIDTH 1 | |||||
#define ESF_DZ_TX_U_PREFETCH_ACTIVE_LBN 66 | #define ESF_DZ_TX_U_PREFETCH_ACTIVE_LBN 66 | ||||
#define ESF_DZ_TX_U_PREFETCH_ACTIVE_WIDTH 1 | #define ESF_DZ_TX_U_PREFETCH_ACTIVE_WIDTH 1 | ||||
#define ESF_DZ_TX_U_PREFETCH_PENDING_LBN 65 | #define ESF_DZ_TX_U_PREFETCH_PENDING_LBN 65 | ||||
#define ESF_DZ_TX_U_PREFETCH_PENDING_WIDTH 1 | #define ESF_DZ_TX_U_PREFETCH_PENDING_WIDTH 1 | ||||
#define ESF_DZ_TX_U_DOORBELL_ENABLED_LBN 64 | #define ESF_DZ_TX_U_DOORBELL_ENABLED_LBN 64 | ||||
#define ESF_DZ_TX_U_DOORBELL_ENABLED_WIDTH 1 | #define ESF_DZ_TX_U_DOORBELL_ENABLED_WIDTH 1 | ||||
#define ESF_DZ_TX_U_UPD_UDPTCP_CSUM_MODE_LBN 33 | #define ESF_DZ_TX_U_UPD_UDPTCP_CSUM_MODE_LBN 33 | ||||
#define ESF_DZ_TX_U_UPD_UDPTCP_CSUM_MODE_WIDTH 1 | #define ESF_DZ_TX_U_UPD_UDPTCP_CSUM_MODE_WIDTH 1 | ||||
Show All 23 Lines | |||||
/* ES_TX_U_QSTATE_TBL1_ENTRY */ | /* ES_TX_U_QSTATE_TBL1_ENTRY */ | ||||
#define ESF_DZ_TX_U_DSCR_BASE_PAGE_ID_LBN 64 | #define ESF_DZ_TX_U_DSCR_BASE_PAGE_ID_LBN 64 | ||||
#define ESF_DZ_TX_U_DSCR_BASE_PAGE_ID_WIDTH 18 | #define ESF_DZ_TX_U_DSCR_BASE_PAGE_ID_WIDTH 18 | ||||
#define ESF_DZ_TX_U_SOFT18_B1R0_LBN 64 | #define ESF_DZ_TX_U_SOFT18_B1R0_LBN 64 | ||||
#define ESF_DZ_TX_U_SOFT18_B1R0_WIDTH 18 | #define ESF_DZ_TX_U_SOFT18_B1R0_WIDTH 18 | ||||
#define ESF_DZ_TX_U_SOFT16_B0R3_LBN 48 | #define ESF_DZ_TX_U_SOFT16_B0R3_LBN 48 | ||||
#define ESF_DZ_TX_U_SOFT16_B0R3_WIDTH 16 | #define ESF_DZ_TX_U_SOFT16_B0R3_WIDTH 16 | ||||
#define ESF_DZ_TX_U_EMERGENCY_FETCH_FAILED_LBN 56 | |||||
#define ESF_DZ_TX_U_EMERGENCY_FETCH_FAILED_WIDTH 1 | |||||
#define ESF_DZ_TX_U_PACER_BYPASS_OK_LBN 55 | |||||
#define ESF_DZ_TX_U_PACER_BYPASS_OK_WIDTH 1 | |||||
#define ESF_DZ_TX_U_STALE_DL_FETCH_LBN 54 | |||||
#define ESF_DZ_TX_U_STALE_DL_FETCH_WIDTH 1 | |||||
#define ESF_DZ_TX_U_ROLLBACK_IDX_REACHED_LBN 52 | |||||
#define ESF_DZ_TX_U_ROLLBACK_IDX_REACHED_WIDTH 1 | |||||
#define ESF_DZ_TX_U_ROLLBACK_ACTIVE_LBN 51 | |||||
#define ESF_DZ_TX_U_ROLLBACK_ACTIVE_WIDTH 1 | |||||
#define ESF_DZ_TX_U_QUEUE_PAUSED_LBN 50 | |||||
#define ESF_DZ_TX_U_QUEUE_PAUSED_WIDTH 1 | |||||
#define ESF_DZ_TX_U_QUEUE_ENABLED_LBN 49 | #define ESF_DZ_TX_U_QUEUE_ENABLED_LBN 49 | ||||
#define ESF_DZ_TX_U_QUEUE_ENABLED_WIDTH 1 | #define ESF_DZ_TX_U_QUEUE_ENABLED_WIDTH 1 | ||||
#define ESF_DZ_TX_U_FLUSH_PENDING_LBN 48 | #define ESF_DZ_TX_U_FLUSH_PENDING_LBN 48 | ||||
#define ESF_DZ_TX_U_FLUSH_PENDING_WIDTH 1 | #define ESF_DZ_TX_U_FLUSH_PENDING_WIDTH 1 | ||||
#define ESF_DZ_TX_U_DSCR_HW_WPTR_LBN 32 | #define ESF_DZ_TX_U_DSCR_HW_WPTR_LBN 32 | ||||
#define ESF_DZ_TX_U_DSCR_HW_WPTR_WIDTH 12 | #define ESF_DZ_TX_U_DSCR_HW_WPTR_WIDTH 12 | ||||
#define ESF_DZ_TX_U_SOFT12_B0R2_LBN 32 | #define ESF_DZ_TX_U_SOFT12_B0R2_LBN 32 | ||||
#define ESF_DZ_TX_U_SOFT12_B0R2_WIDTH 12 | #define ESF_DZ_TX_U_SOFT12_B0R2_WIDTH 12 | ||||
#define ESF_DZ_TX_U_OWNER_ID_LBN 16 | #define ESF_DZ_TX_U_OWNER_ID_LBN 16 | ||||
#define ESF_DZ_TX_U_OWNER_ID_WIDTH 12 | #define ESF_DZ_TX_U_OWNER_ID_WIDTH 12 | ||||
#define ESF_DZ_TX_U_SOFT12_B0R1_LBN 16 | #define ESF_DZ_TX_U_SOFT12_B0R1_LBN 16 | ||||
#define ESF_DZ_TX_U_SOFT12_B0R1_WIDTH 12 | #define ESF_DZ_TX_U_SOFT12_B0R1_WIDTH 12 | ||||
#define ESF_DZ_TX_U_DSCR_SIZE_LBN 0 | #define ESF_DZ_TX_U_DSCR_SIZE_LBN 13 | ||||
#define ESF_DZ_TX_U_DSCR_SIZE_WIDTH 3 | #define ESF_DZ_TX_U_DSCR_SIZE_WIDTH 3 | ||||
#define ESF_DZ_TX_U_SOFT3_B0R0_LBN 0 | #define ESF_DZ_TX_U_SOFT3_B0R0_LBN 0 | ||||
#define ESF_DZ_TX_U_SOFT3_B0R0_WIDTH 3 | #define ESF_DZ_TX_U_SOFT3_B0R0_WIDTH 3 | ||||
/* ES_TX_U_QSTATE_TBL2_ENTRY */ | /* ES_TX_U_QSTATE_TBL2_ENTRY */ | ||||
#define ESF_DZ_TX_FINFO_WRD3_LBN 48 | #define ESF_DZ_TX_FINFO_WRD3_LBN 48 | ||||
#define ESF_DZ_TX_FINFO_WRD3_WIDTH 16 | #define ESF_DZ_TX_FINFO_WRD3_WIDTH 16 | ||||
#define ESF_DZ_TX_FINFO_WRD2_LBN 32 | #define ESF_DZ_TX_FINFO_WRD2_LBN 32 | ||||
#define ESF_DZ_TX_FINFO_WRD2_WIDTH 16 | #define ESF_DZ_TX_FINFO_WRD2_WIDTH 16 | ||||
#define ESF_DZ_TX_FINFO_WRD1_LBN 16 | #define ESF_DZ_TX_FINFO_WRD1_LBN 16 | ||||
#define ESF_DZ_TX_FINFO_WRD1_WIDTH 16 | #define ESF_DZ_TX_FINFO_WRD1_WIDTH 16 | ||||
#define ESF_DZ_TX_FINFO_SRCDST_LBN 0 | #define ESF_DZ_TX_FINFO_SRCDST_LBN 0 | ||||
#define ESF_DZ_TX_FINFO_SRCDST_WIDTH 16 | #define ESF_DZ_TX_FINFO_SRCDST_WIDTH 16 | ||||
/* ES_TX_VLAN_DESC */ | |||||
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 | |||||
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 | |||||
#define ESF_DZ_TX_OPTION_TYPE_LBN 60 | |||||
#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 | |||||
#define ESE_DZ_TX_OPTION_DESC_TSO 7 | |||||
#define ESE_DZ_TX_OPTION_DESC_VLAN 6 | |||||
#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 | |||||
#define ESF_DZ_TX_VLAN_OP_LBN 32 | |||||
#define ESF_DZ_TX_VLAN_OP_WIDTH 2 | |||||
#define ESF_DZ_TX_VLAN_TAG2_LBN 16 | |||||
#define ESF_DZ_TX_VLAN_TAG2_WIDTH 16 | |||||
#define ESF_DZ_TX_VLAN_TAG1_LBN 0 | |||||
#define ESF_DZ_TX_VLAN_TAG1_WIDTH 16 | |||||
/* ES_b2t_cpl_rsp */ | /* ES_b2t_cpl_rsp */ | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_ECC_LBN 268 | #define ESF_DZ_B2T_CPL_RSP_CPL_ECC_LBN 284 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_ECC_WIDTH 32 | #define ESF_DZ_B2T_CPL_RSP_CPL_ECC_WIDTH 32 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_EOT_LBN 283 | |||||
#define ESF_DZ_B2T_CPL_RSP_CPL_EOT_WIDTH 1 | |||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW0_LBN 27 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW0_LBN 27 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW0_WIDTH 32 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW0_WIDTH 32 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW1_LBN 59 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW1_LBN 59 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW1_WIDTH 32 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW1_WIDTH 32 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW2_LBN 91 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW2_LBN 91 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW2_WIDTH 32 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW2_WIDTH 32 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW3_LBN 123 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW3_LBN 123 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW3_WIDTH 32 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW3_WIDTH 32 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW4_LBN 155 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW4_LBN 155 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW4_WIDTH 32 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW4_WIDTH 32 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW5_LBN 187 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW5_LBN 187 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW5_WIDTH 32 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW5_WIDTH 32 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW6_LBN 219 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW6_LBN 219 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW6_WIDTH 32 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW6_WIDTH 32 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW7_LBN 251 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW7_LBN 251 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW7_WIDTH 32 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW7_WIDTH 32 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_LBN 27 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_LBN 27 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_WIDTH 256 | #define ESF_DZ_B2T_CPL_RSP_CPL_DATA_WIDTH 256 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_EOT_LBN 283 | |||||
#define ESF_DZ_B2T_CPL_RSP_CPL_EOT_WIDTH -15 | |||||
#define ESF_DZ_B2T_CPL_RSP_CPL_ERROR_LBN 26 | #define ESF_DZ_B2T_CPL_RSP_CPL_ERROR_LBN 26 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_ERROR_WIDTH 1 | #define ESF_DZ_B2T_CPL_RSP_CPL_ERROR_WIDTH 1 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_LAST_LBN 25 | #define ESF_DZ_B2T_CPL_RSP_CPL_LAST_LBN 25 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_LAST_WIDTH 1 | #define ESF_DZ_B2T_CPL_RSP_CPL_LAST_WIDTH 1 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_TAG_LBN 19 | #define ESF_DZ_B2T_CPL_RSP_CPL_TAG_LBN 19 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_TAG_WIDTH 6 | #define ESF_DZ_B2T_CPL_RSP_CPL_TAG_WIDTH 6 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_LEN_LBN 7 | #define ESF_DZ_B2T_CPL_RSP_CPL_LEN_LBN 7 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_LEN_WIDTH 12 | #define ESF_DZ_B2T_CPL_RSP_CPL_LEN_WIDTH 12 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_ADRS_LBN 0 | #define ESF_DZ_B2T_CPL_RSP_CPL_ADRS_LBN 0 | ||||
#define ESF_DZ_B2T_CPL_RSP_CPL_ADRS_WIDTH 7 | #define ESF_DZ_B2T_CPL_RSP_CPL_ADRS_WIDTH 7 | ||||
/* ES_fltr_info_wrd_mac_to_rx */ | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED2_LBN 112 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED2_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP2_LBN 96 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP2_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP1_LBN 80 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP1_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP0_LBN 64 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP0_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED1_LBN 48 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED1_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_SA_LBN 32 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_SA_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED0_LBN 8 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED0_WIDTH 24 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_LBN 7 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_PRIORITY_LBN 4 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_PRIORITY_WIDTH 3 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_SRC_LBN 0 | |||||
#define ESF_DZ_FLTR_INFO_MAC_TO_RX_SRC_WIDTH 4 | |||||
/* Enum DPCPU_INSTR_BRTYPE */ | |||||
#define ESE_DZ_BNEZAL 19 | |||||
#define ESE_DZ_BEQZAL 18 | |||||
#define ESE_DZ_BGEZAL 17 | |||||
#define ESE_DZ_BLTZAL 16 | |||||
#define ESE_DZ_BNEZ 3 | |||||
#define ESE_DZ_BEQZ 2 | |||||
#define ESE_DZ_BGEZ 1 | |||||
#define ESE_DZ_BLTZ 0 | |||||
/* Enum DPCPU_INSTR_FUNCT */ | /* ES_fltr_info_wrd_mc_pdma */ | ||||
#define ESE_DZ_MASKMOD 44 | #define ESF_DZ_FLTR_INFO_MC_PDMA_FLTR_OUT_LBN 64 | ||||
#define ESE_DZ_SLTU 43 | #define ESF_DZ_FLTR_INFO_MC_PDMA_FLTR_OUT_WIDTH 16 | ||||
#define ESE_DZ_SLT 42 | #define ESE_DZ_FLTR_MULTICAST_VLAN 512 | ||||
#define ESE_DZ_INCMOD 40 | #define ESE_DZ_FLTR_MAC_VLAN 256 | ||||
#define ESE_DZ_NOR 39 | #define ESE_DZ_FLTR_STRUCTURED7 128 | ||||
#define ESE_DZ_XOR 38 | #define ESE_DZ_FLTR_STRUCTURED6 64 | ||||
#define ESE_DZ_OR 37 | #define ESE_DZ_FLTR_STRUCTURED5 32 | ||||
#define ESE_DZ_AND 36 | #define ESE_DZ_FLTR_STRUCTURED4 16 | ||||
#define ESE_DZ_SUBU 35 | #define ESE_DZ_FLTR_STRUCTURED3 8 | ||||
#define ESE_DZ_SUB 34 | #define ESE_DZ_FLTR_STRUCTURED2 4 | ||||
#define ESE_DZ_ADDU 33 | #define ESE_DZ_FLTR_STRUCTURED1 2 | ||||
#define ESE_DZ_ADD 32 | #define ESE_DZ_FLTR_STRUCTURED0 1 | ||||
#define ESE_DZ_MULT 25 | #define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW0_LBN 16 | ||||
#define ESE_DZ_MFLO 18 | #define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW0_WIDTH 32 | ||||
#define ESE_DZ_MFHI 16 | #define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW1_LBN 48 | ||||
#define ESE_DZ_JALR 9 | #define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW1_WIDTH 16 | ||||
#define ESE_DZ_JR 8 | #define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_LBN 16 | ||||
#define ESE_DZ_SRAV 7 | #define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_WIDTH 48 | ||||
#define ESE_DZ_SRLV 6 | #define ESF_DZ_FLTR_INFO_MC_PDMA_DST_LBN 8 | ||||
#define ESE_DZ_SLLV 4 | #define ESF_DZ_FLTR_INFO_MC_PDMA_DST_WIDTH 8 | ||||
#define ESE_DZ_SRA 3 | #define ESE_DZ_DST_NCSI 64 | ||||
#define ESE_DZ_SRL 2 | #define ESE_DZ_DST_PORT0 32 | ||||
#define ESE_DZ_SLL 0 | #define ESE_DZ_DST_PORT1 16 | ||||
#define ESE_DZ_DST_PORT0_IPSEC 8 | |||||
#define ESE_DZ_DST_PORT1_IPSEC 4 | |||||
#define ESE_DZ_DST_PM 2 | |||||
#define ESE_DZ_DST_TIMESTAMP 1 | |||||
#define ESF_DZ_FLTR_INFO_MC_PDMA_PRIORITY_LBN 4 | |||||
#define ESF_DZ_FLTR_INFO_MC_PDMA_PRIORITY_WIDTH 4 | |||||
#define ESF_DZ_FLTR_INFO_MC_PDMA_SRC_LBN 0 | |||||
#define ESF_DZ_FLTR_INFO_MC_PDMA_SRC_WIDTH 4 | |||||
/* Enum DPCPU_INSTR_OP */ | |||||
#define ESE_DZ_LM_MSG 49 | |||||
#define ESE_DZ_MSG 48 | |||||
#define ESE_DZ_SHA 43 | |||||
#define ESE_DZ_SBA 42 | |||||
#define ESE_DZ_SH 41 | |||||
#define ESE_DZ_SB 40 | |||||
#define ESE_DZ_LHUA 39 | |||||
#define ESE_DZ_LBUA 38 | |||||
#define ESE_DZ_LHU 37 | |||||
#define ESE_DZ_LBU 36 | |||||
#define ESE_DZ_LHA 35 | |||||
#define ESE_DZ_LBA 34 | |||||
#define ESE_DZ_LH 33 | |||||
#define ESE_DZ_LB 32 | |||||
#define ESE_DZ_BGTU 31 | |||||
#define ESE_DZ_BLEU 30 | |||||
#define ESE_DZ_MODI 28 | |||||
#define ESE_DZ_NEGU 27 | |||||
#define ESE_DZ_NEG 26 | |||||
#define ESE_DZ_LI 25 | |||||
#define ESE_DZ_INCMODI 24 | |||||
#define ESE_DZ_BGT 23 | |||||
#define ESE_DZ_BLE 22 | |||||
#define ESE_DZ_BBS 21 | |||||
#define ESE_DZ_BBC 20 | |||||
#define ESE_DZ_JAL_EVT 19 | |||||
#define ESE_DZ_J_EVT 18 | |||||
#define ESE_DZ_HALT 16 | |||||
#define ESE_DZ_NORI 15 | |||||
#define ESE_DZ_XORI 14 | |||||
#define ESE_DZ_ORI 13 | |||||
#define ESE_DZ_ANDI 12 | |||||
#define ESE_DZ_SLTIU 11 | |||||
#define ESE_DZ_SLTI 10 | |||||
#define ESE_DZ_ADDIU 9 | |||||
#define ESE_DZ_ADDI 8 | |||||
#define ESE_DZ_BGTZ 7 | |||||
#define ESE_DZ_BLEZ 6 | |||||
#define ESE_DZ_BNE 5 | |||||
#define ESE_DZ_BEQ 4 | |||||
#define ESE_DZ_JAL 3 | |||||
#define ESE_DZ_J 2 | |||||
#define ESE_DZ_BRANCH 1 | |||||
#define ESE_DZ_REG2REG 0 | |||||
/* Enum DPCPU_MSG_DIR */ | /* ES_fltr_info_wrd_rxdi_to_rxdp */ | ||||
#define ESE_DPCPU_MSG_DZ_OUTB 0x1 | #define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_INNER_VLAN_LBN 112 | ||||
#define ESE_DPCPU_MSG_DZ_INB 0x0 | #define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_INNER_VLAN_WIDTH 16 | ||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OUTER_VLAN_LBN 96 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OUTER_VLAN_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH1_LBN 80 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH1_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH0_LBN 64 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH0_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP1_LBN 48 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP1_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP0_LBN 32 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP0_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_CNP_LBN 31 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_CNP_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IVP_LBN 30 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IVP_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OVP_LBN 29 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OVP_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST2_LBN 28 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST2_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST1_LBN 27 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST1_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST0_LBN 26 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RX_QID_LBN 16 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RX_QID_WIDTH 10 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_HOST_LBN 15 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_HOST_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_MC_LBN 14 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_MC_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P0_LBN 13 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P1_LBN 12 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P1_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED1_LBN 11 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED1_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_CRF_LBN 10 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_CRF_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED0_LBN 9 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_REPLAY_LBN 8 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_REPLAY_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IPSEC_LBN 7 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IPSEC_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_PRIORITY_LBN 4 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_PRIORITY_WIDTH 3 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_SRC_LBN 0 | |||||
#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_SRC_WIDTH 4 | |||||
/* Enum DPCPU_PDBUS_OP */ | |||||
#define ESE_DPCPU_PDBUS_DZ_RD 0x1 | |||||
#define ESE_DPCPU_PDBUS_DZ_WR 0x0 | |||||
/* ES_fltr_info_wrd_rxdp_to_host */ | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED3_LBN 33 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED3_WIDTH 31 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RMON_SOFT_LBN 32 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RMON_SOFT_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED2_LBN 27 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED2_WIDTH 5 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RX_QID_LBN 16 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RX_QID_WIDTH 11 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_HOST_LBN 15 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_HOST_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_MC_LBN 14 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_MC_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P0_LBN 13 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P1_LBN 12 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P1_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED1_LBN 11 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED1_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_CRF_LBN 10 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_CRF_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED0_LBN 9 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_REPLAY_LBN 8 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_REPLAY_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_IPSEC_LBN 7 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_IPSEC_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_PRIORITY_LBN 4 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_PRIORITY_WIDTH 3 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_SRC_LBN 0 | |||||
#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_SRC_WIDTH 4 | |||||
/* ES_fltr_info_wrd_tx_to_mac */ | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRV_LBN 63 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRV_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_LB_LBN 62 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_LB_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS0_LBN 61 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS1_LBN 60 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS1_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_NDI_LBN 59 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_NDI_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED2_LBN 48 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED2_WIDTH 11 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_SA_LBN 32 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_SA_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_STACK_ID_LBN 24 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_STACK_ID_WIDTH 8 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_DOMAIN_LBN 16 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_DOMAIN_WIDTH 8 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED1_LBN 14 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED1_WIDTH 2 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P0_LBN 13 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P1_LBN 12 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P1_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP0_LBN 11 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP1_LBN 10 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP1_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_PM_LBN 9 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_PM_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED0_LBN 8 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_LBN 7 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRIORITY_LBN 4 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRIORITY_WIDTH 3 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_SRC_LBN 0 | |||||
#define ESF_DZ_FLTR_INFO_TX_TO_MAC_SRC_WIDTH 4 | |||||
/* ES_fltr_info_wrd_txdi_to_txdp */ | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_INNER_VLAN_LBN 112 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_INNER_VLAN_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OUTER_VLAN_LBN 96 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OUTER_VLAN_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_CNP_LBN 95 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_CNP_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IVP_LBN 94 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IVP_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OVP_LBN 93 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OVP_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED4_LBN 90 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED4_WIDTH 3 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_QID_LBN 80 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_QID_WIDTH 10 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_LBN 79 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED3_LBN 78 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED3_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MTU_DIV4_LBN 66 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MTU_DIV4_WIDTH 12 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_OP_LBN 64 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_OP_WIDTH 2 | |||||
#define ESE_DZ_VRI_OP_INSERT_REPLACE 3 | |||||
#define ESE_DZ_VRI_OP_INSERT_INSERT 2 | |||||
#define ESE_DZ_VRI_OP_REPLACE 1 | |||||
#define ESE_DZ_VRI_OP_INSERT 0 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRV_LBN 63 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRV_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_LB_LBN 62 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_LB_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS0_LBN 61 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS1_LBN 60 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS1_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_NDI_LBN 59 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_NDI_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TXDP_CONTEXT_OUT_LBN 48 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TXDP_CONTEXT_OUT_WIDTH 11 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_SA_LBN 32 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_SA_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_STACK_ID_LBN 24 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_STACK_ID_WIDTH 8 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_DOMAIN_LBN 16 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_DOMAIN_WIDTH 8 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED1_LBN 14 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED1_WIDTH 2 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P0_LBN 13 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P1_LBN 12 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P1_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP0_LBN 11 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP1_LBN 10 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP1_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_PM_LBN 9 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_PM_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED0_LBN 8 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_LBN 7 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRIORITY_LBN 4 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRIORITY_WIDTH 3 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_SRC_LBN 0 | |||||
#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_SRC_WIDTH 4 | |||||
/* ES_fltr_info_wrd_txdp_to_txdi */ | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_VLAN_OP_LBN 62 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_VLAN_OP_WIDTH 2 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED1_LBN 58 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED1_WIDTH 4 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TX_QID_LBN 48 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TX_QID_WIDTH 10 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_INNER_VLAN_LBN 32 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_INNER_VLAN_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_OUTER_VLAN_LBN 16 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_OUTER_VLAN_WIDTH 16 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TXDP_CONTEXT_IN_LBN 5 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TXDP_CONTEXT_IN_WIDTH 11 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED0_LBN 4 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED0_WIDTH 1 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_SRC_LBN 0 | |||||
#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_SRC_WIDTH 4 | |||||
/* ES_nwk_ev_merge_blk_cmd */ | |||||
#define ESF_DZ_EV_MERGE_BLK_COMMAND_OP_LBN 28 | |||||
#define ESF_DZ_EV_MERGE_BLK_COMMAND_OP_WIDTH 4 | |||||
#define ESE_DZ_EV_MERGE_BLK_COMMAND_OP_FLUSH 2 | |||||
#define ESE_DZ_EV_MERGE_BLK_COMMAND_OP_ENABLE 1 | |||||
#define ESE_DZ_EV_MERGE_BLK_COMMAND_OP_DISABLE 0 | |||||
#define ESF_DZ_EV_MERGE_BLK_COMMAND_BUSY_LBN 31 | |||||
#define ESF_DZ_EV_MERGE_BLK_COMMAND_BUSY_WIDTH 1 | |||||
#define ESF_DZ_EV_MERGE_BLK_COMMAND_EVQ_IDX_LBN 0 | |||||
#define ESF_DZ_EV_MERGE_BLK_COMMAND_EVQ_IDX_WIDTH 11 | |||||
/* ES_txpm2ini_cpl_rsp */ | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ECC_LBN 284 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ECC_WIDTH 32 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_EOT_LBN 283 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_EOT_WIDTH 1 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW0_LBN 27 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW0_WIDTH 32 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW1_LBN 59 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW1_WIDTH 32 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW2_LBN 91 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW2_WIDTH 32 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW3_LBN 123 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW3_WIDTH 32 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW4_LBN 155 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW4_WIDTH 32 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW5_LBN 187 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW5_WIDTH 32 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW6_LBN 219 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW6_WIDTH 32 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW7_LBN 251 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW7_WIDTH 32 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_LBN 27 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_WIDTH 256 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ERROR_LBN 26 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ERROR_WIDTH 1 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LAST_LBN 25 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LAST_WIDTH 1 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_TAG_LBN 19 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_TAG_WIDTH 6 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LEN_LBN 7 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LEN_WIDTH 12 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ADRS_LBN 0 | |||||
#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ADRS_WIDTH 7 | |||||
/* Enum INI_OP */ | /* Enum INI_OP */ | ||||
#define ESE_DZ_RD_COMPL 0x3 | #define ESE_DZ_RD_COMPL 0x3 | ||||
#define ESE_DZ_NOP 0x2 | #define ESE_DZ_NOP 0x2 | ||||
#define ESE_DZ_WR 0x1 | #define ESE_DZ_WR 0x1 | ||||
#define ESE_DZ_RD 0x0 | #define ESE_DZ_RD 0x0 | ||||
/* Enum INT_OP */ | /* Enum INT_OP */ | ||||
#define ESE_DZ_LEGACY 0x2 | #define ESE_DZ_LEGACY 0x2 | ||||
#define ESE_DZ_MSI 0x1 | #define ESE_DZ_MSI 0x1 | ||||
#define ESE_DZ_MSIX 0x0 | #define ESE_DZ_MSIX 0x0 | ||||
/* Enum MC_PDMA_BUFFER_ID */ | |||||
#define ESE_DZ_MC_PDMA_BUFFER_ALL 4 | |||||
#define ESE_DZ_MC_PDMA_BUFFER_RXDP 3 | |||||
#define ESE_DZ_MC_PDMA_BUFFER_NCSI 2 | |||||
#define ESE_DZ_MC_PDMA_BUFFER_NWPORT1 1 | |||||
#define ESE_DZ_MC_PDMA_BUFFER_NWPORT0 0 | |||||
/* Enum MC_PDMA_INTERFACE_ID */ | |||||
#define ESE_DZ_MC_PDMA_INTERFACE_RXDP 3 | |||||
#define ESE_DZ_MC_PDMA_INTERFACE_NCSI 2 | |||||
#define ESE_DZ_MC_PDMA_INTERFACE_NWPORT1 1 | |||||
#define ESE_DZ_MC_PDMA_INTERFACE_NWPORT0 0 | |||||
/* Enum PKT_STRM_CTL */ | /* Enum PKT_STRM_CTL */ | ||||
#define ESE_DZ_EOP_TRUNC 0x3 | #define ESE_DZ_EOP_TRUNC 0x3 | ||||
#define ESE_DZ_EOP_CRC_ERR 0x2 | #define ESE_DZ_EOP_CRC_ERR 0x2 | ||||
#define ESE_DZ_EOP 0x1 | #define ESE_DZ_EOP 0x1 | ||||
#define ESE_DZ_NOOP 0x0 | #define ESE_DZ_NOOP 0x0 | ||||
/* Enum PM_EPI_PKT_MARKER */ | /* Enum PM_EPI_PKT_MARKER */ | ||||
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