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head/sys/dev/bhnd/cores/chipc/chipcreg.h
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#define CHIPC_SRC_SIZE_MASK 0x00000006 | #define CHIPC_SRC_SIZE_MASK 0x00000006 | ||||
#define CHIPC_SRC_SIZE_1K 0x00000000 | #define CHIPC_SRC_SIZE_1K 0x00000000 | ||||
#define CHIPC_SRC_SIZE_4K 0x00000002 | #define CHIPC_SRC_SIZE_4K 0x00000002 | ||||
#define CHIPC_SRC_SIZE_16K 0x00000004 | #define CHIPC_SRC_SIZE_16K 0x00000004 | ||||
#define CHIPC_SRC_SIZE_SHIFT 1 | #define CHIPC_SRC_SIZE_SHIFT 1 | ||||
#define CHIPC_SRC_PRESENT 0x00000001 | #define CHIPC_SRC_PRESENT 0x00000001 | ||||
/* gpiotimerval */ | /* gpiotimerval */ | ||||
#define CHIPC_GPIO_ONTIME_SHIFT 16 | #define CHIPC_GPIO_ONTIME_SHIFT 16 | ||||
#define CHIPC_GPIOTIMERVAL_DEFAULT_ON 10 /**< default 10% on duty cycle */ | |||||
#define CHIPC_GPIOTIMERVAL_DEFAULT_OFF 90 /**< default 90% off duty cycle */ | |||||
#define CHIPC_GPIOTIMERVAL_DEFAULT \ | |||||
((CHIPC_GPIOTIMERVAL_DEFAULT_ON << CHIPC_GPIO_ONTIME_SHIFT) | \ | |||||
(CHIPC_GPIOTIMERVAL_DEFAULT_OFF)) | |||||
/* clockcontrol_n */ | /* clockcontrol_n */ | ||||
#define CHIPC_CN_N1_MASK 0x3f /* n1 control */ | #define CHIPC_CN_N1_MASK 0x3f /* n1 control */ | ||||
#define CHIPC_CN_N1_SHIFT 0 | #define CHIPC_CN_N1_SHIFT 0 | ||||
#define CHIPC_CN_N2_MASK 0x3f00 /* n2 control */ | #define CHIPC_CN_N2_MASK 0x3f00 /* n2 control */ | ||||
#define CHIPC_CN_N2_SHIFT 8 | #define CHIPC_CN_N2_SHIFT 8 | ||||
#define CHIPC_CN_PLLC_MASK 0xf0000 /* pll control */ | #define CHIPC_CN_PLLC_MASK 0xf0000 /* pll control */ | ||||
#define CHIPC_CN_PLLC_SHIFT 16 | #define CHIPC_CN_PLLC_SHIFT 16 | ||||
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