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sys/dev/bhnd/cores/pmu/bhnd_pmureg.h
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#define BHND_PMU_RES_REQ_TIMER_SEL 0x640 | #define BHND_PMU_RES_REQ_TIMER_SEL 0x640 | ||||
#define BHND_PMU_RES_REQ_TIMER 0x644 | #define BHND_PMU_RES_REQ_TIMER 0x644 | ||||
#define BHND_PMU_RRQT_TIME_MASK 0x03ff | #define BHND_PMU_RRQT_TIME_MASK 0x03ff | ||||
#define BHND_PMU_RRQT_INTEN 0x0400 | #define BHND_PMU_RRQT_INTEN 0x0400 | ||||
#define BHND_PMU_RRQT_REQ_ACTIVE 0x0800 | #define BHND_PMU_RRQT_REQ_ACTIVE 0x0800 | ||||
#define BHND_PMU_RRQT_ALP_REQ 0x1000 | #define BHND_PMU_RRQT_ALP_REQ 0x1000 | ||||
#define BHND_PMU_RRQT_HT_REQ 0x2000 | #define BHND_PMU_RRQT_HT_REQ 0x2000 | ||||
#define BHND_PMU_RES_REQ_MASK 0x648 | #define BHND_PMU_RES_REQ_MASK 0x648 | ||||
#define BHND_PMU_CHIPCTL_ADDR 0x650 | #define BHND_PMU_CHIP_CONTROL_ADDR 0x650 | ||||
#define BHND_PMU_CHIPCTL_DATA 0x654 | #define BHND_PMU_CHIP_CONTROL_DATA 0x654 | ||||
#define BHND_PMU_REG_CONTROL_ADDR 0x658 | #define BHND_PMU_REG_CONTROL_ADDR 0x658 | ||||
#define BHND_PMU_REG_CONTROL_DATA 0x65C | #define BHND_PMU_REG_CONTROL_DATA 0x65C | ||||
#define BHND_PMU_PLL_CONTROL_ADDR 0x660 | #define BHND_PMU_PLL_CONTROL_ADDR 0x660 | ||||
#define BHND_PMU_PLL_CONTROL_DATA 0x664 | #define BHND_PMU_PLL_CONTROL_DATA 0x664 | ||||
#define BHND_PMU_STRAPOPT 0x668 /* chipc rev >= 28 */ | #define BHND_PMU_STRAPOPT 0x668 /* chipc rev >= 28 */ | ||||
#define BHND_PMU_XTALFREQ 0x66C /* pmu rev >= 10 */ | #define BHND_PMU_XTALFREQ 0x66C /* pmu rev >= 10 */ | ||||
/* PMU resource bit position */ | /* PMU resource bit position */ | ||||
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#define BHND_PMU_RES5354_XTAL_PU 15 /* 0x08000 */ | #define BHND_PMU_RES5354_XTAL_PU 15 /* 0x08000 */ | ||||
#define BHND_PMU_RES5354_XTAL_EN 16 /* 0x10000 */ | #define BHND_PMU_RES5354_XTAL_EN 16 /* 0x10000 */ | ||||
#define BHND_PMU_RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ | #define BHND_PMU_RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ | ||||
#define BHND_PMU_RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ | #define BHND_PMU_RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ | ||||
#define BHND_PMU_RES5354_BB_PLL_PU 19 /* 0x80000 */ | #define BHND_PMU_RES5354_BB_PLL_PU 19 /* 0x80000 */ | ||||
/* 5357 chip-specific CHIPCTRL register bits */ | /* 5357 chip-specific CHIPCTRL register bits */ | ||||
#define BHND_PMU_CCTRL5357_EXTPA (1<<14) /* extPA in CHIPCTL1, bit 14 */ | #define BHND_PMU_CCTRL5357_EXTPA (1<<14) /* extPA in CHIPCTRL1, bit 14 */ | ||||
#define BHND_PMU_CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in CHIPCTL1, bit 15 */ | #define BHND_PMU_CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in CHIPCTRL1, bit 15 */ | ||||
/* 4328 PMU resources */ | /* 4328 PMU resources */ | ||||
#define BHND_PMU_RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ | #define BHND_PMU_RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ | ||||
#define BHND_PMU_RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ | #define BHND_PMU_RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ | ||||
#define BHND_PMU_RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ | #define BHND_PMU_RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ | ||||
#define BHND_PMU_RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ | #define BHND_PMU_RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ | ||||
#define BHND_PMU_RES4328_ILP_REQUEST 4 /* 0x00010 */ | #define BHND_PMU_RES4328_ILP_REQUEST 4 /* 0x00010 */ | ||||
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#define BHND_PMU_RES4322_SI_PLL_ON 4 | #define BHND_PMU_RES4322_SI_PLL_ON 4 | ||||
#define BHND_PMU_RES4322_HT_SI_AVAIL 5 | #define BHND_PMU_RES4322_HT_SI_AVAIL 5 | ||||
#define BHND_PMU_RES4322_PHY_PLL_ON 6 | #define BHND_PMU_RES4322_PHY_PLL_ON 6 | ||||
#define BHND_PMU_RES4322_HT_PHY_AVAIL 7 | #define BHND_PMU_RES4322_HT_PHY_AVAIL 7 | ||||
#define BHND_PMU_RES4322_OTP_PU 8 | #define BHND_PMU_RES4322_OTP_PU 8 | ||||
/* 43224 chip-specific CHIPCTRL register bits */ | /* 43224 chip-specific CHIPCTRL register bits */ | ||||
#define BHND_PMU_CCTRL_43224_GPIO_TOGGLE 0x8000 | #define BHND_PMU_CCTRL43224_GPIO_TOGGLE 0x8000 | ||||
#define BHND_PMU_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ | #define BHND_PMU_CCTRL43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ | ||||
#define BHND_PMU_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ | #define BHND_PMU_CCTRL43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ | ||||
/* 43236 PMU resources */ | /* 43236 PMU resources */ | ||||
#define BHND_PMU_RES43236_REGULATOR 0 | #define BHND_PMU_RES43236_REGULATOR 0 | ||||
#define BHND_PMU_RES43236_ILP_REQUEST 1 | #define BHND_PMU_RES43236_ILP_REQUEST 1 | ||||
#define BHND_PMU_RES43236_XTAL_PU 2 | #define BHND_PMU_RES43236_XTAL_PU 2 | ||||
#define BHND_PMU_RES43236_ALP_AVAIL 3 | #define BHND_PMU_RES43236_ALP_AVAIL 3 | ||||
#define BHND_PMU_RES43236_SI_PLL_ON 4 | #define BHND_PMU_RES43236_SI_PLL_ON 4 | ||||
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#define BHND_PMU_RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ | #define BHND_PMU_RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ | ||||
#define BHND_PMU_RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ | #define BHND_PMU_RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ | ||||
#define BHND_PMU_RES4319_HT_AVAIL 21 /* 0x00200000 */ | #define BHND_PMU_RES4319_HT_AVAIL 21 /* 0x00200000 */ | ||||
/* 4319 chip-specific CHIPCTL register bits */ | /* 4319 chip-specific CHIPCTL register bits */ | ||||
#define BHND_PMU1_PLL0_CHIPCTL0 0 | #define BHND_PMU1_PLL0_CHIPCTL0 0 | ||||
#define BHND_PMU1_PLL0_CHIPCTL1 1 | #define BHND_PMU1_PLL0_CHIPCTL1 1 | ||||
#define BHND_PMU1_PLL0_CHIPCTL2 2 | #define BHND_PMU1_PLL0_CHIPCTL2 2 | ||||
#define BHND_PMU_CCTL_4319USB_XTAL_SEL_MASK 0x00180000 | #define BHND_PMU_CCTRL4319USB_XTAL_SEL_MASK 0x00180000 | ||||
#define BHND_PMU_CCTL_4319USB_XTAL_SEL_SHIFT 19 | #define BHND_PMU_CCTRL4319USB_XTAL_SEL_SHIFT 19 | ||||
#define BHND_PMU_CCTL_4319USB_48MHZ_PLL_SEL 1 | #define BHND_PMU_CCTRL4319USB_48MHZ_PLL_SEL 1 | ||||
#define BHND_PMU_CCTL_4319USB_24MHZ_PLL_SEL 2 | #define BHND_PMU_CCTRL4319USB_24MHZ_PLL_SEL 2 | ||||
/* 4336 PMU resources */ | /* 4336 PMU resources */ | ||||
#define BHND_PMU_RES4336_CBUCK_LPOM 0 | #define BHND_PMU_RES4336_CBUCK_LPOM 0 | ||||
#define BHND_PMU_RES4336_CBUCK_BURST 1 | #define BHND_PMU_RES4336_CBUCK_BURST 1 | ||||
#define BHND_PMU_RES4336_CBUCK_LP_PWM 2 | #define BHND_PMU_RES4336_CBUCK_LP_PWM 2 | ||||
#define BHND_PMU_RES4336_CBUCK_PWM 3 | #define BHND_PMU_RES4336_CBUCK_PWM 3 | ||||
#define BHND_PMU_RES4336_CLDO_PU 4 | #define BHND_PMU_RES4336_CLDO_PU 4 | ||||
#define BHND_PMU_RES4336_DIS_INT_RESET_PD 5 | #define BHND_PMU_RES4336_DIS_INT_RESET_PD 5 | ||||
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#define BHND_PMU_RES4313_BB_PWRSW_RSRC 10 | #define BHND_PMU_RES4313_BB_PWRSW_RSRC 10 | ||||
#define BHND_PMU_RES4313_SYNTH_PWRSW_RSRC 11 | #define BHND_PMU_RES4313_SYNTH_PWRSW_RSRC 11 | ||||
#define BHND_PMU_RES4313_MISC_PWRSW_RSRC 12 | #define BHND_PMU_RES4313_MISC_PWRSW_RSRC 12 | ||||
#define BHND_PMU_RES4313_BB_PLL_PWRSW_RSRC 13 | #define BHND_PMU_RES4313_BB_PLL_PWRSW_RSRC 13 | ||||
#define BHND_PMU_RES4313_HT_AVAIL_RSRC 14 | #define BHND_PMU_RES4313_HT_AVAIL_RSRC 14 | ||||
#define BHND_PMU_RES4313_MACPHY_CLK_AVAIL_RSRC 15 | #define BHND_PMU_RES4313_MACPHY_CLK_AVAIL_RSRC 15 | ||||
/* 4313 chip-specific CHIPCTRL register bits */ | /* 4313 chip-specific CHIPCTRL register bits */ | ||||
#define BHND_PMU_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ | #define BHND_PMU_CCTRL4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ | ||||
/* 43228 resources */ | /* 43228 resources */ | ||||
#define BHND_PMU_RES43228_NOT_USED 0 | #define BHND_PMU_RES43228_NOT_USED 0 | ||||
#define BHND_PMU_RES43228_ILP_REQUEST 1 | #define BHND_PMU_RES43228_ILP_REQUEST 1 | ||||
#define BHND_PMU_RES43228_XTAL_PU 2 | #define BHND_PMU_RES43228_XTAL_PU 2 | ||||
#define BHND_PMU_RES43228_ALP_AVAIL 3 | #define BHND_PMU_RES43228_ALP_AVAIL 3 | ||||
#define BHND_PMU_RES43228_PLL_EN 4 | #define BHND_PMU_RES43228_PLL_EN 4 | ||||
#define BHND_PMU_RES43228_HT_PHY_AVAIL 5 | #define BHND_PMU_RES43228_HT_PHY_AVAIL 5 | ||||
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