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head/sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c
Show All 39 Lines | |||||
#include <machine/bus.h> | #include <machine/bus.h> | ||||
#include <sys/rman.h> | #include <sys/rman.h> | ||||
#include <machine/resource.h> | #include <machine/resource.h> | ||||
#include <dev/pci/pcireg.h> | #include <dev/pci/pcireg.h> | ||||
#include <dev/pci/pcivar.h> | #include <dev/pci/pcivar.h> | ||||
#include <dev/bhnd/cores/pci/bhnd_pcireg.h> | |||||
#include <dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h> | |||||
#include "bhndbvar.h" | #include "bhndbvar.h" | ||||
#include "bhndb_pcireg.h" | #include "bhndb_pcireg.h" | ||||
static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0; | static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0; | ||||
static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci; | static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci; | ||||
static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie; | static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie; | ||||
static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2; | static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2; | ||||
static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3; | static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3; | ||||
Show All 39 Lines | /* bar0+0x0000: configurable backplane window */ | ||||
.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, | .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, | ||||
.d.dyn = { | .d.dyn = { | ||||
.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL | .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL | ||||
}, | }, | ||||
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } | .res = { SYS_RES_MEMORY, PCIR_BAR(0) } | ||||
}, | }, | ||||
BHNDB_REGWIN_TABLE_END | BHNDB_REGWIN_TABLE_END | ||||
}, | }, | ||||
/* DMA unsupported under generic configuration */ | |||||
.dma_translations = NULL, | |||||
}; | }; | ||||
/** | /** | ||||
* Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based | * Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based | ||||
* PCI devices; this configuration is adequate for enumerating a bridged | * PCI devices; this configuration is adequate for enumerating a bridged | ||||
* bcma(4) bus to determine the full hardware configuration. | * bcma(4) bus to determine the full hardware configuration. | ||||
* | * | ||||
Show All 31 Lines | /* bar0+0x3000: chipc core registers */ | ||||
.region = 0, | .region = 0, | ||||
.port_type = BHND_PORT_DEVICE | .port_type = BHND_PORT_DEVICE | ||||
}, | }, | ||||
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } | .res = { SYS_RES_MEMORY, PCIR_BAR(0) } | ||||
}, | }, | ||||
BHNDB_REGWIN_TABLE_END | BHNDB_REGWIN_TABLE_END | ||||
}, | }, | ||||
/* DMA unsupported under generic configuration */ | |||||
.dma_translations = NULL, | |||||
}; | }; | ||||
/** | /** | ||||
* Hardware configuration tables for Broadcom HND PCI NICs. | * Hardware configuration tables for Broadcom HND PCI NICs. | ||||
*/ | */ | ||||
const struct bhndb_hw bhndb_pci_generic_hw_table[] = { | const struct bhndb_hw bhndb_pci_generic_hw_table[] = { | ||||
/* PCI/V0 WLAN */ | /* PCI/V0 WLAN */ | ||||
BHNDB_HW_MATCH("PCI/v0 WLAN", v0, | BHNDB_HW_MATCH("PCI/v0 WLAN", v0, | ||||
▲ Show 20 Lines • Show All 156 Lines • ▼ Show 20 Lines | /* bar0+0x1800: pci core registers */ | ||||
.port = 0, | .port = 0, | ||||
.region = 0, | .region = 0, | ||||
.port_type = BHND_PORT_DEVICE | .port_type = BHND_PORT_DEVICE | ||||
}, | }, | ||||
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } | .res = { SYS_RES_MEMORY, PCIR_BAR(0) } | ||||
}, | }, | ||||
BHNDB_REGWIN_TABLE_END | BHNDB_REGWIN_TABLE_END | ||||
}, | }, | ||||
.dma_translations = (const struct bhnd_dma_translation[]) { | |||||
{ | |||||
.base_addr = BHND_PCI_DMA32_TRANSLATION, | |||||
.addr_mask = ~BHND_PCI_DMA32_MASK, | |||||
.addrext_mask = BHND_PCI_DMA32_MASK | |||||
}, | |||||
BHND_DMA_TRANSLATION_TABLE_END | |||||
} | |||||
}; | }; | ||||
/** | /** | ||||
* PCI_V1 (PCI-only) hardware configuration (PCI version) | * PCI_V1 (PCI-only) hardware configuration (PCI version) | ||||
* | * | ||||
* Applies to: | * Applies to: | ||||
* - PCI (cid=0x804, revision >= 13) | * - PCI (cid=0x804, revision >= 13) | ||||
*/ | */ | ||||
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines | /* bar0+0x3000: chipc core registers */ | ||||
.region = 0, | .region = 0, | ||||
.port_type = BHND_PORT_DEVICE | .port_type = BHND_PORT_DEVICE | ||||
}, | }, | ||||
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } | .res = { SYS_RES_MEMORY, PCIR_BAR(0) } | ||||
}, | }, | ||||
BHNDB_REGWIN_TABLE_END | BHNDB_REGWIN_TABLE_END | ||||
}, | }, | ||||
.dma_translations = (const struct bhnd_dma_translation[]) { | |||||
{ | |||||
.base_addr = BHND_PCI_DMA32_TRANSLATION, | |||||
.addr_mask = ~BHND_PCI_DMA32_MASK, | |||||
.addrext_mask = BHND_PCI_DMA32_MASK | |||||
}, | |||||
BHND_DMA_TRANSLATION_TABLE_END | |||||
} | |||||
}; | }; | ||||
/** | /** | ||||
* PCI_V1 hardware configuration (PCIE version). | * PCI_V1 hardware configuration (PCIE version). | ||||
* | * | ||||
* Applies to: | * Applies to: | ||||
* - PCIE (cid=0x820) with ChipCommon (revision <= 31) | * - PCIE (cid=0x820) with ChipCommon (revision <= 31) | ||||
*/ | */ | ||||
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines | /* bar0+0x3000: chipc core registers */ | ||||
.region = 0, | .region = 0, | ||||
.port_type = BHND_PORT_DEVICE | .port_type = BHND_PORT_DEVICE | ||||
}, | }, | ||||
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } | .res = { SYS_RES_MEMORY, PCIR_BAR(0) } | ||||
}, | }, | ||||
BHNDB_REGWIN_TABLE_END | BHNDB_REGWIN_TABLE_END | ||||
}, | }, | ||||
.dma_translations = (const struct bhnd_dma_translation[]) { | |||||
{ | |||||
.base_addr = BHND_PCIE_DMA32_TRANSLATION, | |||||
.addr_mask = ~BHND_PCIE_DMA32_MASK, | |||||
.addrext_mask = BHND_PCIE_DMA32_MASK | |||||
}, | |||||
{ | |||||
.base_addr = BHND_PCIE_DMA64_TRANSLATION, | |||||
.addr_mask = ~BHND_PCIE_DMA64_MASK, | |||||
.addrext_mask = 0 | |||||
}, | |||||
BHND_DMA_TRANSLATION_TABLE_END | |||||
} | |||||
}; | }; | ||||
/** | /** | ||||
* PCI_V2 hardware configuration. | * PCI_V2 hardware configuration. | ||||
* | * | ||||
* Applies to: | * Applies to: | ||||
* - PCIE (cid=0x820) with ChipCommon (revision >= 32) | * - PCIE (cid=0x820) with ChipCommon (revision >= 32) | ||||
*/ | */ | ||||
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines | /* bar0+0x3000: chipc core registers */ | ||||
.region = 0, | .region = 0, | ||||
.port_type = BHND_PORT_DEVICE | .port_type = BHND_PORT_DEVICE | ||||
}, | }, | ||||
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } | .res = { SYS_RES_MEMORY, PCIR_BAR(0) } | ||||
}, | }, | ||||
BHNDB_REGWIN_TABLE_END | BHNDB_REGWIN_TABLE_END | ||||
}, | }, | ||||
.dma_translations = (const struct bhnd_dma_translation[]) { | |||||
{ | |||||
.base_addr = BHND_PCIE_DMA32_TRANSLATION, | |||||
.addr_mask = ~BHND_PCIE_DMA32_MASK, | |||||
.addrext_mask = BHND_PCIE_DMA32_MASK | |||||
}, | |||||
{ | |||||
.base_addr = BHND_PCIE_DMA64_TRANSLATION, | |||||
.addr_mask = ~BHND_PCIE_DMA64_MASK, | |||||
.addrext_mask = 0 | |||||
}, | |||||
BHND_DMA_TRANSLATION_TABLE_END | |||||
} | |||||
}; | }; | ||||
/** | /** | ||||
* PCI_V3 hardware configuration. | * PCI_V3 hardware configuration. | ||||
* | * | ||||
* Applies to: | * Applies to: | ||||
* - PCIE2 (cid=0x83c) | * - PCIE2 (cid=0x83c) | ||||
*/ | */ | ||||
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines | /* bar0+0x3000: chipc core registers */ | ||||
.region = 0, | .region = 0, | ||||
.port_type = BHND_PORT_DEVICE | .port_type = BHND_PORT_DEVICE | ||||
}, | }, | ||||
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } | .res = { SYS_RES_MEMORY, PCIR_BAR(0) } | ||||
}, | }, | ||||
BHNDB_REGWIN_TABLE_END | BHNDB_REGWIN_TABLE_END | ||||
}, | }, | ||||
.dma_translations = (const struct bhnd_dma_translation[]) { | |||||
{ | |||||
.base_addr = BHND_PCIE2_DMA64_TRANSLATION, | |||||
.addr_mask = ~BHND_PCIE2_DMA64_MASK, | |||||
.addrext_mask = 0 | |||||
}, | |||||
BHND_DMA_TRANSLATION_TABLE_END | |||||
} | |||||
}; | }; |