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	/* Saved Program Status Register */			/* Saved Program Status Register */
	#define DBG_SPSR_SS (0x1 << 21)			#define DBG_SPSR_SS (0x1 << 21)

	/* Monitor Debug System Control Register */			/* Monitor Debug System Control Register */
	#define DBG_MDSCR_SS (0x1 << 0)			#define DBG_MDSCR_SS (0x1 << 0)
	#define DBG_MDSCR_KDE (0x1 << 13)			#define DBG_MDSCR_KDE (0x1 << 13)
	#define DBG_MDSCR_MDE (0x1 << 15)			#define DBG_MDSCR_MDE (0x1 << 15)

				/* Perfomance Monitoring Counters */
				#define PMCR_E (1 << 0) /* Enable all counters */
				#define PMCR_P (1 << 1) /* Reset all counters */
				#define PMCR_C (1 << 2) /* Clock counter reset */
				#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */
				#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */
				#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
				#define PMCR_LC (1 << 6) /* Long cycle count enable */
				#define PMCR_IMP_S 24 /* Implementer code shift */
				#define PMCR_IMP_M 0xff
				#define PMCR_IDCODE_S 16 /* Identification code shift */
				#define PMCR_IDCODE_M 0xff
				#define PMCR_IDCODE_CORTEX_A57 0x01
				#define PMCR_IDCODE_CORTEX_A72 0x02
				#define PMCR_IDCODE_CORTEX_A53 0x03
				#define PMCR_N_S 11 /* Number of counters implemented */
				#define PMCR_N_M 0x1f

	#endif /* !_MACHINE_ARMREG_H_ */			#endif /* !_MACHINE_ARMREG_H_ */