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sys/sys/pmc.h
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* some way for PMC operations. CPU names are grouped by manufacturer | * some way for PMC operations. CPU names are grouped by manufacturer | ||||
* and numbered sparsely in order to minimize changes to the ABI involved | * and numbered sparsely in order to minimize changes to the ABI involved | ||||
* when new CPUs are added. | * when new CPUs are added. | ||||
*/ | */ | ||||
#define __PMC_CPUS() \ | #define __PMC_CPUS() \ | ||||
__PMC_CPU(AMD_K7, 0x00, "AMD K7") \ | __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ | ||||
__PMC_CPU(AMD_K8, 0x01, "AMD K8") \ | __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ | ||||
__PMC_CPU(ARMV7, 0x500, "ARMv7") \ | |||||
__PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \ | __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \ | ||||
__PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \ | __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \ | ||||
__PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \ | __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \ | ||||
__PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \ | __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \ | ||||
__PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \ | __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \ | ||||
__PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \ | __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \ | ||||
__PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \ | __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \ | ||||
__PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ | __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ | ||||
Show All 15 Lines | #define __PMC_CPUS() \ | ||||
__PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ | __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ | ||||
__PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ | __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ | ||||
__PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ | __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ | ||||
__PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \ | __PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \ | ||||
__PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ | __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ | ||||
__PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ | __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ | ||||
__PMC_CPU(PPC_MPC85XX, 0x340, "Freescale PowerPC MPC85XX") \ | __PMC_CPU(PPC_MPC85XX, 0x340, "Freescale PowerPC MPC85XX") \ | ||||
__PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ | __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ | ||||
__PMC_CPU(GENERIC, 0x400, "Generic") | __PMC_CPU(GENERIC, 0x400, "Generic") \ | ||||
__PMC_CPU(ARMV7, 0x500, "ARMv7") \ | |||||
bz: The list is sorted differently. I was wondering if we want some "sparser" allocation scheme... | |||||
Not Done Inline ActionsYeah, the sorting here is rather unfortunate. I'd suggest we rearrange the list and group by processor family, with comments between. Having ARMV7 up near the top with 0x500 is confusing. emaste: Yeah, the sorting here is rather unfortunate. I'd suggest we rearrange the list and group by… | |||||
Not Done Inline ActionsI don't think it makes sence to guess what ARM will name their next design. I don't think it will be an A5x given they have jumped to Cortex-A72. andrew: I don't think it makes sence to guess what ARM will name their next design. I don't think it… | |||||
__PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ | |||||
__PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") | |||||
enum pmc_cputype { | enum pmc_cputype { | ||||
#undef __PMC_CPU | #undef __PMC_CPU | ||||
#define __PMC_CPU(S,V,D) PMC_CPU_##S = V, | #define __PMC_CPU(S,V,D) PMC_CPU_##S = V, | ||||
__PMC_CPUS() | __PMC_CPUS() | ||||
}; | }; | ||||
#define PMC_CPU_FIRST PMC_CPU_AMD_K7 | #define PMC_CPU_FIRST PMC_CPU_AMD_K7 | ||||
Show All 11 Lines | #define __PMC_CLASSES() \ | ||||
__PMC_CLASS(P6) /* Intel Pentium Pro counters */ \ | __PMC_CLASS(P6) /* Intel Pentium Pro counters */ \ | ||||
__PMC_CLASS(P4) /* Intel Pentium-IV counters */ \ | __PMC_CLASS(P4) /* Intel Pentium-IV counters */ \ | ||||
__PMC_CLASS(IAF) /* Intel Core2/Atom, fixed function */ \ | __PMC_CLASS(IAF) /* Intel Core2/Atom, fixed function */ \ | ||||
__PMC_CLASS(IAP) /* Intel Core...Atom, programmable */ \ | __PMC_CLASS(IAP) /* Intel Core...Atom, programmable */ \ | ||||
__PMC_CLASS(UCF) /* Intel Uncore fixed function */ \ | __PMC_CLASS(UCF) /* Intel Uncore fixed function */ \ | ||||
__PMC_CLASS(UCP) /* Intel Uncore programmable */ \ | __PMC_CLASS(UCP) /* Intel Uncore programmable */ \ | ||||
__PMC_CLASS(XSCALE) /* Intel XScale counters */ \ | __PMC_CLASS(XSCALE) /* Intel XScale counters */ \ | ||||
__PMC_CLASS(ARMV7) /* ARMv7 */ \ | __PMC_CLASS(ARMV7) /* ARMv7 */ \ | ||||
__PMC_CLASS(ARMV8) /* ARMv8 */ \ | |||||
Not Done Inline ActionsNote that this breaks the ABI since these enums get implicit values rather than explicit ones like __PMC_CPU() does. I would really like us to fix this to also use explicit values, but that is outside the scope of this change. jhb: Note that this breaks the ABI since these enums get implicit values rather than explicit ones… | |||||
Not Done Inline Actionsthat is true, all the classes below will require recompile libpmc br: that is true, all the classes below will require recompile libpmc | |||||
__PMC_CLASS(MIPS24K) /* MIPS 24K */ \ | __PMC_CLASS(MIPS24K) /* MIPS 24K */ \ | ||||
__PMC_CLASS(OCTEON) /* Cavium Octeon */ \ | __PMC_CLASS(OCTEON) /* Cavium Octeon */ \ | ||||
__PMC_CLASS(MIPS74K) /* MIPS 74K */ \ | __PMC_CLASS(MIPS74K) /* MIPS 74K */ \ | ||||
__PMC_CLASS(PPC7450) /* Motorola MPC7450 class */ \ | __PMC_CLASS(PPC7450) /* Motorola MPC7450 class */ \ | ||||
__PMC_CLASS(PPC970) /* IBM PowerPC 970 class */ \ | __PMC_CLASS(PPC970) /* IBM PowerPC 970 class */ \ | ||||
__PMC_CLASS(E500) /* Freescale e500 class */ \ | __PMC_CLASS(E500) /* Freescale e500 class */ \ | ||||
__PMC_CLASS(SOFT) /* Software events */ | __PMC_CLASS(SOFT) /* Software events */ | ||||
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The list is sorted differently. I was wondering if we want some "sparser" allocation scheme...