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	mov x2, #(PSR_F \| PSR_I \| PSR_A \| PSR_D \| PSR_M_EL1h)	mov x2, #(PSR_F \| PSR_I \| PSR_A \| PSR_D \| PSR_M_EL1h)
	msr spsr_el2, x2	msr spsr_el2, x2

		/* Configure GICv3 CPU interface */
		mrs x2, id_aa64pfr0_el1
		/* Extract GIC bits from the register */
		andrewUnsubmitted Done Inline Actions What is the GIC field? It's generally better to explain what is happening when writing asm so you still understand what is happening in 6 months time. andrew: What is the GIC field? It's generally better to explain what is happening when writing asm so…
		zbbAuthorUnsubmitted Done Inline Actions This is the explanation from the documentation ("GIC bits"). If you look at the following line you see more detailed description what field setting means what /* 0001 - SR CPU IF supported / I will make that line even more detailed in the next iteration.... zbb:* This is the explanation from the documentation ("GIC bits"). If you look at the following line…
		ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS
		/* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */
		cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT)
		b.ne 2f

		mrs x2, icc_sre_el2
		orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */
		msr icc_sre_el2, x2
		isb
		2:

	/* Set the address to return to our return address */	/* Set the address to return to our return address */
	msr elr_el2, x30	msr elr_el2, x30

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