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Differential D2474 Diff 5262 sys/dev/ixl/i40e_adminq_cmd.h

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sys/dev/ixl/i40e_adminq_cmd.h

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*/ */
#define I40E_FW_API_VERSION_MAJOR 0x0001 #define I40E_FW_API_VERSION_MAJOR 0x0001
#define I40E_FW_API_VERSION_MINOR 0x0002 #define I40E_FW_API_VERSION_MINOR 0x0004
struct i40e_aq_desc { struct i40e_aq_desc {
__le16 flags; __le16 flags;
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i40e_aqc_opc_list_func_capabilities = 0x000A, i40e_aqc_opc_list_func_capabilities = 0x000A,
i40e_aqc_opc_list_dev_capabilities = 0x000B, i40e_aqc_opc_list_dev_capabilities = 0x000B,
i40e_aqc_opc_set_cppm_configuration = 0x0103,
i40e_aqc_opc_set_arp_proxy_entry = 0x0104,
i40e_aqc_opc_set_ns_proxy_entry = 0x0105,
/* LAA */ /* LAA */
i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */
i40e_aqc_opc_mac_address_read = 0x0107, i40e_aqc_opc_mac_address_read = 0x0107,
i40e_aqc_opc_mac_address_write = 0x0108, i40e_aqc_opc_mac_address_write = 0x0108,
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/* Tunnel commands */ /* Tunnel commands */
i40e_aqc_opc_add_udp_tunnel = 0x0B00, i40e_aqc_opc_add_udp_tunnel = 0x0B00,
i40e_aqc_opc_del_udp_tunnel = 0x0B01, i40e_aqc_opc_del_udp_tunnel = 0x0B01,
i40e_aqc_opc_tunnel_key_structure = 0x0B10,
/* Async Events */ /* Async Events */
i40e_aqc_opc_event_lan_overflow = 0x1001, i40e_aqc_opc_event_lan_overflow = 0x1001,
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i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
/* debug commands */ /* debug commands */
i40e_aqc_opc_debug_get_deviceid = 0xFF00,
i40e_aqc_opc_debug_set_mode = 0xFF01,
i40e_aqc_opc_debug_read_reg = 0xFF03, i40e_aqc_opc_debug_read_reg = 0xFF03,
i40e_aqc_opc_debug_write_reg = 0xFF04, i40e_aqc_opc_debug_write_reg = 0xFF04,
i40e_aqc_opc_debug_modify_reg = 0xFF07, i40e_aqc_opc_debug_modify_reg = 0xFF07,
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#define I40E_AQC_SAN_ADDR_VALID 0x20 #define I40E_AQC_SAN_ADDR_VALID 0x20
#define I40E_AQC_PORT_ADDR_VALID 0x40 #define I40E_AQC_PORT_ADDR_VALID 0x40
#define I40E_AQC_WOL_ADDR_VALID 0x80 #define I40E_AQC_WOL_ADDR_VALID 0x80
#define I40E_AQC_ADDR_VALID_MASK 0xf0 #define I40E_AQC_MC_MAG_EN_VALID 0x100
#define I40E_AQC_ADDR_VALID_MASK 0x1F0
u8 reserved[6]; u8 reserved[6];
__le32 addr_high; __le32 addr_high;
__le32 addr_low; __le32 addr_low;
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#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
#define I40E_AQC_WRITE_TYPE_PORT 0x8000 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
#define I40E_AQC_WRITE_TYPE_MASK 0xc000 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
#define I40E_AQC_WRITE_TYPE_MASK 0xC000
__le16 mac_sah; __le16 mac_sah;
__le32 mac_sal; __le32 mac_sal;
u8 reserved[8]; u8 reserved[8];
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__le16 seid; __le16 seid;
#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
__le16 vlan_tag; __le16 vlan_tag;
#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
u8 reserved[8]; u8 reserved[8];
}; };
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#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
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#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
* word boundary layout issues, which the Linux compilers silently deal
* with by adding padding, making the actual struct larger than designed.
* However, the FW compiler for the NIC is less lenient and complains
* about the struct. Hence, the struct defined here has an extra byte in
* fields reserved3 and reserved4 to directly acknowledge that padding,
* and the new length is used in the length check macro.
*/
struct i40e_aqc_get_cee_dcb_cfg_v1_resp { struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
u8 reserved1; u8 reserved1;
u8 oper_num_tc; u8 oper_num_tc;
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u8 reserved2; u8 reserved2;
u8 oper_tc_bw[8]; u8 oper_tc_bw[8];
u8 oper_pfc_en; u8 oper_pfc_en;
u8 reserved3; u8 reserved3[2];
__le16 oper_app_prio; __le16 oper_app_prio;
u8 reserved4; u8 reserved4[2];
__le16 tlv_status; __le16 tlv_status;
}; };
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