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sys/dev/ixl/i40e_adminq.c
| Context not available. | |||||
| wr32(hw, hw->aq.asq.tail, 0); | wr32(hw, hw->aq.asq.tail, 0); | ||||
| /* set starting point */ | /* set starting point */ | ||||
| wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | | if (!i40e_is_vf(hw)) | ||||
| I40E_PF_ATQLEN_ATQENABLE_MASK)); | wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | | ||||
| I40E_PF_ATQLEN_ATQENABLE_MASK)); | |||||
| if (i40e_is_vf(hw)) | |||||
| wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | | |||||
| I40E_VF_ATQLEN1_ATQENABLE_MASK)); | |||||
| wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa)); | wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa)); | ||||
| wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa)); | wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa)); | ||||
| Context not available. | |||||
| wr32(hw, hw->aq.arq.tail, 0); | wr32(hw, hw->aq.arq.tail, 0); | ||||
| /* set starting point */ | /* set starting point */ | ||||
| wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | | if (!i40e_is_vf(hw)) | ||||
| I40E_PF_ARQLEN_ARQENABLE_MASK)); | wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | | ||||
| I40E_PF_ARQLEN_ARQENABLE_MASK)); | |||||
| if (i40e_is_vf(hw)) | |||||
| wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | | |||||
| I40E_VF_ARQLEN1_ARQENABLE_MASK)); | |||||
| wr32(hw, hw->aq.arq.bal, I40E_LO_DWORD(hw->aq.arq.desc_buf.pa)); | wr32(hw, hw->aq.arq.bal, I40E_LO_DWORD(hw->aq.arq.desc_buf.pa)); | ||||
| wr32(hw, hw->aq.arq.bah, I40E_HI_DWORD(hw->aq.arq.desc_buf.pa)); | wr32(hw, hw->aq.arq.bah, I40E_HI_DWORD(hw->aq.arq.desc_buf.pa)); | ||||
| Context not available. | |||||
| i40e_destroy_spinlock(&hw->aq.asq_spinlock); | i40e_destroy_spinlock(&hw->aq.asq_spinlock); | ||||
| i40e_destroy_spinlock(&hw->aq.arq_spinlock); | i40e_destroy_spinlock(&hw->aq.arq_spinlock); | ||||
| if (hw->nvm_buff.va) | |||||
| i40e_free_virt_mem(hw, &hw->nvm_buff); | |||||
| return ret_code; | return ret_code; | ||||
| } | } | ||||
| Context not available. | |||||
| details = I40E_ADMINQ_DETAILS(*asq, ntc); | details = I40E_ADMINQ_DETAILS(*asq, ntc); | ||||
| while (rd32(hw, hw->aq.asq.head) != ntc) { | while (rd32(hw, hw->aq.asq.head) != ntc) { | ||||
| i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | ||||
| "%s: ntc %d head %d.\n", __FUNCTION__, ntc, | "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); | ||||
| rd32(hw, hw->aq.asq.head)); | |||||
| if (details->callback) { | if (details->callback) { | ||||
| I40E_ADMINQ_CALLBACK cb_func = | I40E_ADMINQ_CALLBACK cb_func = | ||||
| Context not available. | |||||
| u16 retval = 0; | u16 retval = 0; | ||||
| u32 val = 0; | u32 val = 0; | ||||
| hw->aq.asq_last_status = I40E_AQ_RC_OK; | |||||
| val = rd32(hw, hw->aq.asq.head); | val = rd32(hw, hw->aq.asq.head); | ||||
| if (val >= hw->aq.num_asq_entries) { | if (val >= hw->aq.num_asq_entries) { | ||||
| i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | ||||
| Context not available. | |||||
| "AQTX: desc and buffer writeback:\n"); | "AQTX: desc and buffer writeback:\n"); | ||||
| i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size); | i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size); | ||||
| /* save writeback aq if requested */ | |||||
| if (details->wb_desc) | |||||
| i40e_memcpy(details->wb_desc, desc_on_ring, | |||||
| sizeof(struct i40e_aq_desc), I40E_DMA_TO_NONDMA); | |||||
| /* update the error if time out occurred */ | /* update the error if time out occurred */ | ||||
| if ((!cmd_completed) && | if ((!cmd_completed) && | ||||
| (!details->async && !details->postpone)) { | (!details->async && !details->postpone)) { | ||||
| Context not available. | |||||
| i40e_acquire_spinlock(&hw->aq.arq_spinlock); | i40e_acquire_spinlock(&hw->aq.arq_spinlock); | ||||
| /* set next_to_use to head */ | /* set next_to_use to head */ | ||||
| ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK); | if (!i40e_is_vf(hw)) | ||||
| ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK); | |||||
| if (i40e_is_vf(hw)) | |||||
| ntu = (rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK); | |||||
| if (ntu == ntc) { | if (ntu == ntc) { | ||||
| /* nothing to do - shouldn't need to update ring's values */ | /* nothing to do - shouldn't need to update ring's values */ | ||||
| ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK; | ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK; | ||||
| Context not available. | |||||
| i40e_release_nvm(hw); | i40e_release_nvm(hw); | ||||
| hw->aq.nvm_release_on_done = FALSE; | hw->aq.nvm_release_on_done = FALSE; | ||||
| } | } | ||||
| switch (hw->nvmupd_state) { | |||||
| case I40E_NVMUPD_STATE_INIT_WAIT: | |||||
| hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | |||||
| break; | |||||
| case I40E_NVMUPD_STATE_WRITE_WAIT: | |||||
| hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; | |||||
| break; | |||||
| default: | |||||
| break; | |||||
| } | |||||
| } | } | ||||
| return ret_code; | return ret_code; | ||||
| Context not available. | |||||
| hw->aq.asq.next_to_use = 0; | hw->aq.asq.next_to_use = 0; | ||||
| hw->aq.asq.next_to_clean = 0; | hw->aq.asq.next_to_clean = 0; | ||||
| #if (I40E_VF_ATQLEN_ATQENABLE_MASK != I40E_PF_ATQLEN_ATQENABLE_MASK) | |||||
| #error I40E_VF_ATQLEN_ATQENABLE_MASK != I40E_PF_ATQLEN_ATQENABLE_MASK | |||||
| #endif | |||||
| i40e_config_asq_regs(hw); | i40e_config_asq_regs(hw); | ||||
| hw->aq.arq.next_to_use = 0; | hw->aq.arq.next_to_use = 0; | ||||
| Context not available. | |||||