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sys/arm64/include/armreg.h
| Context not available. | |||||
| #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ | #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ | ||||
| #define EXCP_BRK 0x3c /* Breakpoint */ | #define EXCP_BRK 0x3c /* Breakpoint */ | ||||
| /* ICC_SRE_EL2 */ | |||||
| #define ICC_SRE_EL2_EN (1U << 3) | |||||
| /* ICC_SRE_EL1 */ | |||||
| #define ICC_SRE_EL1_SRE (1U << 0) | |||||
| /* ICC_CTLR_EL1 */ | |||||
| #define ICC_CTLR_EL1_EOI (1U << 1) | |||||
andrew: This should be `ICC_CTLR_EL1_EOIMODE` | |||||
| /* ICC_IGRPEN0_EL1 */ | |||||
| #define ICC_IGRPEN0_EL1_EN (1U << 0) | |||||
| /* ICC_IAR1_EL1 */ | |||||
| #define ICC_IAR1_EL1_SPUR (0x03ff) | |||||
andrewUnsubmitted Done Inline ActionsI don't see this in the ARMv8 ARM, is it documented differently in the GICv3 docs? andrew: I don't see this in the ARMv8 ARM, is it documented differently in the GICv3 docs? | |||||
zbbAuthorUnsubmitted Done Inline ActionsTo avoid another ping-pong: Do you ask because:
zbb: To avoid another ping-pong:
1023 is a spurious interrupt ID that is described in GICv3 docs and… | |||||
andrewUnsubmitted Done Inline ActionsOk, this is one of the problems with me not having GICv3 docs,I'm unsure what is in there that may be useful. andrew: Ok, this is one of the problems with me not having GICv3 docs,I'm unsure what is in there that… | |||||
andrewUnsubmitted Done Inline ActionsIn general I've tried to add all the used bits when adding new register values, and the registers should be alphabetically sorted by name. andrew: In general I've tried to add all the used bits when adding new register values, and the… | |||||
ianUnsubmitted Done Inline ActionsEeek! No way -- the registers should be sorted ascending by address, not by name, so that they match the way they're documented. (I've yet to see a soc manual arrange register docs alphabetical as opposed to by address.) ian: Eeek! No way -- the registers should be sorted ascending by address, not by name, so that they… | |||||
andrewUnsubmitted Done Inline ActionsThese are special registers, they are listed by name in the docs. There is sort of an address (as much of one as the 32-bit coprocessor registers), but only the assembler needs to know about it. andrew: These are special registers, they are listed by name in the docs. There is sort of an address… | |||||
| /* ID_AA64PFR0_EL1 */ | /* ID_AA64PFR0_EL1 */ | ||||
| #define ID_AA64PFR0_EL0_MASK (0xf << 0) | #define ID_AA64PFR0_EL0_MASK (0xf << 0) | ||||
| #define ID_AA64PFR0_EL1_MASK (0xf << 4) | #define ID_AA64PFR0_EL1_MASK (0xf << 4) | ||||
| Context not available. | |||||
This should be ICC_CTLR_EL1_EOIMODE