Differential D2250 Diff 4723 sys/amd64/amd64/mp_machdep.c

Changeset View

Standalone View

sys/amd64/amd64/mp_machdep.c

Show First 20 Lines • Show All 1,450 Lines • ▼ Show 20 Lines	cpustop_handler(void)
cpu = PCPU_GET(cpuid);		cpu = PCPU_GET(cpuid);

savectx(&stoppcbs[cpu]);		savectx(&stoppcbs[cpu]);

/* Indicate that we are stopped */		/* Indicate that we are stopped */
CPU_SET_ATOMIC(cpu, &stopped_cpus);		CPU_SET_ATOMIC(cpu, &stopped_cpus);

/* Wait for restart */		/* Wait for restart */
while (!CPU_ISSET(cpu, &started_cpus))		while (!CPU_ISSET(cpu, &started_cpus)) {
ia32_pause();		ia32_pause();

		/* If we paniced, just stop this CPU. */
		while (panicstr) {
		markjUnsubmitted Not Done Inline Actions Why is this a loop rather than an if statement? markj: Why is this a loop rather than an if statement?
		cse_cem_gmail_comAuthorUnsubmitted Not Done Inline Actions Same reason you see `for (;;) ;` at the end of reboot. In case it zomies back from the dead for whatever reason. cse_cem_gmail_com: Same reason you see `for (;;) ;` at the end of reboot. In case it zomies back from the dead for…
		disable_intr();
		markjUnsubmitted Not Done Inline Actions Is this actually needed? IPI_STOP_HARD is implemented by raising an NMI, so interrupts should already be disabled here. And IPI_STOP is handled through an interrupt gate, so interrupts will be disabled here in that case too. markj: Is this actually needed? IPI_STOP_HARD is implemented by raising an NMI, so interrupts should…
		cse_cem_gmail_comAuthorUnsubmitted Not Done Inline Actions It sounds like it's not needed. I didn't spot the logic that disables interrupts — where is it? Thanks. cse_cem_gmail_com: It sounds like it's not needed. I didn't spot the logic that disables interrupts — where is it?
		kibUnsubmitted Not Done Inline Actions The NMI IDT entry is set as the interrupt gate in the hammer_time(). The type of gate makes the CPU implicitly disable maskable interrupts on entry. NMI itself is implicitly disabled by the internal latch upon NMI deliver; the latch i cleared only by iretq. kib: The NMI IDT entry is set as the interrupt gate in the hammer_time(). The type of gate makes…
		cse_cem_gmail_comAuthorUnsubmitted Not Done Inline Actions Thanks. cse_cem_gmail_com: Thanks.
		halt();
		}
		}

CPU_CLR_ATOMIC(cpu, &started_cpus);		CPU_CLR_ATOMIC(cpu, &started_cpus);
CPU_CLR_ATOMIC(cpu, &stopped_cpus);		CPU_CLR_ATOMIC(cpu, &stopped_cpus);

#ifdef DDB		#ifdef DDB
amd64_db_resume_dbreg();		amd64_db_resume_dbreg();
#endif		#endif

▲ Show 20 Lines • Show All 272 Lines • Show Last 20 Lines