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Show First 20 Lines • Show All 1,948 Lines • ▼ Show 20 Lines	em_if_msix_intr_assign(if_ctx_t ctx, int msix)
}		}
rx_vectors = vector;		rx_vectors = vector;

vector = 0;		vector = 0;
for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {		for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
rid = vector + 1;		rid = vector + 1;
snprintf(buf, sizeof(buf), "txq%d", i);		snprintf(buf, sizeof(buf), "txq%d", i);
tx_que = &adapter->tx_queues[i];		tx_que = &adapter->tx_queues[i];
iflib_softirq_alloc_generic(ctx, rid, IFLIB_INTR_TX, tx_que, tx_que->me, buf);		iflib_softirq_alloc_generic(ctx,
		&adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
		IFLIB_INTR_TX, tx_que, tx_que->me, buf);

tx_que->msix = (vector % adapter->tx_num_queues);		tx_que->msix = (vector % adapter->tx_num_queues);

/*		/*
* Set the bit to enable interrupt		* Set the bit to enable interrupt
* in E1000_IMS -- bits 22 and 23		* in E1000_IMS -- bits 22 and 23
* are for TX0 and TX1, note this has		* are for TX0 and TX1, note this has
* NOTHING to do with the MSIX vector		* NOTHING to do with the MSIX vector
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