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Differential D1892 Diff 4110 sys/x86/iommu/intel_utils.c

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sys/x86/iommu/intel_utils.c

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#include <sys/rman.h> #include <sys/rman.h>
#include <sys/rwlock.h> #include <sys/rwlock.h>
#include <sys/sched.h> #include <sys/sched.h>
#include <sys/sf_buf.h> #include <sys/sf_buf.h>
#include <sys/sysctl.h> #include <sys/sysctl.h>
#include <sys/systm.h> #include <sys/systm.h>
#include <sys/taskqueue.h> #include <sys/taskqueue.h>
#include <sys/tree.h> #include <sys/tree.h>
#include <sys/vmem.h>
#include <dev/pci/pcivar.h> #include <dev/pci/pcivar.h>
#include <vm/vm.h> #include <vm/vm.h>
#include <vm/vm_extern.h> #include <vm/vm_extern.h>
#include <vm/vm_kern.h> #include <vm/vm_kern.h>
#include <vm/vm_object.h> #include <vm/vm_object.h>
#include <vm/vm_page.h> #include <vm/vm_page.h>
#include <vm/vm_map.h> #include <vm/vm_map.h>
#include <vm/vm_pageout.h> #include <vm/vm_pageout.h>
#include <machine/bus.h> #include <machine/bus.h>
#include <machine/cpu.h> #include <machine/cpu.h>
#include <machine/intr_machdep.h>
#include <x86/include/apicvar.h>
#include <x86/include/busdma_impl.h> #include <x86/include/busdma_impl.h>
#include <x86/iommu/intel_reg.h> #include <x86/iommu/intel_reg.h>
#include <x86/iommu/busdma_dmar.h> #include <x86/iommu/busdma_dmar.h>
#include <x86/iommu/intel_dmar.h> #include <x86/iommu/intel_dmar.h>
u_int u_int
dmar_nd2mask(u_int nd) dmar_nd2mask(u_int nd)
{ {
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dmar_disable_translation(struct dmar_unit *unit) dmar_disable_translation(struct dmar_unit *unit)
{ {
DMAR_ASSERT_LOCKED(unit); DMAR_ASSERT_LOCKED(unit);
unit->hw_gcmd &= ~DMAR_GCMD_TE; unit->hw_gcmd &= ~DMAR_GCMD_TE;
dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
/* XXXKIB should have a timeout */ /* XXXKIB should have a timeout */
while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) != 0) while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) != 0)
cpu_spinwait();
return (0);
}
int
dmar_load_irt_ptr(struct dmar_unit *unit)
{
uint64_t irta, s;
DMAR_ASSERT_LOCKED(unit);
irta = unit->irt_phys;
if (DMAR_X2APIC(unit))
irta |= DMAR_IRTA_EIME;
s = fls(unit->irte_cnt) - 2;
KASSERT(unit->irte_cnt >= 2 && s <= DMAR_IRTA_S_MASK &&
powerof2(unit->irte_cnt),
("IRTA_REG_S overflow %x", unit->irte_cnt));
irta |= s;
dmar_write8(unit, DMAR_IRTA_REG, irta);
dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SIRTP);
/* XXXKIB should have a timeout */
while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRTPS) == 0)
cpu_spinwait();
return (0);
}
int
dmar_enable_ir(struct dmar_unit *unit)
{
DMAR_ASSERT_LOCKED(unit);
unit->hw_gcmd |= DMAR_GCMD_IRE;
unit->hw_gcmd &= ~DMAR_GCMD_CFI;
dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
/* XXXKIB should have a timeout */
while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) == 0)
cpu_spinwait();
return (0);
}
int
dmar_disable_ir(struct dmar_unit *unit)
{
DMAR_ASSERT_LOCKED(unit);
unit->hw_gcmd &= ~DMAR_GCMD_IRE;
dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
/* XXXKIB should have a timeout */
while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) != 0)
cpu_spinwait(); cpu_spinwait();
return (0); return (0);
} }
#define BARRIER_F \ #define BARRIER_F \
u_int f_done, f_inproc, f_wakeup; \ u_int f_done, f_inproc, f_wakeup; \
\ \
f_done = 1 << (barrier_id * 3); \ f_done = 1 << (barrier_id * 3); \
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