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sys/x86/iommu/intel_reg.h
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/* Destination Id */ | /* Destination Id */ | ||||
#define DMAR_IRTE1_DST_xAPIC(x) (((uint64_t)(x)) << 40) | #define DMAR_IRTE1_DST_xAPIC(x) (((uint64_t)(x)) << 40) | ||||
#define DMAR_IRTE1_DST_x2APIC(x) (((uint64_t)(x)) << 32) | #define DMAR_IRTE1_DST_x2APIC(x) (((uint64_t)(x)) << 32) | ||||
/* Vector */ | /* Vector */ | ||||
#define DMAR_IRTE1_V(x) (((uint64_t)x) << 16) | #define DMAR_IRTE1_V(x) (((uint64_t)x) << 16) | ||||
#define DMAR_IRTE1_IM_POSTED (1ULL << 15) /* Posted */ | #define DMAR_IRTE1_IM_POSTED (1ULL << 15) /* Posted */ | ||||
/* Delivery Mode */ | /* Delivery Mode */ | ||||
#define DMAR_IRTE1_DLM_FM (0ULL << 5) | #define DMAR_IRTE1_DLM_FM (0ULL << 5) | ||||
#define DMAR_IRTE1_DLM_LP (1ULL << 5 | #define DMAR_IRTE1_DLM_LP (1ULL << 5 | ||||
neel: Typo: missing the closing ")" | |||||
#define DMAR_IRTE1_DLM_SMI (2ULL << 5) | #define DMAR_IRTE1_DLM_SMI (2ULL << 5) | ||||
#define DMAR_IRTE1_DLM_NMI (4ULL << 5) | #define DMAR_IRTE1_DLM_NMI (4ULL << 5) | ||||
#define DMAR_IRTE1_DLM_INIT (5ULL << 5) | #define DMAR_IRTE1_DLM_INIT (5ULL << 5) | ||||
#define DMAR_IRTE1_DLM_ExtINT (7ULL << 5) | #define DMAR_IRTE1_DLM_ExtINT (7ULL << 5) | ||||
/* Trigger Mode */ | /* Trigger Mode */ | ||||
#define DMAR_IRTE1_TM_EDGE (0ULL << 4) | #define DMAR_IRTE1_TM_EDGE (0ULL << 4) | ||||
#define DMAR_IRTE1_TM_LEVEL (1ULL << 4) | #define DMAR_IRTE1_TM_LEVEL (1ULL << 4) | ||||
/* Redirection Hint */ | /* Redirection Hint */ | ||||
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#define DMAR_ECAP_MTS (1ULL << 25) /* Memory Type */ | #define DMAR_ECAP_MTS (1ULL << 25) /* Memory Type */ | ||||
#define DMAR_ECAP_ECS (1ULL << 24) /* Extended Context */ | #define DMAR_ECAP_ECS (1ULL << 24) /* Extended Context */ | ||||
#define DMAR_ECAP_MHMV(x) ((u_int)(((x) >> 20) & 0xf)) | #define DMAR_ECAP_MHMV(x) ((u_int)(((x) >> 20) & 0xf)) | ||||
/* Maximum Handle Mask Value */ | /* Maximum Handle Mask Value */ | ||||
#define DMAR_ECAP_IRO(x) ((u_int)(((x) >> 8) & 0x3ff)) | #define DMAR_ECAP_IRO(x) ((u_int)(((x) >> 8) & 0x3ff)) | ||||
/* IOTLB Register Offset */ | /* IOTLB Register Offset */ | ||||
#define DMAR_ECAP_SC (1 << 7) /* Snoop Control */ | #define DMAR_ECAP_SC (1 << 7) /* Snoop Control */ | ||||
#define DMAR_ECAP_PT (1 << 6) /* Pass Through */ | #define DMAR_ECAP_PT (1 << 6) /* Pass Through */ | ||||
#define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode */ | #define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode (x2APIC) */ | ||||
#define DMAR_ECAP_IR (1 << 3) /* Interrupt Remapping */ | #define DMAR_ECAP_IR (1 << 3) /* Interrupt Remapping */ | ||||
#define DMAR_ECAP_DI (1 << 2) /* Device IOTLB */ | #define DMAR_ECAP_DI (1 << 2) /* Device IOTLB */ | ||||
#define DMAR_ECAP_QI (1 << 1) /* Queued Invalidation */ | #define DMAR_ECAP_QI (1 << 1) /* Queued Invalidation */ | ||||
#define DMAR_ECAP_C (1 << 0) /* Coherency */ | #define DMAR_ECAP_C (1 << 0) /* Coherency */ | ||||
/* Global Command register */ | /* Global Command register */ | ||||
#define DMAR_GCMD_REG 0x18 | #define DMAR_GCMD_REG 0x18 | ||||
#define DMAR_GCMD_TE (1U << 31) /* Translation Enable */ | #define DMAR_GCMD_TE (1U << 31) /* Translation Enable */ | ||||
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#define DMAR_PHMLIMIT_REG 0x78 | #define DMAR_PHMLIMIT_REG 0x78 | ||||
/* Queued Invalidation Descriptors */ | /* Queued Invalidation Descriptors */ | ||||
#define DMAR_IQ_DESCR_SZ_SHIFT 4 /* Shift for descriptor count | #define DMAR_IQ_DESCR_SZ_SHIFT 4 /* Shift for descriptor count | ||||
to ring offset */ | to ring offset */ | ||||
#define DMAR_IQ_DESCR_SZ (1 << DMAR_IQ_DESCR_SZ_SHIFT) | #define DMAR_IQ_DESCR_SZ (1 << DMAR_IQ_DESCR_SZ_SHIFT) | ||||
/* Descriptor size */ | /* Descriptor size */ | ||||
#define DMAR_IQ_DESCR_CTX_INV 0x1 /* Context-cache Invalidate | /* Context-cache Invalidate Descriptor */ | ||||
Descriptor */ | #define DMAR_IQ_DESCR_CTX_INV 0x1 | ||||
#define DMAR_IQ_DESCR_CTX_GLOB (0x1 << 4) /* Granularity: Global */ | #define DMAR_IQ_DESCR_CTX_GLOB (0x1 << 4) /* Granularity: Global */ | ||||
#define DMAR_IQ_DESCR_CTX_DOM (0x2 << 4) /* Granularity: Domain */ | #define DMAR_IQ_DESCR_CTX_DOM (0x2 << 4) /* Granularity: Domain */ | ||||
#define DMAR_IQ_DESCR_CTX_DEV (0x3 << 4) /* Granularity: Device */ | #define DMAR_IQ_DESCR_CTX_DEV (0x3 << 4) /* Granularity: Device */ | ||||
#define DMAR_IQ_DESCR_CTX_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ | #define DMAR_IQ_DESCR_CTX_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ | ||||
#define DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */ | #define DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */ | ||||
#define DMAR_IQ_DESCR_CTX_FM(x) (((uint64_t)(x)) << 48) /* Function Mask */ | #define DMAR_IQ_DESCR_CTX_FM(x) (((uint64_t)(x)) << 48) /* Function Mask */ | ||||
#define DMAR_IQ_DESCR_IOTLB_INV 0x2 /* IOTLB Invalidate Descriptor */ | /* IOTLB Invalidate Descriptor */ | ||||
#define DMAR_IQ_DESCR_IOTLB_INV 0x2 | |||||
#define DMAR_IQ_DESCR_IOTLB_GLOB (0x1 << 4) /* Granularity: Global */ | #define DMAR_IQ_DESCR_IOTLB_GLOB (0x1 << 4) /* Granularity: Global */ | ||||
#define DMAR_IQ_DESCR_IOTLB_DOM (0x2 << 4) /* Granularity: Domain */ | #define DMAR_IQ_DESCR_IOTLB_DOM (0x2 << 4) /* Granularity: Domain */ | ||||
#define DMAR_IQ_DESCR_IOTLB_PAGE (0x3 << 4) /* Granularity: Page */ | #define DMAR_IQ_DESCR_IOTLB_PAGE (0x3 << 4) /* Granularity: Page */ | ||||
#define DMAR_IQ_DESCR_IOTLB_DW (1 << 6) /* Drain Writes */ | #define DMAR_IQ_DESCR_IOTLB_DW (1 << 6) /* Drain Writes */ | ||||
#define DMAR_IQ_DESCR_IOTLB_DR (1 << 7) /* Drain Reads */ | #define DMAR_IQ_DESCR_IOTLB_DR (1 << 7) /* Drain Reads */ | ||||
#define DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ | #define DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ | ||||
#define DMAR_IQ_DESCR_IEC_INV 0x4 /* Invalidate Interrupt Entry Cache */ | /* Device-TLB Invalidate Descriptor */ | ||||
#define DMAR_IQ_DESCR_DTLB_INV 0x3 | |||||
/* Invalidate Interrupt Entry Cache */ | |||||
#define DMAR_IQ_DESCR_IEC_INV 0x4 | |||||
#define DMAR_IQ_DESCR_IEC_IDX (1 << 4) /* Index-Selective Invalidation */ | #define DMAR_IQ_DESCR_IEC_IDX (1 << 4) /* Index-Selective Invalidation */ | ||||
#define DMAR_IQ_DESCR_IEC_IIDX(x) (((uint64_t)x) << 32) /* Interrupt Index */ | #define DMAR_IQ_DESCR_IEC_IIDX(x) (((uint64_t)x) << 32) /* Interrupt Index */ | ||||
#define DMAR_IQ_DESCR_IEC_IM(x) ((x) << 27) /* Index Mask */ | #define DMAR_IQ_DESCR_IEC_IM(x) ((x) << 27) /* Index Mask */ | ||||
#define DMAR_IQ_DESCR_WAIT_ID 0x5 /* Invalidation Wait Descriptor */ | /* Invalidation Wait Descriptor */ | ||||
#define DMAR_IQ_DESCR_WAIT_ID 0x5 | |||||
#define DMAR_IQ_DESCR_WAIT_IF (1 << 4) /* Interrupt Flag */ | #define DMAR_IQ_DESCR_WAIT_IF (1 << 4) /* Interrupt Flag */ | ||||
#define DMAR_IQ_DESCR_WAIT_SW (1 << 5) /* Status Write */ | #define DMAR_IQ_DESCR_WAIT_SW (1 << 5) /* Status Write */ | ||||
#define DMAR_IQ_DESCR_WAIT_FN (1 << 6) /* Fence */ | #define DMAR_IQ_DESCR_WAIT_FN (1 << 6) /* Fence */ | ||||
#define DMAR_IQ_DESCR_WAIT_SD(x) (((uint64_t)(x)) << 32) /* Status Data */ | #define DMAR_IQ_DESCR_WAIT_SD(x) (((uint64_t)(x)) << 32) /* Status Data */ | ||||
/* Extended IOTLB Invalidate Descriptor */ | |||||
#define DMAR_IQ_DESCR_EIOTLB_INV 0x6 | |||||
/* PASID-Cache Invalidate Descriptor */ | |||||
#define DMAR_IQ_DESCR_PASIDC_INV 0x7 | |||||
/* Extended Device-TLB Invalidate Descriptor */ | |||||
#define DMAR_IQ_DESCR_EDTLB_INV 0x8 | |||||
/* Invalidation Queue Head register */ | /* Invalidation Queue Head register */ | ||||
#define DMAR_IQH_REG 0x80 | #define DMAR_IQH_REG 0x80 | ||||
#define DMAR_IQH_MASK 0x7fff0 /* Next cmd index mask */ | #define DMAR_IQH_MASK 0x7fff0 /* Next cmd index mask */ | ||||
/* Invalidation Queue Tail register */ | /* Invalidation Queue Tail register */ | ||||
#define DMAR_IQT_REG 0x88 | #define DMAR_IQT_REG 0x88 | ||||
#define DMAR_IQT_MASK 0x7fff0 | #define DMAR_IQT_MASK 0x7fff0 | ||||
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