Differential D12203 Diff 32582 sys/dev/bnxt/hsi_struct_def.h

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sys/dev/bnxt/hsi_struct_def.h

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Context not available.
	*	*
	* Description: Definition of HSI data structures	* Description: Definition of HSI data structures
	*	*
	* Date: 07/26/16 21:30:37	* Date: 08/30/17 14:39:29
	*	*
	* Note: This file is scripted generated by hsi_decode.py.	* Note: This file is scripted generated by hsi_decode.py.
	* DO NOT modify this file manually !!!!	* DO NOT modify this file manually !!!!
Context not available.
	****************************************************************************/	****************************************************************************/
	#ifndef _HSI_STRUCT_DEF_EXTERNAL_H_	#ifndef _HSI_STRUCT_DEF_EXTERNAL_H_
	#define _HSI_STRUCT_DEF_EXTERNAL_H_	#define _HSI_STRUCT_DEF_EXTERNAL_H_
		/* HSI and HWRM Specification 1.8.1 */
		#define HWRM_VERSION_MAJOR 1
		#define HWRM_VERSION_MINOR 8
		#define HWRM_VERSION_UPDATE 1

		#define HWRM_VERSION_RSVD 5 /* non-zero means beta version */
		shurdUnsubmitted Done Inline Actions So this is for a beta version? shurd: So this is for a beta version?
		bhargava.marreddy_broadcom.comAuthorUnsubmitted Not Done Inline Actions Based on the discussion with firmware team, non-zero HWRM_VERSION_RSVD is acceptable for external releases. I deleted that comment. bhargava.marreddy_broadcom.com: Based on the discussion with firmware team, non-zero HWRM_VERSION_RSVD is acceptable for…

		#define HWRM_VERSION_STR "1.8.1.5"
	/*	/*
	* per-context HW statistics -- chip view	* Following is the signature for HWRM message field that indicates not
	* Reference to stat_ctx_stat_xxx for	* applicable (All F's). Need to cast it the size of the field if needed.
	*/	*/
		#define HWRM_NA_SIGNATURE ((uint32_t)(-1))
		#define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
		#define HWRM_MAX_RESP_LEN (248) /* hwrm_selftest_qlist */
		#define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
		#define HW_HASH_KEY_SIZE 40
		#define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
		#define ROCE_SP_HSI_VERSION_MAJOR 1
		#define ROCE_SP_HSI_VERSION_MINOR 8
		#define ROCE_SP_HSI_VERSION_UPDATE 1

	struct ctx_hw_stats {	#define ROCE_SP_HSI_VERSION_STR "1.8.1"
	uint64_t rx_ucast_pkts;	/*
	uint64_t rx_mcast_pkts;	* Following is the signature for ROCE_SP_HSI message field that indicates not
	uint64_t rx_bcast_pkts;	* applicable (All F's). Need to cast it the size of the field if needed.
	uint64_t rx_discard_pkts;	*/
	uint64_t rx_drop_pkts;	#define ROCE_SP_HSI_NA_SIGNATURE ((uint32_t)(-1))
	uint64_t rx_ucast_bytes;	/*
	uint64_t rx_mcast_bytes;	* Note: The Host Software Interface (HSI) and Hardware Resource Manager (HWRM)
	uint64_t rx_bcast_bytes;	* specification describes the data structures used in Ethernet packet or RDMA
	uint64_t tx_ucast_pkts;	* message data transfers as well as an abstract interface for managing Ethernet
	uint64_t tx_mcast_pkts;	* NIC hardware resources.
	uint64_t tx_bcast_pkts;	*/
	uint64_t tx_discard_pkts;	/* Ethernet Data path Host Structures */
	uint64_t tx_drop_pkts;	/*
	uint64_t tx_ucast_bytes;	* Description: The following three sections document the host structures used
	uint64_t tx_mcast_bytes;	* between device and software drivers for communicating Ethernet packets.
	uint64_t tx_bcast_bytes;	*/
	uint64_t tpa_pkts;
	uint64_t tpa_bytes;
	uint64_t tpa_events;
	uint64_t tpa_aborts;
	} __attribute__((packed));

	/* BD Ring Structures */	/* BD Ring Structures */
	/*	/*
	* Description: This structure is used to inform the NIC of a location for and	* Description: This structure is used to inform the NIC of a location for and
Context not available.
	/* This bit is '1' if the RSS field in this completion is valid. */	/* This bit is '1' if the RSS field in this completion is valid. */
	#define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)	#define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
	/* unused is 1 b */	/* unused is 1 b */
		#define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
	/*	/*
	* This value indicates what the inner packet determined for the packet	* This value indicates what the inner packet determined for the packet
	* was.	* was.
Context not available.
	uint8_t rss_hash_type;	uint8_t rss_hash_type;
	/*	/*
	* This is the RSS hash type for the packet. The value is packed	* This is the RSS hash type for the packet. The value is packed
	* {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.	* {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. The
		* value of tuple_extrac_op provides the information about what fields
		* the hash was computed on. * 0: The RSS hash was computed over source
		* IP address, destination IP address, source port, and destination port
		* of inner IP and TCP or UDP headers. Note: For non-tunneled packets,
		* the packet headers are considered inner packet headers for the RSS
		* hash computation purpose. * 1: The RSS hash was computed over source
		* IP address and destination IP address of inner IP header. Note: For
		* non-tunneled packets, the packet headers are considered inner packet
		* headers for the RSS hash computation purpose. * 2: The RSS hash was
		* computed over source IP address, destination IP address, source port,
		* and destination port of IP and TCP or UDP headers of outer tunnel
		* headers. Note: For non-tunneled packets, this value is not
		* applicable. * 3: The RSS hash was computed over source IP address and
		* destination IP address of IP header of outer tunnel headers. Note:
		* For non-tunneled packets, this value is not applicable. Note that
		* 4-tuples values listed above are applicable for layer 4 protocols
		* supported and enabled for RSS in the hardware, HWRM firmware, and
		* drivers. For example, if RSS hash is supported and enabled for TCP
		* traffic only, then the values of tuple_extract_op corresponding to
		* 4-tuples are only valid for TCP traffic.
	*/	*/
	uint8_t payload_offset;	uint8_t payload_offset;
	/*	/*
Context not available.
	/* This bit is '1' if the RSS field in this completion is valid. */	/* This bit is '1' if the RSS field in this completion is valid. */
	#define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)	#define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
	/* unused is 1 b */	/* unused is 1 b */
		#define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
	/*	/*
	* This value indicates what the inner packet determined for the packet	* This value indicates what the inner packet determined for the packet
	* was.	* was.
Context not available.
	uint8_t rss_hash_type;	uint8_t rss_hash_type;
	/*	/*
	* This is the RSS hash type for the packet. The value is packed	* This is the RSS hash type for the packet. The value is packed
	* {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.	* {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. The
		* value of tuple_extrac_op provides the information about what fields
		* the hash was computed on. * 0: The RSS hash was computed over source
		* IP address, destination IP address, source port, and destination port
		* of inner IP and TCP or UDP headers. Note: For non-tunneled packets,
		* the packet headers are considered inner packet headers for the RSS
		* hash computation purpose. * 1: The RSS hash was computed over source
		* IP address and destination IP address of inner IP header. Note: For
		* non-tunneled packets, the packet headers are considered inner packet
		* headers for the RSS hash computation purpose. * 2: The RSS hash was
		* computed over source IP address, destination IP address, source port,
		* and destination port of IP and TCP or UDP headers of outer tunnel
		* headers. Note: For non-tunneled packets, this value is not
		* applicable. * 3: The RSS hash was computed over source IP address and
		* destination IP address of IP header of outer tunnel headers. Note:
		* For non-tunneled packets, this value is not applicable. Note that
		* 4-tuples values listed above are applicable for layer 4 protocols
		* supported and enabled for RSS in the hardware, HWRM firmware, and
		* drivers. For example, if RSS hash is supported and enabled for TCP
		* traffic only, then the values of tuple_extract_op corresponding to
		* 4-tuples are only valid for TCP traffic.
	*/	*/
	uint16_t agg_id;	uint16_t agg_id;
	/*	/*
Context not available.
	#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)	#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
	#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS	#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
	/* unused is 2 b */	/* unused is 2 b */
		#define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
		#define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
	/*	/*
	* This value indicates what the inner packet determined for the packet	* This value indicates what the inner packet determined for the packet
	* was. - 2 TCP Packet Indicates that the packet was IP and TCP. This	* was. - 2 TCP Packet Indicates that the packet was IP and TCP. This
Context not available.
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3)	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3)
	uint32_t event_data2;	uint32_t event_data2;
	/* Event specific data */	/* Event specific data */
		/* ETS configuration change */
		#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS UINT32_C(0x1)
		/* PFC configuration change */
		#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC UINT32_C(0x2)
		/* APP configuration change */
		#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP UINT32_C(0x4)
	uint8_t opaque_v;	uint8_t opaque_v;
	/* opaque is 7 b */	/* opaque is 7 b */
	/*	/*
Context not available.
	/* PORT ID */	/* PORT ID */
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
		/* Priority recommended for RoCE traffic */
		#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK UINT32_C(0xff0000)
		#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16
		/* none is 255 */
		#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (UINT32_C(0xff) << 16)
		#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
		/* Priority recommended for L2 traffic */
		#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK UINT32_C(0xff000000)
		#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24
		/* none is 255 */
		#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (UINT32_C(0xff) << 24)
		#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
	} __attribute__((packed));	} __attribute__((packed));

	/* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */	/* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */
Context not available.
	*/	*/
	} __attribute__((packed));	} __attribute__((packed));

	/* HW Resource Manager Specification 1.4.0 */	/* Doorbell Structures */
	#define HWRM_VERSION_MAJOR 1
	#define HWRM_VERSION_MINOR 4
	#define HWRM_VERSION_UPDATE 0

	#define HWRM_VERSION_STR "1.4.0"
	/*	/*
	* Following is the signature for HWRM message field that indicates not	* Description: This is the RoCE 32b Doorbell format. The host writes this
	* applicable (All F's). Need to cast it the size of the field if needed.	* message format directly to byte offset 8 of the appropriate doorbell page.
	*/	*/
	#define HWRM_NA_SIGNATURE ((uint32_t)(-1))	/* 64b Doorbell Format (8 bytes) */
	#define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
	#define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */	struct dbr_dbr {
	#define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */	uint32_t index;
	#define HW_HASH_KEY_SIZE 40	/*
	#define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */	* This value is the index being written. For SQ, RQ, SRQ, this is the
		* producer index and should be the queue index of the last WQE written
		* plus 1. For CQ, this is the consumer index and should be the index of
		* the last CQE processed plus 1.
		*/
		#define DBR_DBR_INDEX_MASK UINT32_C(0xfffff)
		#define DBR_DBR_INDEX_SFT 0
		#define DBR_DBR_RESERVED12_MASK UINT32_C(0xfff00000)
		#define DBR_DBR_RESERVED12_SFT 20
		uint32_t type_xid;
		/* This value identifies the type of doorbell being written. */
		/*
		* This value identifies the resource that the doorbell is intended to
		* notify. For SQ and RQ, this is the QPID. For SRQ, this is the SID.
		* For CQ, this is the CID. Bits [19:16] of this values must be zero for
		* a SID value.
		*/
		#define DBR_DBR_XID_MASK UINT32_C(0xfffff)
		#define DBR_DBR_XID_SFT 0
		#define DBR_DBR_RESERVED8_MASK UINT32_C(0xff00000)
		#define DBR_DBR_RESERVED8_SFT 20
		/* This value identifies the type of doorbell being written. */
		#define DBR_DBR_TYPE_MASK UINT32_C(0xf0000000)
		#define DBR_DBR_TYPE_SFT 28
		/*
		* This is a SQ producer index update. It indicates one or more
		* new entries have been written to the SQ for the QPID
		* indicated on the xID field.
		*/
		#define DBR_DBR_TYPE_SQ (UINT32_C(0x0) << 28)
		/*
		* This is a RQ producer index update. It indicates one or more
		* new entries have been written to the RQ for the QPID
		* indicated on the xID field.
		*/
		#define DBR_DBR_TYPE_RQ (UINT32_C(0x1) << 28)
		/*
		* This is a SRQ producer index update. It indicates one or more
		* new entries have been written to the SRQ for the SID
		* indicated on the xID field.
		*/
		#define DBR_DBR_TYPE_SRQ (UINT32_C(0x2) << 28)
		/*
		* This doorbell command arms the SRQ async event. The xID field
		* must identify the SID that is begin armed. The index field is
		* will set the arm threshold such that a notification will be
		* generated if less than that number or SRQ entries are posted.
		*/
		#define DBR_DBR_TYPE_SRQ_ARM (UINT32_C(0x3) << 28)
		/*
		* This is a CQ consumer index update. It indicates one or more
		* entries have been processed off the CQ indicated on the xID
		* field.
		*/
		#define DBR_DBR_TYPE_CQ (UINT32_C(0x4) << 28)
		/*
		* this is a CQ consumer index update that also arms the CQ for
		* solicited events.
		*/
		#define DBR_DBR_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28)
		/*
		* This is a CQ consumer index update that also arms the CQ for
		* any new CQE.
		*/
		#define DBR_DBR_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28)
		/*
		* This is a CQ arm enable message. This message must be sent
		* from the privileged driver before a new CQ_ARMSE or CQ_ARMALL
		* message will be accepted. This doorbell can only be sent from
		* the privileged (first) doorbell page of a function.
		*/
		#define DBR_DBR_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28)
		/*
		* This doorbell command enables the SRQ async event to be
		* armed. This message must be setn from the privileged driver
		* before a new SRQ_ARM message will be accepted. The xID field
		* must identify the SID that is begin enabled for arm. This
		* doorbell can only be sent from the privileged (first)
		* doorbell page of a function.
		*/
		#define DBR_DBR_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28)
		/*
		* This doorbell command indicates that the cutoff CQE has been
		* processed and the driver is now processing completions from
		* the new CQ. The index field for this doorbell type must be
		* zero.
		*/
		#define DBR_DBR_TYPE_CQ_CUTOFF_ACK (UINT32_C(0x9) << 28)
		/*
		* This doorbell command is used during doorbell moderation to
		* consume system BW and help prevent doorbell FIFO overflow.
		* All other fields should be zero for NULL doorbell.
		*/
		#define DBR_DBR_TYPE_NULL (UINT32_C(0xf) << 28)
		} __attribute__((packed));

		/* 32b Doorbell Format (4 bytes) */

		struct dbr_dbr32 {
		uint32_t type_abs_incr_xid;
		/* This value identifies the type of doorbell being written. */
		/*
		* This value identifies the resource that the doorbell is intended to
		* notify. For SQ and RQ, this is the QPID. For SRQ, this is the SID.
		* For CQ, this is the CID. Bits [19:16] of this values must be zero for
		* a SID value.
		*/
		#define DBR_DBR32_XID_MASK UINT32_C(0xfffff)
		#define DBR_DBR32_XID_SFT 0
		#define DBR_DBR32_RESERVED4_MASK UINT32_C(0xf00000)
		#define DBR_DBR32_RESERVED4_SFT 20
		/*
		* When abs=0, this value is the value to add to the appropriate index
		* value. When abs=1, this value is the new value for the index.
		* Absolute value is used when the queue is being wrapped. When abs=1,
		* the incr value follows the same rules as the index value in the 64b
		* doorbell.
		*/
		#define DBR_DBR32_INCR_MASK UINT32_C(0xf000000)
		#define DBR_DBR32_INCR_SFT 24
		/* This value defines how the incr value will be interpreted. */
		#define DBR_DBR32_ABS UINT32_C(0x10000000)
		/* This value identifies the type of doorbell being written. */
		#define DBR_DBR32_TYPE_MASK UINT32_C(0xe0000000)
		#define DBR_DBR32_TYPE_SFT 29
		/*
		* This is a SQ producer index update. It indicates one or more
		* new entries have been written to the SQ for the QPID
		* indicated on the xID field.
		*/
		#define DBR_DBR32_TYPE_SQ (UINT32_C(0x0) << 29)
		} __attribute__((packed));

		/* SQ WQE Structures */
	/*	/*
	* Description: Port Rx Statistics Formats. The HWRM shall return any	* Description: This is the Bind WQE structure. This WQE can perform either: *
	* unsupported counter with a value of 0xFFFFFFFF for 32-bit counters and	* type1 "bind memory window", if mw_type==Type1 * type2 "post send bind memory
	* 0xFFFFFFFFFFFFFFFF for 64-bit counters.	* window", if mw_type==Type2
	*/	*/
	/*	/* Base SQ WQE (8 bytes) */
	* Note: The Hardware Resource Manager (HWRM) manages various hardware resources
	* inside the chip. The HWRM is implemented in firmware, and runs on embedded
	* processors inside the chip. This firmware service is vital part of the chip.
	* The chip can not be used by a driver or HWRM client without the HWRM.
	*/
	/* Input (16 bytes) */

	struct input {	struct sq_base {
	uint16_t req_type;	uint8_t wqe_type;
		/* This field defines the type of SQ WQE. */
		/* Send */
		#define SQ_BASE_WQE_TYPE_SEND UINT32_C(0x0)
	/*	/*
	* This value indicates what type of request this is. The format for the	* Send with Immediate Allowed only on reliable connection (RC)
	* rest of the command is determined by this field.	* and unreliable datagram (UD) SQ's.
	*/	*/
	uint16_t cmpl_ring;	#define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1)
	/*	/*
	* This value indicates the what completion ring the request will be	* Send with Invalidate. Allowed only on reliable connection
	* optionally completed on. If the value is -1, then no CR completion	* (RC) SQ's.
	* will be generated. Any other value must be a valid CR ring_id value
	* for this function.
	*/	*/
	uint16_t seq_id;	#define SQ_BASE_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
	/* This value indicates the command sequence number. */	/* RDMA Write. Allowed only on reliable connection (RC) SQ's. */
	uint16_t target_id;	#define SQ_BASE_WQE_TYPE_WRITE_WQE UINT32_C(0x4)
	/*	/*
	* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids	* RDMA Write with Immediate. Allowed only on reliable
	* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM	* connection (RC) SQ's.
	*/	*/
	uint64_t resp_addr;	#define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
		/* RDMA Read. Allowed only on reliable connection (RC) SQ's. */
		#define SQ_BASE_WQE_TYPE_READ_WQE UINT32_C(0x6)
	/*	/*
	* This is the host address where the response will be written when the	* Atomic Compare/Swap. Allowed only on reliable connection (RC)
	* request is complete. This area must be 16B aligned and must be	* SQ's.
	* cleared to zero before the request is made.
	*/	*/
		#define SQ_BASE_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
		/* Atomic Fetch/Add. Allowed only on reliable connection (RC) SQ's. */
		#define SQ_BASE_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
		/* Local Invalidate. Allowed only on reliable connection (RC) SQ's. */
		#define SQ_BASE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
		/*
		* FR-PMR (Fast Register Physical Memory Region) Allowed only on
		* reliable connection (RC) SQ's.
		*/
		#define SQ_BASE_WQE_TYPE_FR_PMR UINT32_C(0xd)
		/* Memory Bind Allowed only on reliable connection (RC) SQ's. */
		#define SQ_BASE_WQE_TYPE_BIND UINT32_C(0xe)
		uint8_t unused_0[7];
	} __attribute__((packed));	} __attribute__((packed));

	/* Output (8 bytes) */	/* WQE SGE (16 bytes) */

	struct output {	struct sq_sge {
	uint16_t error_code;	uint64_t va_or_pa;
	/*	/*
	* Pass/Fail or error type Note: receiver to verify the in parameters,	* The virtual address in local memory or a physical address when l_key
	* and fail the call with an error when appropriate	* value is a reserved value of a physical address. Driver configures
		* this value in the chip and the chip compares l_key in SGEs with that
		* reserved value, if equal it access the physical address specified.
		* The chip however MUST verify that the QP allows the use reserved key.
	*/	*/
	uint16_t req_type;	uint32_t l_key;
	/* This field returns the type of original request. */
	uint16_t seq_id;
	/* This field provides original sequence number of the command. */
	uint16_t resp_len;
	/*	/*
	* This field is the length of the response in bytes. The last byte of	* Local Key associated with this registered MR; The 24 msb of the key
	* the response is a valid flag that will read as '1' when the command	* used to index the MRW Table and the 8 lsb are compared with the 8
	* has been completely written to memory.	* bits key part stored in the MRWC. The PBL in the MRW Context is used
		* to translate the above VA to physical address.
	*/	*/
		uint32_t size;
		/*
		* Size of SGE in bytes; Based on page size of the system the chip knows
		* how many entries are in the PBL
		*/
	} __attribute__((packed));	} __attribute__((packed));

	#define GET_HWRM_REQ_TYPE(x) \	/* PSN Search Structure (8 bytes) */
	((x) == 0x98 ? "HWRM_CFA_ENCAP_RECORD_FREE": \
	((x) == 0x99 ? "HWRM_CFA_NTUPLE_FILTER_ALLOC": \
	((x) == 0x90 ? "HWRM_CFA_L2_FILTER_ALLOC": \
	((x) == 0x91 ? "HWRM_CFA_L2_FILTER_FREE": \
	((x) == 0x92 ? "HWRM_CFA_L2_FILTER_CFG": \
	((x) == 0x93 ? "HWRM_CFA_L2_SET_RX_MASK": \
	((x) == 0x94 ? "RESERVED3": \
	((x) == 0x95 ? "HWRM_CFA_TUNNEL_FILTER_ALLOC": \
	((x) == 0x96 ? "HWRM_CFA_TUNNEL_FILTER_FREE": \
	((x) == 0x97 ? "HWRM_CFA_ENCAP_RECORD_ALLOC": \
	((x) == 0x10 ? "RESERVED1": \
	((x) == 0x11 ? "HWRM_FUNC_RESET": \
	((x) == 0x12 ? "HWRM_FUNC_GETFID": \
	((x) == 0x13 ? "HWRM_FUNC_VF_ALLOC": \
	((x) == 0x14 ? "HWRM_FUNC_VF_FREE": \
	((x) == 0x15 ? "HWRM_FUNC_QCAPS": \
	((x) == 0x16 ? "HWRM_FUNC_QCFG": \
	((x) == 0x17 ? "HWRM_FUNC_CFG": \
	((x) == 0x18 ? "HWRM_FUNC_QSTATS": \
	((x) == 0x19 ? "HWRM_FUNC_CLR_STATS": \
	((x) == 0xe0 ? "HWRM_TEMP_MONITOR_QUERY": \
	((x) == 0xd3 ? "HWRM_FWD_ASYNC_EVENT_CMPL": \
	((x) == 0xd2 ? "HWRM_FWD_RESP": \
	((x) == 0x1a ? "HWRM_FUNC_DRV_UNRGTR": \
	((x) == 0x1b ? "HWRM_FUNC_VF_RESC_FREE": \
	((x) == 0x1c ? "HWRM_FUNC_VF_VNIC_IDS_QUERY": \
	((x) == 0x1d ? "HWRM_FUNC_DRV_RGTR": \
	((x) == 0x1e ? "HWRM_FUNC_DRV_QVER": \
	((x) == 0x1f ? "HWRM_FUNC_BUF_RGTR": \
	((x) == 0x9a ? "HWRM_CFA_NTUPLE_FILTER_FREE": \
	((x) == 0x9b ? "HWRM_CFA_NTUPLE_FILTER_CFG": \
	((x) == 0x9c ? "HWRM_CFA_EM_FLOW_ALLOC": \
	((x) == 0x9d ? "HWRM_CFA_EM_FLOW_FREE": \
	((x) == 0x9e ? "HWRM_CFA_EM_FLOW_CFG": \
	((x) == 0xd1 ? "HWRM_REJECT_FWD_RESP": \
	((x) == 0xd0 ? "HWRM_EXEC_FWD_RESP": \
	((x) == 0xc8 ? "HWRM_FW_SET_TIME": \
	((x) == 0xc9 ? "HWRM_FW_GET_TIME": \
	((x) == 0xc0 ? "HWRM_FW_RESET": \
	((x) == 0xc1 ? "HWRM_FW_QSTATUS": \
	((x) == 0x70 ? "HWRM_VNIC_RSS_COS_LB_CTX_ALLOC": \
	((x) == 0x71 ? "HWRM_VNIC_RSS_COS_LB_CTX_FREE": \
	((x) == 0xb1 ? "HWRM_STAT_CTX_FREE": \
	((x) == 0xb0 ? "HWRM_STAT_CTX_ALLOC": \
	((x) == 0xb3 ? "HWRM_STAT_CTX_CLR_STATS": \
	((x) == 0xb2 ? "HWRM_STAT_CTX_QUERY": \
	((x) == 0xfff6 ? "HWRM_NVM_GET_DEV_INFO": \
	((x) == 0x61 ? "HWRM_RING_GRP_FREE": \
	((x) == 0x60 ? "HWRM_RING_GRP_ALLOC": \
	((x) == 0xf1 ? "HWRM_WOL_FILTER_FREE": \
	((x) == 0xf0 ? "HWRM_WOL_FILTER_ALLOC": \
	((x) == 0xf3 ? "HWRM_WOL_REASON_QCFG": \
	((x) == 0xf2 ? "HWRM_WOL_FILTER_QCFG": \
	((x) == 0xa0 ? "HWRM_TUNNEL_DST_PORT_QUERY": \
	((x) == 0xa1 ? "HWRM_TUNNEL_DST_PORT_ALLOC": \
	((x) == 0xa2 ? "HWRM_TUNNEL_DST_PORT_FREE": \
	((x) == 0xfffc ? "HWRM_NVM_RAW_DUMP": \
	((x) == 0xfffb ? "HWRM_NVM_GET_DIR_INFO": \
	((x) == 0xfffa ? "HWRM_NVM_GET_DIR_ENTRIES": \
	((x) == 0xe ? "HWRM_FUNC_BUF_UNRGTR": \
	((x) == 0xf ? "HWRM_FUNC_VF_CFG": \
	((x) == 0xffff ? "HWRM_NVM_RAW_WRITE_BLK": \
	((x) == 0xfffe ? "HWRM_NVM_WRITE": \
	((x) == 0xfffd ? "HWRM_NVM_READ": \
	((x) == 0x50 ? "HWRM_RING_ALLOC": \
	((x) == 0x51 ? "HWRM_RING_FREE": \
	((x) == 0x52 ? "HWRM_RING_CMPL_RING_QAGGINT_PARAMS": \
	((x) == 0x53 ? "HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS": \
	((x) == 0x4a ? "HWRM_VNIC_QCAPS": \
	((x) == 0x49 ? "HWRM_VNIC_PLCMODES_QCFG": \
	((x) == 0x48 ? "HWRM_VNIC_PLCMODES_CFG": \
	((x) == 0x47 ? "HWRM_VNIC_RSS_QCFG": \
	((x) == 0x46 ? "HWRM_VNIC_RSS_CFG": \
	((x) == 0x45 ? "HWRM_VNIC_TPA_QCFG": \
	((x) == 0x44 ? "HWRM_VNIC_TPA_CFG": \
	((x) == 0x43 ? "HWRM_VNIC_QCFG": \
	((x) == 0x42 ? "HWRM_VNIC_CFG": \
	((x) == 0x41 ? "HWRM_VNIC_FREE": \
	((x) == 0x40 ? "HWRM_VNIC_ALLOC": \
	((x) == 0x0 ? "HWRM_VER_GET": \
	((x) == 0xfff9 ? "HWRM_NVM_FIND_DIR_ENTRY": \
	((x) == 0xfff8 ? "HWRM_NVM_MOD_DIR_ENTRY": \
	((x) == 0xfff7 ? "HWRM_NVM_ERASE_DIR_ENTRY": \
	((x) == 0x5e ? "HWRM_RING_RESET": \
	((x) == 0xfff5 ? "HWRM_NVM_VERIFY_UPDATE": \
	((x) == 0xfff4 ? "HWRM_NVM_MODIFY": \
	((x) == 0xfff3 ? "HWRM_NVM_INSTALL_UPDATE": \
	((x) == 0x2a ? "HWRM_PORT_PHY_QCAPS": \
	((x) == 0x2c ? "HWRM_PORT_PHY_I2C_READ": \
	((x) == 0x2b ? "HWRM_PORT_PHY_I2C_WRITE": \
	((x) == 0x38 ? "HWRM_QUEUE_PRI2COS_CFG": \
	((x) == 0x39 ? "HWRM_QUEUE_COS2BW_QCFG": \
	((x) == 0x32 ? "HWRM_QUEUE_CFG": \
	((x) == 0x33 ? "HWRM_QUEUE_BUFFERS_QCFG": \
	((x) == 0x30 ? "HWRM_QUEUE_QPORTCFG": \
	((x) == 0x31 ? "HWRM_QUEUE_QCFG": \
	((x) == 0x36 ? "HWRM_QUEUE_PFCENABLE_CFG": \
	((x) == 0x37 ? "HWRM_QUEUE_PRI2COS_QCFG": \
	((x) == 0x34 ? "HWRM_QUEUE_BUFFERS_CFG": \
	((x) == 0x35 ? "HWRM_QUEUE_PFCENABLE_QCFG": \
	((x) == 0xff14 ? "HWRM_DBG_DUMP": \
	((x) == 0xff12 ? "HWRM_DBG_WRITE_DIRECT": \
	((x) == 0xff13 ? "HWRM_DBG_WRITE_INDIRECT": \
	((x) == 0xff10 ? "HWRM_DBG_READ_DIRECT": \
	((x) == 0xff11 ? "HWRM_DBG_READ_INDIRECT": \
	((x) == 0x25 ? "HWRM_PORT_CLR_STATS": \
	((x) == 0x24 ? "HWRM_PORT_LPBK_QSTATS": \
	((x) == 0x27 ? "HWRM_PORT_PHY_QCFG": \
	((x) == 0x26 ? "HWRM_PORT_LPBK_CLR_STATS": \
	((x) == 0x21 ? "HWRM_PORT_MAC_CFG": \
	((x) == 0x20 ? "HWRM_PORT_PHY_CFG": \
	((x) == 0x23 ? "HWRM_PORT_QSTATS": \
	((x) == 0x22 ? "HWRM_PORT_TS_QUERY": \
	((x) == 0x29 ? "HWRM_PORT_BLINK_LED": \
	((x) == 0x28 ? "HWRM_PORT_MAC_QCFG": \
	((x) == 0x3a ? "HWRM_QUEUE_COS2BW_CFG": \
	"Unknown req_type"))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))

	/* Command numbering (8 bytes) */	struct sq_psn_search {
		uint32_t opcode_start_psn;
		/* The opcodes are software defined. */
		/* Start PSN. */
		#define SQ_PSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff)
		#define SQ_PSN_SEARCH_START_PSN_SFT 0
		/* The opcodes are software defined. */
		#define SQ_PSN_SEARCH_OPCODE_MASK UINT32_C(0xff000000)
		#define SQ_PSN_SEARCH_OPCODE_SFT 24
		uint32_t flags_next_psn;
		/* Opcode specific flags. */
		/* Next PSN. Equal to the start PSN of the next WQE. */
		#define SQ_PSN_SEARCH_NEXT_PSN_MASK UINT32_C(0xffffff)
		#define SQ_PSN_SEARCH_NEXT_PSN_SFT 0
		/* Opcode specific flags. */
		#define SQ_PSN_SEARCH_FLAGS_MASK UINT32_C(0xff000000)
		#define SQ_PSN_SEARCH_FLAGS_SFT 24
		} __attribute__((packed));

	struct cmd_nums {	/* Send SQ WQE (40 bytes) */
	uint16_t req_type;
		struct sq_send {
		uint8_t wqe_type;
		/* This field defines the type of SQ WQE. */
		/* Send */
		#define SQ_SEND_WQE_TYPE_SEND UINT32_C(0x0)
	/*	/*
	* This version of the specification defines the commands listed in the	* Send with Immediate Allowed only on reliable connection (RC)
	* table below. The following are general implementation requirements	* and unreliable datagram (UD) SQ's.
	* for these commands: # All commands listed below that are marked
	* neither reserved nor experimental shall be implemented by the HWRM. #
	* A HWRM client compliant to this specification should not use commands
	* outside of the list below. # A HWRM client compliant to this
	* specification should not use command numbers marked reserved below. #
	* A command marked experimental below may not be implemented by the
	* HWRM. # A command marked experimental may change in the future
	* version of the HWRM specification. # A command not listed below may
	* be implemented by the HWRM. The behavior of commands that are not
	* listed below is outside the scope of this specification.
	*/	*/
	#define HWRM_VER_GET (UINT32_C(0x0))	#define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1)
	#define HWRM_FUNC_BUF_UNRGTR (UINT32_C(0xe))	/*
	/* Experimental */	* Send with Invalidate. Allowed only on reliable connection
	#define HWRM_FUNC_VF_CFG (UINT32_C(0xf))	* (RC) SQ's.
	/* Reserved for future use */	*/
	#define RESERVED1 (UINT32_C(0x10))	#define SQ_SEND_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
	#define HWRM_FUNC_RESET (UINT32_C(0x11))	uint8_t flags;
	#define HWRM_FUNC_GETFID (UINT32_C(0x12))	/*
	#define HWRM_FUNC_VF_ALLOC (UINT32_C(0x13))	* Set if completion signaling is requested. If this bit is 0, and the
	#define HWRM_FUNC_VF_FREE (UINT32_C(0x14))	* SQ is configured to support Unsignaled completion the controller
	#define HWRM_FUNC_QCAPS (UINT32_C(0x15))	* should not generate a CQE unless there was an error. This refers to
	#define HWRM_FUNC_QCFG (UINT32_C(0x16))	* the CQE on the sender side. (The se flag refers to the receiver
	#define HWRM_FUNC_CFG (UINT32_C(0x17))	* side).
	#define HWRM_FUNC_QSTATS (UINT32_C(0x18))	*/
	#define HWRM_FUNC_CLR_STATS (UINT32_C(0x19))	#define SQ_SEND_FLAGS_SIGNAL_COMP UINT32_C(0x1)
	#define HWRM_FUNC_DRV_UNRGTR (UINT32_C(0x1a))	/*
	#define HWRM_FUNC_VF_RESC_FREE (UINT32_C(0x1b))	* Indication to complete all previous RDMA Read or Atomic WQEs on the
	#define HWRM_FUNC_VF_VNIC_IDS_QUERY (UINT32_C(0x1c))	* SQ before executing this WQE. This flag must be zero for a UD send.
	#define HWRM_FUNC_DRV_RGTR (UINT32_C(0x1d))	*/
	#define HWRM_FUNC_DRV_QVER (UINT32_C(0x1e))	#define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
	#define HWRM_FUNC_BUF_RGTR (UINT32_C(0x1f))	/*
	#define HWRM_PORT_PHY_CFG (UINT32_C(0x20))	* For local invalidate request. Indicate to complete all previous SQ's
	#define HWRM_PORT_MAC_CFG (UINT32_C(0x21))	* WQEs before executing this WQE. This flag must be zero for a UD send.
	/* Experimental */	*/
	#define HWRM_PORT_TS_QUERY (UINT32_C(0x22))	#define SQ_SEND_FLAGS_UC_FENCE UINT32_C(0x4)
	#define HWRM_PORT_QSTATS (UINT32_C(0x23))	/*
	#define HWRM_PORT_LPBK_QSTATS (UINT32_C(0x24))	* Solicit event flag. Indication sent in BTH header to the receiver to
	/* Experimental */	* generate a Completion Event Notification, i.e. CNQE. This bit should
	#define HWRM_PORT_CLR_STATS (UINT32_C(0x25))	* be set only in the last (or only) packet of the message.
	/* Experimental */	*/
	#define HWRM_PORT_LPBK_CLR_STATS (UINT32_C(0x26))	#define SQ_SEND_FLAGS_SE UINT32_C(0x8)
	#define HWRM_PORT_PHY_QCFG (UINT32_C(0x27))	/*
	/* Experimental */	* Indicate that inline data is posted to the SQ in the data area of
	#define HWRM_PORT_MAC_QCFG (UINT32_C(0x28))	* this WQE.
	/* Experimental */	*/
	#define HWRM_PORT_BLINK_LED (UINT32_C(0x29))	#define SQ_SEND_FLAGS_INLINE UINT32_C(0x10)
	/* Experimental */	uint8_t wqe_size;
	#define HWRM_PORT_PHY_QCAPS (UINT32_C(0x2a))	/*
	/* Experimental */	* The number of 16 bytes chunks of data including this first word of
	#define HWRM_PORT_PHY_I2C_WRITE (UINT32_C(0x2b))	* the request that are a valid part of the request. The valid 16 bytes
	/* Experimental */	* units other than the WQE structure can be SGEs (Scatter Gather
	#define HWRM_PORT_PHY_I2C_READ (UINT32_C(0x2c))	* Elements) OR inline data. While this field defines the valid WQE
	#define HWRM_QUEUE_QPORTCFG (UINT32_C(0x30))	* size. The actual total WQE size is always 128B.
	#define HWRM_QUEUE_QCFG (UINT32_C(0x31))	*/
	#define HWRM_QUEUE_CFG (UINT32_C(0x32))	uint8_t reserved8_1;
	#define HWRM_QUEUE_BUFFERS_QCFG (UINT32_C(0x33))	uint32_t inv_key_or_imm_data;
	#define HWRM_QUEUE_BUFFERS_CFG (UINT32_C(0x34))	/*
	/* Experimental */	* Either invalidate key (R_Key of the remote host) that will be send
	#define HWRM_QUEUE_PFCENABLE_QCFG (UINT32_C(0x35))	* with IETH (Invalidate ETH) if wqe_type is of Send with Invalidate, or
	/* Experimental */	* immediate value that will be sent with ImmDt header if wqe_type is
	#define HWRM_QUEUE_PFCENABLE_CFG (UINT32_C(0x36))	* Send with Immediate.
	/* Experimental */	*/
	#define HWRM_QUEUE_PRI2COS_QCFG (UINT32_C(0x37))	uint32_t length;
	/* Experimental */	/* This field represents a 32-bit total data length, in bytes. */
	#define HWRM_QUEUE_PRI2COS_CFG (UINT32_C(0x38))	uint32_t q_key;
	/* Experimental */	/*
	#define HWRM_QUEUE_COS2BW_QCFG (UINT32_C(0x39))	* When in the SQ of a UD QP, indicates the q_key to be used in the
	/* Experimental */	* transmitted packet. However, if the most significant bit of this
	#define HWRM_QUEUE_COS2BW_CFG (UINT32_C(0x3a))	* field is set, then the q_key will be taken from QP context, rather
	#define HWRM_VNIC_ALLOC (UINT32_C(0x40))	* than from this field. When in the SQ of a non-UD QP, this field is
	#define HWRM_VNIC_FREE (UINT32_C(0x41))	* reserved and should be filled with zeros.
	#define HWRM_VNIC_CFG (UINT32_C(0x42))	*/
	/* Experimental */	uint32_t dst_qp;
	#define HWRM_VNIC_QCFG (UINT32_C(0x43))	/*
	#define HWRM_VNIC_TPA_CFG (UINT32_C(0x44))	* When in the SQ of a UD QP, indicates the destination QP to be used in
	/* Experimental */	* the transmitted packet. When in the SQ of a non-UD QP, this field is
	#define HWRM_VNIC_TPA_QCFG (UINT32_C(0x45))	* reserved and should be filled with zeros.
	#define HWRM_VNIC_RSS_CFG (UINT32_C(0x46))	*/
	#define HWRM_VNIC_RSS_QCFG (UINT32_C(0x47))	#define SQ_SEND_DST_QP_MASK UINT32_C(0xffffff)
	#define HWRM_VNIC_PLCMODES_CFG (UINT32_C(0x48))	#define SQ_SEND_DST_QP_SFT 0
	#define HWRM_VNIC_PLCMODES_QCFG (UINT32_C(0x49))	#define SQ_SEND_RESERVED8_2_MASK UINT32_C(0xff000000)
	/* Experimental */	#define SQ_SEND_RESERVED8_2_SFT 24
	#define HWRM_VNIC_QCAPS (UINT32_C(0x4a))	uint32_t avid;
	#define HWRM_RING_ALLOC (UINT32_C(0x50))	/* This field is reserved for future expansion of the AVID. */
	#define HWRM_RING_FREE (UINT32_C(0x51))	/*
	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (UINT32_C(0x52))	* If the serv_type is 'UD', then this field supplies the AVID (Address
	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (UINT32_C(0x53))	* Vector ID).
	#define HWRM_RING_RESET (UINT32_C(0x5e))	*/
	#define HWRM_RING_GRP_ALLOC (UINT32_C(0x60))	#define SQ_SEND_AVID_MASK UINT32_C(0xfffff)
	#define HWRM_RING_GRP_FREE (UINT32_C(0x61))	#define SQ_SEND_AVID_SFT 0
	#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (UINT32_C(0x70))	/* This field is reserved for future expansion of the AVID. */
	#define HWRM_VNIC_RSS_COS_LB_CTX_FREE (UINT32_C(0x71))	#define SQ_SEND_RESERVED_AVID_MASK UINT32_C(0xfff00000)
	#define HWRM_CFA_L2_FILTER_ALLOC (UINT32_C(0x90))	#define SQ_SEND_RESERVED_AVID_SFT 20
	#define HWRM_CFA_L2_FILTER_FREE (UINT32_C(0x91))	uint64_t reserved64;
	#define HWRM_CFA_L2_FILTER_CFG (UINT32_C(0x92))	uint32_t data[24];
	#define HWRM_CFA_L2_SET_RX_MASK (UINT32_C(0x93))	/*
	/* Reserved for future use */	* When inline=0, then this area is filled with from 1 to 6 SGEs based
	#define RESERVED3 (UINT32_C(0x94))	* on the wqe_size field. When inline=1, this area is filled with
	#define HWRM_CFA_TUNNEL_FILTER_ALLOC (UINT32_C(0x95))	* payload data for the send based on the length_or_AVID field. Bits
	#define HWRM_CFA_TUNNEL_FILTER_FREE (UINT32_C(0x96))	* [7:0] of word 0 hold the first byte to go out on the wire.
	/* Experimental */	*/
	#define HWRM_CFA_ENCAP_RECORD_ALLOC (UINT32_C(0x97))
	/* Experimental */
	#define HWRM_CFA_ENCAP_RECORD_FREE (UINT32_C(0x98))
	#define HWRM_CFA_NTUPLE_FILTER_ALLOC (UINT32_C(0x99))
	#define HWRM_CFA_NTUPLE_FILTER_FREE (UINT32_C(0x9a))
	#define HWRM_CFA_NTUPLE_FILTER_CFG (UINT32_C(0x9b))
	/* Experimental */
	#define HWRM_CFA_EM_FLOW_ALLOC (UINT32_C(0x9c))
	/* Experimental */
	#define HWRM_CFA_EM_FLOW_FREE (UINT32_C(0x9d))
	/* Experimental */
	#define HWRM_CFA_EM_FLOW_CFG (UINT32_C(0x9e))
	#define HWRM_TUNNEL_DST_PORT_QUERY (UINT32_C(0xa0))
	#define HWRM_TUNNEL_DST_PORT_ALLOC (UINT32_C(0xa1))
	#define HWRM_TUNNEL_DST_PORT_FREE (UINT32_C(0xa2))
	#define HWRM_STAT_CTX_ALLOC (UINT32_C(0xb0))
	#define HWRM_STAT_CTX_FREE (UINT32_C(0xb1))
	#define HWRM_STAT_CTX_QUERY (UINT32_C(0xb2))
	#define HWRM_STAT_CTX_CLR_STATS (UINT32_C(0xb3))
	#define HWRM_FW_RESET (UINT32_C(0xc0))
	#define HWRM_FW_QSTATUS (UINT32_C(0xc1))
	/* Experimental */
	#define HWRM_FW_SET_TIME (UINT32_C(0xc8))
	/* Experimental */
	#define HWRM_FW_GET_TIME (UINT32_C(0xc9))
	#define HWRM_EXEC_FWD_RESP (UINT32_C(0xd0))
	#define HWRM_REJECT_FWD_RESP (UINT32_C(0xd1))
	#define HWRM_FWD_RESP (UINT32_C(0xd2))
	#define HWRM_FWD_ASYNC_EVENT_CMPL (UINT32_C(0xd3))
	#define HWRM_TEMP_MONITOR_QUERY (UINT32_C(0xe0))
	/* Experimental */
	#define HWRM_WOL_FILTER_ALLOC (UINT32_C(0xf0))
	/* Experimental */
	#define HWRM_WOL_FILTER_FREE (UINT32_C(0xf1))
	/* Experimental */
	#define HWRM_WOL_FILTER_QCFG (UINT32_C(0xf2))
	/* Experimental */
	#define HWRM_WOL_REASON_QCFG (UINT32_C(0xf3))
	/* Experimental */
	#define HWRM_DBG_READ_DIRECT (UINT32_C(0xff10))
	/* Experimental */
	#define HWRM_DBG_READ_INDIRECT (UINT32_C(0xff11))
	/* Experimental */
	#define HWRM_DBG_WRITE_DIRECT (UINT32_C(0xff12))
	/* Experimental */
	#define HWRM_DBG_WRITE_INDIRECT (UINT32_C(0xff13))
	#define HWRM_DBG_DUMP (UINT32_C(0xff14))
	#define HWRM_NVM_INSTALL_UPDATE (UINT32_C(0xfff3))
	#define HWRM_NVM_MODIFY (UINT32_C(0xfff4))
	#define HWRM_NVM_VERIFY_UPDATE (UINT32_C(0xfff5))
	#define HWRM_NVM_GET_DEV_INFO (UINT32_C(0xfff6))
	#define HWRM_NVM_ERASE_DIR_ENTRY (UINT32_C(0xfff7))
	#define HWRM_NVM_MOD_DIR_ENTRY (UINT32_C(0xfff8))
	#define HWRM_NVM_FIND_DIR_ENTRY (UINT32_C(0xfff9))
	#define HWRM_NVM_GET_DIR_ENTRIES (UINT32_C(0xfffa))
	#define HWRM_NVM_GET_DIR_INFO (UINT32_C(0xfffb))
	#define HWRM_NVM_RAW_DUMP (UINT32_C(0xfffc))
	#define HWRM_NVM_READ (UINT32_C(0xfffd))
	#define HWRM_NVM_WRITE (UINT32_C(0xfffe))
	#define HWRM_NVM_RAW_WRITE_BLK (UINT32_C(0xffff))
	uint16_t unused_0[3];
	} __attribute__((packed));	} __attribute__((packed));

	#define GET_HWRM_ERROR_CODE(x) \	/* Send Raw Ethernet and QP1 SQ WQE (40 bytes) */
	((x) == 0xf ? "HWRM_ERROR": \
	((x) == 0xffff ? "CMD_NOT_SUPPORTED": \
	((x) == 0xfffe ? "UNKNOWN_ERR": \
	((x) == 0x4 ? "RESOURCE_ALLOC_ERROR": \
	((x) == 0x5 ? "INVALID_FLAGS": \
	((x) == 0x6 ? "INVALID_ENABLES": \
	((x) == 0x0 ? "SUCCESS": \
	((x) == 0x1 ? "FAIL": \
	((x) == 0x2 ? "INVALID_PARAMS": \
	((x) == 0x3 ? "RESOURCE_ACCESS_DENIED": \
	"Unknown error_code"))))))))))

	/* Return Codes (8 bytes) */	struct sq_send_raweth_qp1 {
		uint8_t wqe_type;
		/* This field defines the type of SQ WQE. */
		/* Send */
		#define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND UINT32_C(0x0)
		uint8_t flags;
		/*
		* Set if completion signaling is requested. If this bit is 0, and the
		* SQ is configured to support Unsignaled completion the controller
		* should not generate a CQE unless there was an error. This refers to
		* the CQE on the sender side. (The se flag refers to the receiver
		* side).
		*/
		#define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP UINT32_C(0x1)
		/* This flag must be zero for a Raweth or QP1 send. */
		#define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
		/* This flag must be zero for a Raweth or QP1 send. */
		#define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE UINT32_C(0x4)
		/* This flag must be zero for a Raweth or QP1 send. */
		#define SQ_SEND_RAWETH_QP1_FLAGS_SE UINT32_C(0x8)
		/*
		* Indicate that inline data is posted to the SQ in the data area of
		* this WQE.
		*/
		#define SQ_SEND_RAWETH_QP1_FLAGS_INLINE UINT32_C(0x10)
		uint8_t wqe_size;
		/*
		* The number of 16 bytes chunks of data including this first word of
		* the request that are a valid part of the request. The valid 16 bytes
		* units other than the WQE structure can be SGEs (Scatter Gather
		* Elements) OR inline data. While this field defines the valid WQE
		* size. The actual total WQE size is always 128B.
		*/
		uint8_t reserved8;
		uint16_t lflags;
		/*
		* All bits in this field must be valid on the first BD of a packet.
		* Their value on other BDs of the packet will be ignored.
		*/
		/*
		* If set to 1, the controller replaces the TCP/UPD checksum fields of
		* normal TCP/UPD checksum, or the inner TCP/UDP checksum field of the
		* encapsulated TCP/UDP packets with the hardware calculated TCP/UDP
		* checksum for the packet associated with this descriptor. This bit
		* must be valid on the first BD of a packet.
		*/
		#define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
		/*
		* If set to 1, the controller replaces the IP checksum of the normal
		* packets, or the inner IP checksum of the encapsulated packets with
		* the hardware calculated IP checksum for the packet associated with
		* this descriptor. This bit must be valid on the first BD of a packet.
		*/
		#define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM UINT32_C(0x2)
		/*
		* If set to 1, the controller will not append an Ethernet CRC to the
		* end of the frame. This bit must be valid on the first BD of a packet.
		* Packet must be 64B or longer when this flag is set. It is not usefull
		* to use this bit with any form of TX offload such as CSO or LSO. The
		* intent is that the packet from the host already has a valid Ethernet
		* CRC on the packet.
		*/
		#define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC UINT32_C(0x4)
		/*
		* If set to 1, the device will record the time at which the packet was
		* actually transmitted at the TX MAC. This bit must be valid on the
		* first BD of a packet.
		*/
		#define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP UINT32_C(0x8)
		/*
		* If set to 1, The controller replaces the tunnel IP checksum field
		* with hardware calculated IP checksum for the IP header of the packet
		* associated with this descriptor. In case of VXLAN, the controller
		* also replaces the outer header UDP checksum with hardware calculated
		* UDP checksum for the packet associated with this descriptor.
		*/
		#define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
		/* This bit is reserved and should be zero. */
		#define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_1 UINT32_C(0x20)
		/* This bit is reserved and should be zero. */
		#define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_2 UINT32_C(0x40)
		/* This bit is reserved and should be zero. */
		#define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_3 UINT32_C(0x80)
		/*
		* If set to '1', then the RoCE ICRC will be appended to the packet.
		* Packet must be a valid RoCE format packet.
		*/
		#define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC UINT32_C(0x100)
		/*
		* If set to '1', then the FCoE CRC will be appended to the packet.
		* Packet must be a valid FCoE format packet.
		*/
		#define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC UINT32_C(0x200)
		uint16_t cfa_action;
		/*
		* This value selects a CFA action to perform on the packet. Set this
		* value to zero if no CFA action is desired. This value must be valid
		* on the first BD of a packet.
		*/
		uint32_t length;
		/*
		* This field represents a 32-bit total data length, in bytes. Note,
		* however, that the length cannot exceed the MTU.
		*/
		uint32_t reserved32_1;
		uint32_t cfa_meta;
		/*
		* This value is action meta-data that defines CFA edit operations that
		* are done in addition to any action editing.
		*/
		/* When key=1, This is the VLAN tag VID value. */
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0
		/* When key=1, This is the VLAN tag DE value. */
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE UINT32_C(0x1000)
		/* When key=1, This is the VLAN tag PRI value. */
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13
		/* When key=1, This is the VLAN tag TPID select value. */
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16
		/* 0x88a8 */
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
		/* 0x8100 */
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
		/* 0x9100 */
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
		/* 0x9200 */
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
		/* 0x9300 */
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
		/* Value programmed in CFA VLANTPID register. */
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG
		/* When key=1, This is the VLAN tag TPID select value. */
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19
		/*
		* This field identifies the type of edit to be performed on the packet.
		* This value must be valid on the first BD of a packet.
		*/
		#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK UINT32_C(0xf0000000)
		#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28
		/* No editing */
		#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
		/*
		* - meta[17:16] - TPID select value (0 = 0x8100). - meta[15:12]
		* - PRI/DE value. - meta[11:0] - VID value.
		*/
		#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
		#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG
		uint32_t reserved32_2;
		uint64_t reserved64;
		uint32_t data[24];
		/*
		* When inline=0, then this area is filled with from 1 to 6 SGEs based
		* on the wqe_size field. When inline=1, this area is filled with
		* payload data for the send based on the length_or_AVID field. Bits
		* [7:0] of word 0 hold the first byte to go out on the wire.
		*/
		} __attribute__((packed));

	struct ret_codes {	/* RDMA SQ WQE (40 bytes) */
	uint16_t error_code;
	/* These are numbers assigned to return/error codes. */	struct sq_rdma {
	/* Request was successfully executed by the HWRM. */	uint8_t wqe_type;
	#define HWRM_ERR_CODE_SUCCESS (UINT32_C(0x0))	/* This field defines the type of SQ WQE. */
	/* THe HWRM failed to execute the request. */	/* RDMA Write. Allowed only on reliable connection (RC) SQ's. */
	#define HWRM_ERR_CODE_FAIL (UINT32_C(0x1))	#define SQ_RDMA_WQE_TYPE_WRITE_WQE UINT32_C(0x4)
	/* The request contains invalid argument(s) or input parameters. */
	#define HWRM_ERR_CODE_INVALID_PARAMS (UINT32_C(0x2))
	/*	/*
	* The requester is not allowed to access the requested	* RDMA Write with Immediate. Allowed only on reliable
	* resource. This error code shall be provided in a response to	* connection (RC) SQ's.
	* a request to query or modify an existing resource that is not
	* accessible by the requester.
	*/	*/
	#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (UINT32_C(0x3))	#define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
		/* RDMA Read. Allowed only on reliable connection (RC) SQ's. */
		#define SQ_RDMA_WQE_TYPE_READ_WQE UINT32_C(0x6)
		uint8_t flags;
	/*	/*
	* The HWRM is unable to allocate the requested resource. This	* Set if completion signaling is requested. If this bit is 0, and the
	* code only applies to requests for HWRM resource allocations.	* SQ is configured to support Unsignaled completion the controller
		* should not generate a CQE unless there was an error. This refer to
		* CQE on the sender side (se_flag refer to the receiver side)
	*/	*/
	#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (UINT32_C(0x4))	#define SQ_RDMA_FLAGS_SIGNAL_COMP UINT32_C(0x1)
	/* Invalid combination of flags is specified in the request. */
	#define HWRM_ERR_CODE_INVALID_FLAGS (UINT32_C(0x5))
	/*	/*
	* Invalid combination of enables fields is specified in the	* Indication to complete all previous RDMA Read or Atomic WQEs on the
	* request.	* SQ before executing this WQE
	*/	*/
	#define HWRM_ERR_CODE_INVALID_ENABLES (UINT32_C(0x6))	#define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
	/* Generic HWRM execution error that represents an internal error. */	/*
	#define HWRM_ERR_CODE_HWRM_ERROR (UINT32_C(0xf))	* Unconditional fence. Indicate to complete all previous SQ's WQEs
	/* Unknown error */	* before executing this WQE.
	#define HWRM_ERR_CODE_UNKNOWN_ERR (UINT32_C(0xfffe))	*/
	/* Unsupported or invalid command */	#define SQ_RDMA_FLAGS_UC_FENCE UINT32_C(0x4)
	#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (UINT32_C(0xffff))	/*
	uint16_t unused_0[3];	* Solicit event. Indication sent in BTH header to the receiver to
		* generate a Completion Event Notification, i.e. CNQE. This bit should
		* be set only in the last (or only) packet of the message.
		*/
		#define SQ_RDMA_FLAGS_SE UINT32_C(0x8)
		/*
		* Indicate that inline data is posted to the SQ following this WQE.
		* This bit may be 1 only for write operations.
		*/
		#define SQ_RDMA_FLAGS_INLINE UINT32_C(0x10)
		uint8_t wqe_size;
		/*
		* The number of 16 bytes chunks of data including this first wqe of the
		* request that are a valid part of the request. The valid 16 bytes
		* units other than the WQE structure can be SGEs (Scatter Gather
		* Elements) OR inline data. While this field defines the valid WQE
		* size. The actual total WQE size is always 128B.
		*/
		uint8_t reserved8;
		uint32_t imm_data;
		/*
		* Immediate data - valid for RDMA Write with immediate and causes the
		* controller to add immDt header with this value
		*/
		uint32_t length;
		/* Total data length in bytes */
		uint32_t reserved32_1;
		uint64_t remote_va;
		/* Remote VA sent to the destination QP */
		uint32_t remote_key;
		/*
		* R_Key provided by remote node when the connection was established and
		* placed in the RETH header. It identify the MRW on the remote host
		*/
		uint32_t reserved32_2;
		uint32_t data[24];
		/*
		* When inline=0, then this area is filled with from 1 to 6 SGEs based
		* on the wqe_size field. When inline=1, this area is filled with
		* payload data for the write based on the length field. Bits [7:0] of
		* word 0 hold the first byte to go out on the wire.
		*/
	} __attribute__((packed));	} __attribute__((packed));

	/* Output (16 bytes) */	/* Atomic SQ WQE (40 bytes) */

	struct hwrm_err_output {	struct sq_atomic {
	uint16_t error_code;	uint8_t wqe_type;
		/* This field defines the type of SQ WQE. */
	/*	/*
	* Pass/Fail or error type Note: receiver to verify the in parameters,	* Atomic Compare/Swap. Allowed only on reliable connection (RC)
	* and fail the call with an error when appropriate	* SQ's.
	*/	*/
	uint16_t req_type;	#define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
	/* This field returns the type of original request. */	/* Atomic Fetch/Add. Allowed only on reliable connection (RC) SQ's. */
	uint16_t seq_id;	#define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
	/* This field provides original sequence number of the command. */	uint8_t flags;
	uint16_t resp_len;
	/*	/*
	* This field is the length of the response in bytes. The last byte of	* Set if completion signaling is requested. If this bit is 0, and the
	* the response is a valid flag that will read as '1' when the command	* SQ is configured to support Unsignaled completion the controller
	* has been completely written to memory.	* should not generate a CQE unless there was an error. This refer to
		* CQE on the sender side (se_flag refer to the receiver side)
	*/	*/
	uint32_t opaque_0;	#define SQ_ATOMIC_FLAGS_SIGNAL_COMP UINT32_C(0x1)
	/* debug info for this error response. */
	uint16_t opaque_1;
	/* debug info for this error response. */
	uint8_t cmd_err;
	/*	/*
	* In the case of an error response, command specific error code is	* Indication to complete all previous RDMA Read or Atomic WQEs on the
	* returned in this field.	* SQ before executing this WQE
	*/	*/
	uint8_t valid;	#define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
	/*	/*
	* This field is used in Output records to indicate that the output is	* Unconditional fence. Indicate to complete all previous SQ's WQEs
	* completely written to RAM. This field should be read as '1' to	* before executing this WQE.
	* indicate that the output has been completely written. When writing a
	* command completion or response to an internal processor, the order of
	* writes has to be such that this field is written last.
	*/	*/
		#define SQ_ATOMIC_FLAGS_UC_FENCE UINT32_C(0x4)
		/*
		* Solicit event. Indication sent in BTH header to the receiver to
		* generate a Completion Event Notification, i.e. CNQE. This bit should
		* be set only in the last (or only) packet of the message.
		*/
		#define SQ_ATOMIC_FLAGS_SE UINT32_C(0x8)
		/* NA for this WQE. */
		#define SQ_ATOMIC_FLAGS_INLINE UINT32_C(0x10)
		uint16_t reserved16;
		uint32_t remote_key;
		/*
		* R_Key provided by remote node when the connection was established and
		* placed in the AETH header. It identify the MRW on the remote host
		*/
		uint64_t remote_va;
		/* Remote VA sent to the destination QP */
		uint64_t swap_data;
		/* Data value to be placed in remote host specified address */
		uint64_t cmp_data;
		/*
		* Data value to be compared with the value in the remote host specified
		* address
		*/
		uint32_t data[24];
		/*
		* The first 16B of the data field must be filled with a single SGE.
		* This will be used to store the return value from the Atomic Ack
		* response. The size of the single SGE must be 8B.
		*/
	} __attribute__((packed));	} __attribute__((packed));

	/* Port Tx Statistics Formats (408 bytes) */	/* Local Invalidate SQ WQE (40 bytes) */

	struct tx_port_stats {	struct sq_localinvalidate {
	uint64_t tx_64b_frames;	uint8_t wqe_type;
	/* Total Number of 64 Bytes frames transmitted */	/* This field defines the type of SQ WQE. */
	uint64_t tx_65b_127b_frames;	/* Local Invalidate. Allowed only on reliable connection (RC) SQ's. */
	/* Total Number of 65-127 Bytes frames transmitted */	#define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
	uint64_t tx_128b_255b_frames;	uint8_t flags;
	/* Total Number of 128-255 Bytes frames transmitted */
	uint64_t tx_256b_511b_frames;
	/* Total Number of 256-511 Bytes frames transmitted */
	uint64_t tx_512b_1023b_frames;
	/* Total Number of 512-1023 Bytes frames transmitted */
	uint64_t tx_1024b_1518_frames;
	/* Total Number of 1024-1518 Bytes frames transmitted */
	uint64_t tx_good_vlan_frames;
	/*	/*
	* Total Number of each good VLAN (exludes FCS errors) frame transmitted	* Set if completion signaling is requested. If this bit is 0, and the
	* which is 1519 to 1522 bytes in length inclusive (excluding framing	* SQ is configured to support Unsignaled completion the controller
	* bits but including FCS bytes).	* should not generate a CQE unless there was an error. This refer to
		* CQE on the sender side (se_flag refer to the receiver side)
	*/	*/
	uint64_t tx_1519b_2047_frames;	#define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP UINT32_C(0x1)
	/* Total Number of 1519-2047 Bytes frames transmitted */	/*
	uint64_t tx_2048b_4095b_frames;	* Indication to complete all previous RDMA Read or Atomic WQEs on the
	/* Total Number of 2048-4095 Bytes frames transmitted */	* SQ before executing this WQE
	uint64_t tx_4096b_9216b_frames;	*/
	/* Total Number of 4096-9216 Bytes frames transmitted */	#define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
	uint64_t tx_9217b_16383b_frames;	/*
	/* Total Number of 9217-16383 Bytes frames transmitted */	* Unconditional fence. Indicate to complete all previous SQ's WQEs
	uint64_t tx_good_frames;	* before executing this WQE.
	/* Total Number of good frames transmitted */	*/
	uint64_t tx_total_frames;	#define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE UINT32_C(0x4)
	/* Total Number of frames transmitted */	/*
	uint64_t tx_ucast_frames;	* Solicit event. Indication sent in BTH header to the receiver to
	/* Total number of unicast frames transmitted */	* generate a Completion Event Notification, i.e. CNQE. This bit should
	uint64_t tx_mcast_frames;	* be set only in the last (or only) packet of the message.
	/* Total number of multicast frames transmitted */	*/
	uint64_t tx_bcast_frames;	#define SQ_LOCALINVALIDATE_FLAGS_SE UINT32_C(0x8)
	/* Total number of broadcast frames transmitted */	/* NA for this WQE */
	uint64_t tx_pause_frames;	#define SQ_LOCALINVALIDATE_FLAGS_INLINE UINT32_C(0x10)
	/* Total number of PAUSE control frames transmitted */	uint16_t reserved16;
	uint64_t tx_pfc_frames;	uint32_t inv_l_key;
	/* Total number of PFC/per-priority PAUSE control frames transmitted */	/*
	uint64_t tx_jabber_frames;	* The local key for the MR/W to invalidate; 24 msb of the key are used
	/* Total number of jabber frames transmitted */	* to index the MRW table, 8 lsb are compared with the 8 bit key in the
	uint64_t tx_fcs_err_frames;	* MRWC
	/* Total number of frames transmitted with FCS error */	*/
	uint64_t tx_control_frames;	uint64_t reserved64;
	/* Total number of control frames transmitted */	uint32_t reserved128[4];
	uint64_t tx_oversz_frames;	uint32_t data[24];
	/* Total number of over-sized frames transmitted */	/* The data field for local invalidate is not used. */
	uint64_t tx_single_dfrl_frames;
	/* Total number of frames with single deferral */
	uint64_t tx_multi_dfrl_frames;
	/* Total number of frames with multiple deferrals */
	uint64_t tx_single_coll_frames;
	/* Total number of frames with single collision */
	uint64_t tx_multi_coll_frames;
	/* Total number of frames with multiple collisions */
	uint64_t tx_late_coll_frames;
	/* Total number of frames with late collisions */
	uint64_t tx_excessive_coll_frames;
	/* Total number of frames with excessive collisions */
	uint64_t tx_frag_frames;
	/* Total number of fragmented frames transmitted */
	uint64_t tx_err;
	/* Total number of transmit errors */
	uint64_t tx_tagged_frames;
	/* Total number of single VLAN tagged frames transmitted */
	uint64_t tx_dbl_tagged_frames;
	/* Total number of double VLAN tagged frames transmitted */
	uint64_t tx_runt_frames;
	/* Total number of runt frames transmitted */
	uint64_t tx_fifo_underruns;
	/* Total number of TX FIFO under runs */
	uint64_t tx_pfc_ena_frames_pri0;
	/* Total number of PFC frames with PFC enabled bit for Pri 0 transmitted */
	uint64_t tx_pfc_ena_frames_pri1;
	/* Total number of PFC frames with PFC enabled bit for Pri 1 transmitted */
	uint64_t tx_pfc_ena_frames_pri2;
	/* Total number of PFC frames with PFC enabled bit for Pri 2 transmitted */
	uint64_t tx_pfc_ena_frames_pri3;
	/* Total number of PFC frames with PFC enabled bit for Pri 3 transmitted */
	uint64_t tx_pfc_ena_frames_pri4;
	/* Total number of PFC frames with PFC enabled bit for Pri 4 transmitted */
	uint64_t tx_pfc_ena_frames_pri5;
	/* Total number of PFC frames with PFC enabled bit for Pri 5 transmitted */
	uint64_t tx_pfc_ena_frames_pri6;
	/* Total number of PFC frames with PFC enabled bit for Pri 6 transmitted */
	uint64_t tx_pfc_ena_frames_pri7;
	/* Total number of PFC frames with PFC enabled bit for Pri 7 transmitted */
	uint64_t tx_eee_lpi_events;
	/* Total number of EEE LPI Events on TX */
	uint64_t tx_eee_lpi_duration;
	/* EEE LPI Duration Counter on TX */
	uint64_t tx_llfc_logical_msgs;
	/* Total number of Link Level Flow Control (LLFC) messages transmitted */
	uint64_t tx_hcfc_msgs;
	/* Total number of HCFC messages transmitted */
	uint64_t tx_total_collisions;
	/* Total number of TX collisions */
	uint64_t tx_bytes;
	/* Total number of transmitted bytes */
	uint64_t tx_xthol_frames;
	/* Total number of end-to-end HOL frames */
	uint64_t tx_stat_discard;
	/* Total Tx Drops per Port reported by STATS block */
	uint64_t tx_stat_error;
	/* Total Tx Error Drops per Port reported by STATS block */
	} __attribute__((packed));	} __attribute__((packed));

	/* Port Rx Statistics Formats (528 bytes) */	/* FR-PMR SQ WQE (40 bytes) */

	struct rx_port_stats {	struct sq_fr_pmr {
	uint64_t rx_64b_frames;	uint8_t wqe_type;
	/* Total Number of 64 Bytes frames received */	/* This field defines the type of SQ WQE. */
	uint64_t rx_65b_127b_frames;
	/* Total Number of 65-127 Bytes frames received */
	uint64_t rx_128b_255b_frames;
	/* Total Number of 128-255 Bytes frames received */
	uint64_t rx_256b_511b_frames;
	/* Total Number of 256-511 Bytes frames received */
	uint64_t rx_512b_1023b_frames;
	/* Total Number of 512-1023 Bytes frames received */
	uint64_t rx_1024b_1518_frames;
	/* Total Number of 1024-1518 Bytes frames received */
	uint64_t rx_good_vlan_frames;
	/*	/*
	* Total Number of each good VLAN (exludes FCS errors) frame received	* FR-PMR (Fast Register Physical Memory Region) Allowed only on
	* which is 1519 to 1522 bytes in length inclusive (excluding framing	* reliable connection (RC) SQ's.
	* bits but including FCS bytes).
	*/	*/
	uint64_t rx_1519b_2047b_frames;	#define SQ_FR_PMR_WQE_TYPE_FR_PMR UINT32_C(0xd)
	/* Total Number of 1519-2047 Bytes frames received */	uint8_t flags;
	uint64_t rx_2048b_4095b_frames;
	/* Total Number of 2048-4095 Bytes frames received */
	uint64_t rx_4096b_9216b_frames;
	/* Total Number of 4096-9216 Bytes frames received */
	uint64_t rx_9217b_16383b_frames;
	/* Total Number of 9217-16383 Bytes frames received */
	uint64_t rx_total_frames;
	/* Total number of frames received */
	uint64_t rx_ucast_frames;
	/* Total number of unicast frames received */
	uint64_t rx_mcast_frames;
	/* Total number of multicast frames received */
	uint64_t rx_bcast_frames;
	/* Total number of broadcast frames received */
	uint64_t rx_fcs_err_frames;
	/* Total number of received frames with FCS error */
	uint64_t rx_ctrl_frames;
	/* Total number of control frames received */
	uint64_t rx_pause_frames;
	/* Total number of PAUSE frames received */
	uint64_t rx_pfc_frames;
	/* Total number of PFC frames received */
	uint64_t rx_unsupported_opcode_frames;
	/* Total number of frames received with an unsupported opcode */
	uint64_t rx_unsupported_da_pausepfc_frames;
	/*	/*
	* Total number of frames received with an unsupported DA for pause and	* Set if completion signaling is requested. If this bit is 0, and the
	* PFC	* SQ is configured to support Unsignaled completion the controller
		* should not generate a CQE unless there was an error. This refer to
		* CQE on the sender side (se_flag refer to the receiver side)
	*/	*/
	uint64_t rx_wrong_sa_frames;	#define SQ_FR_PMR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
	/* Total number of frames received with an unsupported SA */
	uint64_t rx_align_err_frames;
	/* Total number of received packets with alignment error */
	uint64_t rx_oor_len_frames;
	/* Total number of received frames with out-of-range length */
	uint64_t rx_code_err_frames;
	/* Total number of received frames with error termination */
	uint64_t rx_false_carrier_frames;
	/*	/*
	* Total number of received frames with a false carrier is detected	* Indication to complete all previous RDMA Read or Atomic WQEs on the
	* during idle, as defined by RX_ER samples active and RXD is 0xE. The	* SQ before executing this WQE
	* event is reported along with the statistics generated on the next
	* received frame. Only one false carrier condition can be detected and
	* logged between frames. Carrier event, valid for 10M/100M speed modes
	* only.
	*/	*/
	uint64_t rx_ovrsz_frames;	#define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
	/* Total number of over-sized frames received */
	uint64_t rx_jbr_frames;
	/* Total number of jabber packets received */
	uint64_t rx_mtu_err_frames;
	/* Total number of received frames with MTU error */
	uint64_t rx_match_crc_frames;
	/* Total number of received frames with CRC match */
	uint64_t rx_promiscuous_frames;
	/* Total number of frames received promiscuously */
	uint64_t rx_tagged_frames;
	/* Total number of received frames with one or two VLAN tags */
	uint64_t rx_double_tagged_frames;
	/* Total number of received frames with two VLAN tags */
	uint64_t rx_trunc_frames;
	/* Total number of truncated frames received */
	uint64_t rx_good_frames;
	/* Total number of good frames (without errors) received */
	uint64_t rx_pfc_xon2xoff_frames_pri0;
	/*	/*
	* Total number of received PFC frames with transition from XON to XOFF	* Unconditional fence. Indicate to complete all previous SQ's WQEs
	* on Pri 0	* before executing this WQE.
	*/	*/
	uint64_t rx_pfc_xon2xoff_frames_pri1;	#define SQ_FR_PMR_FLAGS_UC_FENCE UINT32_C(0x4)
		/* Not Applicable for FR_PMR. Nothing is sent */
		#define SQ_FR_PMR_FLAGS_SE UINT32_C(0x8)
		/* NA. */
		#define SQ_FR_PMR_FLAGS_INLINE UINT32_C(0x10)
		uint8_t access_cntl;
	/*	/*
	* Total number of received PFC frames with transition from XON to XOFF	* This is the new access control for the MR. '1' means the operation is
	* on Pri 1	* allowed. '0' means operation is not allowed.
	*/	*/
	uint64_t rx_pfc_xon2xoff_frames_pri2;	/* Local Write Access */
		#define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
		/* Remote Read Access */
		#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
		/* Remote Write Access */
		#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
		/* Remote Atomic Access */
		#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
		/* Window Binding Allowed */
		#define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
		uint8_t zero_based_page_size_log;
		/* 0 for 4KB page size, ... to 8GB */
		#define SQ_FR_PMR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
		#define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0
		/* Page size is 4KB. */
		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
		/* Page size is 8KB. */
		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
		/* Page size is 64KB. */
		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
		/* Page size is 256KB. */
		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
		/* Page size is 1MB. */
		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
		/* Page size is 2MB. */
		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
		/* Page size is 4MB. */
		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
		/* Page size is 1GB. */
		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
		/* Indicate the MR is ZBVA (Zero Base VA) */
		#define SQ_FR_PMR_ZERO_BASED UINT32_C(0x20)
		#define SQ_FR_PMR_RESERVED2_MASK UINT32_C(0xc0)
		#define SQ_FR_PMR_RESERVED2_SFT 6
		uint32_t l_key;
	/*	/*
	* Total number of received PFC frames with transition from XON to XOFF	* Local Key; 24 msb of the key are used to index the MRW table, 8 lsb
	* on Pri 2	* are assigned to the 8 bit key_lsb field in the MRWC.
	*/	*/
	uint64_t rx_pfc_xon2xoff_frames_pri3;	uint8_t length[5];
		/* Length in bytes of registered MR */
		uint8_t reserved8_1;
		uint8_t reserved8_2;
		uint8_t numlevels_pbl_page_size_log;
		/* Number of levels of PBL for translation */
		/* PBL page size. 0 for 4KB page size. */
		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0
		/* Page size is 4KB. */
		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
		/* Page size is 8KB. */
		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
		/* Page size is 64KB. */
		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
		/* Page size is 256KB. */
		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
		/* Page size is 1MB. */
		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
		/* Page size is 2MB. */
		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
		/* Page size is 4MB. */
		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
		/* Page size is 1GB. */
		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
		#define SQ_FR_PMR_RESERVED1 UINT32_C(0x20)
		/* Number of levels of PBL for translation */
		#define SQ_FR_PMR_NUMLEVELS_MASK UINT32_C(0xc0)
		#define SQ_FR_PMR_NUMLEVELS_SFT 6
	/*	/*
	* Total number of received PFC frames with transition from XON to XOFF	* A zero level PBL means that the VA is the physical address
	* on Pri 3	* used for the operation. No translation is done by the PTU.
	*/	*/
	uint64_t rx_pfc_xon2xoff_frames_pri4;	#define SQ_FR_PMR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6)
	/*	/*
	* Total number of received PFC frames with transition from XON to XOFF	* A one layer translation is provided between the logical and
	* on Pri 4	* physical address. The PBL points to a physical page that
		* contains PBE values that point to actual pg_size physical
		* pages.
	*/	*/
	uint64_t rx_pfc_xon2xoff_frames_pri5;	#define SQ_FR_PMR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6)
	/*	/*
	* Total number of received PFC frames with transition from XON to XOFF	* A two layer translation is provided between the logical and
	* on Pri 5	* physical address. The PBL points to a physical page that
		* contains PDE values that in turn point to pbl_pg_size
		* physical pages that contain PBE values that point to actual
		* physical pages.
	*/	*/
	uint64_t rx_pfc_xon2xoff_frames_pri6;	#define SQ_FR_PMR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6)
		uint64_t pblptr;
		/* Pointer to the PBL, or PDL depending on number of levels */
		uint64_t va;
		/* Local Virtual Address */
		uint32_t data[24];
		/* The data field for FR-PRM is not used. */
		} __attribute__((packed));

		/* Bind SQ WQE (40 bytes) */

		struct sq_bind {
		uint8_t wqe_type;
		/* This field defines the type of SQ WQE. */
		/* Memory Bind Allowed only on reliable connection (RC) SQ's. */
		#define SQ_BIND_WQE_TYPE_BIND UINT32_C(0xe)
		uint8_t flags;
	/*	/*
	* Total number of received PFC frames with transition from XON to XOFF	* Set if completion signaling is requested. If this bit is 0, and the
	* on Pri 6	* SQ is configured to support Unsignaled completion the controller
		* should not generate a CQE unless there was an error. This refer to
		* CQE on the sender side (se_flag refer to the receiver side)
	*/	*/
	uint64_t rx_pfc_xon2xoff_frames_pri7;	#define SQ_BIND_FLAGS_SIGNAL_COMP UINT32_C(0x1)
	/*	/*
	* Total number of received PFC frames with transition from XON to XOFF	* Indication to complete all previous RDMA Read or Atomic WQEs on the
	* on Pri 7	* SQ before executing this WQE
	*/	*/
	uint64_t rx_pfc_ena_frames_pri0;	#define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
	/* Total number of received PFC frames with PFC enabled bit for Pri 0 */
	uint64_t rx_pfc_ena_frames_pri1;
	/* Total number of received PFC frames with PFC enabled bit for Pri 1 */
	uint64_t rx_pfc_ena_frames_pri2;
	/* Total number of received PFC frames with PFC enabled bit for Pri 2 */
	uint64_t rx_pfc_ena_frames_pri3;
	/* Total number of received PFC frames with PFC enabled bit for Pri 3 */
	uint64_t rx_pfc_ena_frames_pri4;
	/* Total number of received PFC frames with PFC enabled bit for Pri 4 */
	uint64_t rx_pfc_ena_frames_pri5;
	/* Total number of received PFC frames with PFC enabled bit for Pri 5 */
	uint64_t rx_pfc_ena_frames_pri6;
	/* Total number of received PFC frames with PFC enabled bit for Pri 6 */
	uint64_t rx_pfc_ena_frames_pri7;
	/* Total number of received PFC frames with PFC enabled bit for Pri 7 */
	uint64_t rx_sch_crc_err_frames;
	/* Total Number of frames received with SCH CRC error */
	uint64_t rx_undrsz_frames;
	/* Total Number of under-sized frames received */
	uint64_t rx_frag_frames;
	/* Total Number of fragmented frames received */
	uint64_t rx_eee_lpi_events;
	/* Total number of RX EEE LPI Events */
	uint64_t rx_eee_lpi_duration;
	/* EEE LPI Duration Counter on RX */
	uint64_t rx_llfc_physical_msgs;
	/*	/*
	* Total number of physical type Link Level Flow Control (LLFC) messages	* Unconditional fence. Indicate to complete all previous SQ's WQEs
	* received	* before executing this WQE.
	*/	*/
	uint64_t rx_llfc_logical_msgs;	#define SQ_BIND_FLAGS_UC_FENCE UINT32_C(0x4)
		/* NA, nothing is sent. */
		#define SQ_BIND_FLAGS_SE UINT32_C(0x8)
		/* NA */
		#define SQ_BIND_FLAGS_INLINE UINT32_C(0x10)
		uint8_t access_cntl;
	/*	/*
	* Total number of logical type Link Level Flow Control (LLFC) messages	* This is the new access control for the MR. '1' means the operation is
	* received	* allowed. '0' means operation is not allowed.
	*/	*/
	uint64_t rx_llfc_msgs_with_crc_err;
	/*	/*
	* Total number of logical type Link Level Flow Control (LLFC) messages	* Local Write Access. Local accesses are never allowed for memory
	* received with CRC error	* windows, so this bit must always be zero in a bind WQE. If this bit
		* is ever set, the bind will fail with an errored completion.
	*/	*/
	uint64_t rx_hcfc_msgs;	#define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
	/* Total number of HCFC messages received */	/* Remote Read Access */
	uint64_t rx_hcfc_msgs_with_crc_err;	#define SQ_BIND_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
	/* Total number of HCFC messages received with CRC error */	/*
	uint64_t rx_bytes;	* Remote Write Access. Note that, if this bit is set, then the parent
	/* Total number of received bytes */	* region to which the window is being bound must allow local writes. If
	uint64_t rx_runt_bytes;	* this is not the case, then the bind will fail with an errored
	/* Total number of bytes received in runt frames */	* completion.
	uint64_t rx_runt_frames;	*/
	/* Total number of runt frames received */	#define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
	uint64_t rx_stat_discard;	/*
	/* Total Rx Discards per Port reported by STATS block */	* Remote Atomic Access. Note that, if this bit is set, then the parent
	uint64_t rx_stat_err;	* region to which the window is being bound must allow local writes. If
	/* Total Rx Error Drops per Port reported by STATS block */	* this is not the case, then the bind will fail with an errored
		* completion.
		*/
		#define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
		/*
		* Window Binding Allowed. It is never allowed to bind windows to
		* windows, so this bit must always be zero in a bind WQE. If this bit
		* is ever set, the bind will fail with an errored completion.
		*/
		#define SQ_BIND_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
		uint8_t reserved8_1;
		/* reserved8_1 is 8 b */
		uint8_t mw_type_zero_based;
		/*
		* If this bit is set, then the newly-bound memory window will be zero-
		* based. If clear, then the newly-bound memory window will be non-zero-
		* based.
		*/
		#define SQ_BIND_ZERO_BASED UINT32_C(0x1)
		/*
		* If type1 is specified, then this WQE performs a "bind memory window"
		* operation on a type1 window. If type2 is specified, then this WQE
		* performs a "post send bind memory window" operation on a type2
		* window. Note that the bind WQE cannot change the type of the memory
		* window. If a "bind memory window" operation is attempted on a memory
		* window that was allocated as type2, then the bind will fail with an
		* errored completion, as "bind memory window" is allowed only on type1
		* memory windows. Similarly, if a "post send bind memory window"
		* operation is attempted on a memory window that was allocated as
		* type1, then the bind will fail with an errored completions, as "post
		* send bind memory window" is allowed only on type2 memory windows.
		*/
		#define SQ_BIND_MW_TYPE UINT32_C(0x2)
		/* Type 1 Bind Memory Window */
		#define SQ_BIND_MW_TYPE_TYPE1 (UINT32_C(0x0) << 1)
		/* Type 2 Post Send Bind Memory Window */
		#define SQ_BIND_MW_TYPE_TYPE2 (UINT32_C(0x1) << 1)
		#define SQ_BIND_RESERVED6_MASK UINT32_C(0xfc)
		#define SQ_BIND_RESERVED6_SFT 2
		uint8_t reserved8_2;
		uint16_t reserved16;
		uint32_t parent_l_key;
		/*
		* The L_Key of the parent MR; 24 msb of the key are used to index the
		* MRW table, 8 lsb are compared with the 8 bit key in the MRWC.
		*/
		uint32_t l_key;
		/*
		* Local Key; 24 msb of the key are used to index the memory window
		* being bound in the MRW table, 8 lsb are assign to the 8 bit key_lsb
		* field in the MRWC.
		*/
		uint64_t va;
		/* Local Virtual Address */
		uint8_t length[5];
		/*
		* Length in bytes of registered MW; 40 bits as this is the max size of
		* an MR/W
		*/
		uint8_t data_reserved24[99];
		/* The data field for Bind is not used. */
		#define SQ_BIND_RESERVED24_MASK UINT32_C(0xffffff00)
		#define SQ_BIND_RESERVED24_SFT 8
		/* The data field for Bind is not used. */
		#define SQ_BIND_DATA_MASK UINT32_C(0xffffffff)
		#define SQ_BIND_DATA_SFT 0
	} __attribute__((packed));	} __attribute__((packed));

		/* RQ/SRQ WQE Structures */
		/* Description: This is the RQ/SRQ WQE structure. */
		/* RQ/SRQ WQE (40 bytes) */

		struct rq_wqe {
		uint8_t wqe_type;
		/* wqe_type is 8 b */
		/* RQ/SRQ WQE. This WQE is used for posting buffers on an RQ or SRQ. */
		#define RQ_WQE_WQE_TYPE_RCV UINT32_C(0x80)
		uint8_t flags;
		/* No flags supported for this WQE type. */
		uint8_t wqe_size;
		/*
		* Specify the total number 16B chunks that make up the valid portion of
		* the WQE. This includes the first chunk that is the WQE structure and
		* up to 6 SGE structures. While the valid area is defined by the
		* wqe_size field, the actual WQE size is fixed at 128B.
		*/
		uint8_t reserved8;
		uint32_t reserved32;
		uint64_t wr_id;
		/*
		* Opaque value used by upper layer SW to identify the id of the WR
		* which generated the WQE. Used in CQE. Valid in the first SGE of an
		* SRQ WQE.
		*/
		#define RQ_WQE_WR_ID_MASK UINT32_C(0xfffff)
		#define RQ_WQE_WR_ID_SFT 0
		#define RQ_WQE_RESERVED44_MASK UINT32_C(0xfff00000)
		#define RQ_WQE_RESERVED44_SFT 20
		uint32_t reserved128[4];
		uint32_t data[24];
		/*
		* The data field for RQ WQE is filled with from 1 to 6 SGE structures
		* as defined by the wqe_size field.
		*/
		} __attribute__((packed));

		/* CQ CQE Structures */
		/* Description: This is the Cutoff CQE structure. */
		/* Base CQE (32 bytes) */

		struct cq_base {
		uint64_t reserved64_1;
		uint64_t reserved64_2;
		uint64_t reserved64_3;
		uint8_t cqe_type_toggle;
		/*
		* Indicate valid completion - written by the chip. Cumulus toggle this
		* bit each time it finished consuming all PBL entries
		*/
		#define CQ_BASE_TOGGLE UINT32_C(0x1)
		/* This field defines the type of SQ WQE. */
		#define CQ_BASE_CQE_TYPE_MASK UINT32_C(0x1e)
		#define CQ_BASE_CQE_TYPE_SFT 1
		/*
		* Requester completion - This is used for both RC and UD SQ
		* completions.
		*/
		#define CQ_BASE_CQE_TYPE_REQ (UINT32_C(0x0) << 1)
		/*
		* Responder RC Completion - This is used for both RQ and SRQ
		* completions for RC service QPs.
		*/
		#define CQ_BASE_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1)
		/*
		* Responder UD Completion - This is used for both RQ and SRQ
		* completion for UD service QPs.
		*/
		#define CQ_BASE_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1)
		/*
		* Responder RawEth and QP1 Completion - This is used for RQ
		* completion for RawEth service and QP1 service QPs.
		*/
		#define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1)
		/*
		* Terminal completion - This is used to indicate that no
		* further completions will be made for this QP on this CQ.
		*/
		#define CQ_BASE_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1)
		/* Cut off CQE; for CQ resize see CQ and SRQ Resize */
		#define CQ_BASE_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1)
		#define CQ_BASE_RESERVED3_MASK UINT32_C(0xe0)
		#define CQ_BASE_RESERVED3_SFT 5
		uint8_t status;
		/* This field indicates the status for the CQE. */
		uint16_t reserved16;
		uint32_t reserved32;
		} __attribute__((packed));

		/* Requester CQ CQE (32 bytes) */

		struct cq_req {
		uint64_t qp_handle;
		/*
		* This is an application level ID used to identify the QP and its SQ
		* and RQ.
		*/
		uint16_t sq_cons_idx;
		/*
		* SQ Consumer Index - points to the entry just past the last WQE that
		* has been completed by the chip. Wraps around at QPC.sq_size (i.e. the
		* valid range of the SQ Consumer Index is 0 to (QPC.sq_size - 1)).
		*/
		uint16_t reserved16_1;
		uint32_t reserved32_2;
		uint64_t reserved64;
		uint8_t cqe_type_toggle;
		/*
		* Indicate valid completion - written by the chip. Cumulus toggle this
		* bit each time it finished consuming all PBL entries
		*/
		#define CQ_REQ_TOGGLE UINT32_C(0x1)
		/* This field defines the type of SQ WQE. */
		#define CQ_REQ_CQE_TYPE_MASK UINT32_C(0x1e)
		#define CQ_REQ_CQE_TYPE_SFT 1
		/*
		* Requester completion - This is used for both RC and UD SQ
		* completions.
		*/
		#define CQ_REQ_CQE_TYPE_REQ (UINT32_C(0x0) << 1)
		#define CQ_REQ_RESERVED3_MASK UINT32_C(0xe0)
		#define CQ_REQ_RESERVED3_SFT 5
		uint8_t status;
		/* This field indicates the status for the CQE. */
		/* OK is 0 */
		#define CQ_REQ_STATUS_OK UINT32_C(0x0)
		/* BAD_RESPONSE_ERR is 1 */
		#define CQ_REQ_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1)
		/* LOCAL_LENGTH_ERR is 2 */
		#define CQ_REQ_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
		/* LOCAL_QP_OPERATION_ERR is 3 */
		#define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x3)
		/* LOCAL_PROTECTION_ERR is 4 */
		#define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x4)
		/* MEMORY_MGT_OPERATION_ERR is 5 */
		#define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
		/* REMOTE_INVALID_REQUEST_ERR is 6 */
		#define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6)
		/* REMOTE_ACCESS_ERR is 7 */
		#define CQ_REQ_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x7)
		/* REMOTE_OPERATION_ERR is 8 */
		#define CQ_REQ_STATUS_REMOTE_OPERATION_ERR UINT32_C(0x8)
		/* RNR_NAK_RETRY_CNT_ERR is 9 */
		#define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0x9)
		/* TRANSPORT_RETRY_CNT_ERR is 10 */
		#define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xa)
		/* WORK_REQUEST_FLUSHED_ERR is 11 */
		#define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xb)
		uint16_t reserved16_2;
		uint32_t reserved32_1;
		} __attribute__((packed));

		/* Responder RC CQE (32 bytes) */

		struct cq_res_rc {
		uint32_t length;
		/* The length of the message's payload in bytes, stored in the SGEs */
		uint32_t imm_data_or_inv_r_key;
		/*
		* Immediate data in case the imm_flag set, R_Key to be invalidated in
		* case inv_flag is set.
		*/
		uint64_t qp_handle;
		/*
		* This is an application level ID used to identify the QP and its SQ
		* and RQ.
		*/
		uint64_t mr_handle;
		/*
		* Opaque value - valid when inv_flag is set. Used by driver to
		* reference the buffer used to store PBL when the MR was fast
		* registered. The driver can reclaim this buffer after an MR was
		* remotely invalidated. The controller take that value from the MR
		* referenced by R_Key
		*/
		uint8_t cqe_type_toggle;
		/*
		* Indicate valid completion - written by the chip. Cumulus toggle this
		* bit each time it finished consuming all PBL entries
		*/
		#define CQ_RES_RC_TOGGLE UINT32_C(0x1)
		/* This field defines the type of SQ WQE. */
		#define CQ_RES_RC_CQE_TYPE_MASK UINT32_C(0x1e)
		#define CQ_RES_RC_CQE_TYPE_SFT 1
		/*
		* Responder RC Completion - This is used for both RQ and SRQ
		* completions for RC service QPs.
		*/
		#define CQ_RES_RC_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1)
		#define CQ_RES_RC_RESERVED3_MASK UINT32_C(0xe0)
		#define CQ_RES_RC_RESERVED3_SFT 5
		uint8_t status;
		/* This field indicates the status for the CQE. */
		/* OK is 0 */
		#define CQ_RES_RC_STATUS_OK UINT32_C(0x0)
		/* LOCAL_ACCESS_ERROR is 1 */
		#define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
		/* LOCAL_LENGTH_ERR is 2 */
		#define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
		/* LOCAL_PROTECTION_ERR is 3 */
		#define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
		/* LOCAL_QP_OPERATION_ERR is 4 */
		#define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
		/* MEMORY_MGT_OPERATION_ERR is 5 */
		#define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
		/* REMOTE_INVALID_REQUEST_ERR is 6 */
		#define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6)
		/* WORK_REQUEST_FLUSHED_ERR is 7 */
		#define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
		/* HW_FLUSH_ERR is 8 */
		#define CQ_RES_RC_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
		uint16_t flags;
		/*
		* This flag indicates that the completion is for a SRQ entry rather
		* than for an RQ entry.
		*/
		#define CQ_RES_RC_FLAGS_SRQ UINT32_C(0x1)
		/* CQE relates to RQ WQE. */
		#define CQ_RES_RC_FLAGS_SRQ_RQ (UINT32_C(0x0) << 0)
		/* CQE relates to SRQ WQE. */
		#define CQ_RES_RC_FLAGS_SRQ_SRQ (UINT32_C(0x1) << 0)
		#define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ
		/* Immediate data indicator */
		#define CQ_RES_RC_FLAGS_IMM UINT32_C(0x2)
		/* R_Key invalidate indicator */
		#define CQ_RES_RC_FLAGS_INV UINT32_C(0x4)
		#define CQ_RES_RC_FLAGS_RDMA UINT32_C(0x8)
		/* CQE relates to an incoming Send request */
		#define CQ_RES_RC_FLAGS_RDMA_SEND (UINT32_C(0x0) << 3)
		/* CQE relates to incoming RDMA Write request */
		#define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (UINT32_C(0x1) << 3)
		#define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE
		uint32_t srq_or_rq_wr_id;
		/*
		* Opaque value from RQ or SRQ WQE. Used by driver/lib to reference the
		* WQE in order to claim the received data and reuse the WQE space
		*/
		#define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
		#define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0
		#define CQ_RES_RC_RESERVED12_MASK UINT32_C(0xfff00000)
		#define CQ_RES_RC_RESERVED12_SFT 20
		} __attribute__((packed));

		/* Responder UD CQE (32 bytes) */

		struct cq_res_ud {
		uint32_t length;
		/* The length of the message's payload in bytes, stored in the SGEs */
		#define CQ_RES_UD_LENGTH_MASK UINT32_C(0x3fff)
		#define CQ_RES_UD_LENGTH_SFT 0
		#define CQ_RES_UD_RESERVED18_MASK UINT32_C(0xffffc000)
		#define CQ_RES_UD_RESERVED18_SFT 14
		uint32_t imm_data;
		/* Immediate data in case the imm_flag set. */
		uint64_t qp_handle;
		/*
		* This is an application level ID used to identify the QP and its SQ
		* and RQ.
		*/
		uint16_t src_mac[3];
		/*
		* Source MAC address for the UD message placed in the WQE that is
		* completed by this CQE.
		*/
		uint16_t src_qp_low;
		/* Lower 16b of the Source QP value from the DETH header. */
		uint8_t cqe_type_toggle;
		/*
		* Indicate valid completion - written by the chip. Cumulus toggle this
		* bit each time it finished consuming all PBL entries
		*/
		#define CQ_RES_UD_TOGGLE UINT32_C(0x1)
		/* This field defines the type of SQ WQE. */
		#define CQ_RES_UD_CQE_TYPE_MASK UINT32_C(0x1e)
		#define CQ_RES_UD_CQE_TYPE_SFT 1
		/*
		* Responder UD Completion - This is used for both RQ and SRQ
		* completion for UD service QPs.
		*/
		#define CQ_RES_UD_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1)
		#define CQ_RES_UD_RESERVED3_MASK UINT32_C(0xe0)
		#define CQ_RES_UD_RESERVED3_SFT 5
		uint8_t status;
		/* This field indicates the status for the CQE. */
		/*
		* This indicates that the completion is without error. All
		* fields are valid.
		*/
		#define CQ_RES_UD_STATUS_OK UINT32_C(0x0)
		/*
		* This indicates that write access was not allowed for at least
		* one of the SGEs in the WQE. This is a fatal error. Only the
		* srq_or_rq_wr_id is field is valid.
		*/
		#define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
		/*
		* This indicates that the packet was too long for the WQE
		* provided on the SRQ/RQ. This is not a fatal error. All the
		* fields are valid.
		*/
		#define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
		/* LOCAL_PROTECTION_ERR is 3 */
		#define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
		/* LOCAL_QP_OPERATION_ERR is 4 */
		#define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
		/* MEMORY_MGT_OPERATION_ERR is 5 */
		#define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
		/* WORK_REQUEST_FLUSHED_ERR is 7 */
		#define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
		/* HW_FLUSH_ERR is 8 */
		#define CQ_RES_UD_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
		uint16_t flags;
		/*
		* This flag indicates that the completion is for a SRQ entry rather
		* than for an RQ entry.
		*/
		#define CQ_RES_UD_FLAGS_SRQ UINT32_C(0x1)
		/* CQE relates to RQ WQE. */
		#define CQ_RES_UD_FLAGS_SRQ_RQ (UINT32_C(0x0) << 0)
		/* CQE relates to SRQ WQE. */
		#define CQ_RES_UD_FLAGS_SRQ_SRQ (UINT32_C(0x1) << 0)
		#define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ
		/* Immediate data indicator */
		#define CQ_RES_UD_FLAGS_IMM UINT32_C(0x2)
		#define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK UINT32_C(0xc)
		#define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 2
		/* RoCEv1 Message */
		#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 2)
		/* RoCEv2 IPv4 Message */
		#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 2)
		/* RoCEv2 IPv6 Message */
		#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 2)
		#define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6
		uint32_t src_qp_high_srq_or_rq_wr_id;
		/* Upper 8b of the Source QP value from the DETH header. */
		/*
		* Opaque value from RQ or SRQ WQE. Used by driver/lib to reference the
		* WQE in order to claim the received data and reuse the WQE space
		*/
		#define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
		#define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0
		#define CQ_RES_UD_RESERVED4_MASK UINT32_C(0xf00000)
		#define CQ_RES_UD_RESERVED4_SFT 20
		/* Upper 8b of the Source QP value from the DETH header. */
		#define CQ_RES_UD_SRC_QP_HIGH_MASK UINT32_C(0xff000000)
		#define CQ_RES_UD_SRC_QP_HIGH_SFT 24
		} __attribute__((packed));

		/* Responder RawEth and QP1 CQE (32 bytes) */

		struct cq_res_raweth_qp1 {
		uint16_t length;
		/* The length of the message's payload in bytes, stored in the SGEs */
		#define CQ_RES_RAWETH_QP1_LENGTH_MASK UINT32_C(0x3fff)
		#define CQ_RES_RAWETH_QP1_LENGTH_SFT 0
		#define CQ_RES_RAWETH_QP1_RESERVED2_MASK UINT32_C(0xc000)
		#define CQ_RES_RAWETH_QP1_RESERVED2_SFT 14
		uint16_t raweth_qp1_flags;
		/*
		* When this bit is '1', it indicates a packet that has an error of some
		* type. Type of error is indicated in raweth_qp1_errors.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR UINT32_C(0x1)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_MASK UINT32_C(0x3e)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_SFT 1
		/*
		* This value indicates what the inner packet determined for the packet
		* was.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK UINT32_C(0x3c0)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6
		/* Not Known: Indicates that the packet type was not known. */
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6)
		/*
		* IP Packet: Indicates that the packet was an IP packet, but
		* further classification was not possible.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (UINT32_C(0x1) << 6)
		/*
		* TCP Packet: Indicates that the packet was IP and TCP. This
		* indicates that the raweth_qp1_payload_offset field is valid.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 6)
		/*
		* UDP Packet: Indicates that the packet was IP and UDP. This
		* indicates that the raweth_qp1_payload_offset field is valid.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 6)
		/*
		* FCoE Packet: Indicates that the packet was recognized as a
		* FCoE. This also indicates that the raweth_qp1_payload_offset
		* field is valid.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 6)
		/*
		* RoCE Packet: Indicates that the packet was recognized as a
		* RoCE. This also indicates that the raweth_qp1_payload_offset
		* field is valid.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 6)
		/*
		* ICMP Packet: Indicates that the packet was recognized as
		* ICMP. This indicates that the raweth_qp1_payload_offset field
		* is valid.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 6)
		/*
		* PtP packet wo/timestamp: Indicates that the packet was
		* recognized as a PtP packet.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6)
		/*
		* PtP packet w/timestamp: Indicates that the packet was
		* recognized as a PtP packet and that a timestamp was taken for
		* the packet.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK UINT32_C(0x3ff)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0
		#define CQ_RES_RAWETH_QP1_RESERVED6_MASK UINT32_C(0xfc00)
		#define CQ_RES_RAWETH_QP1_RESERVED6_SFT 10
		uint16_t raweth_qp1_errors;
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_MASK UINT32_C(0xf)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_SFT 0
		/* This indicates that there was an error in the IP header checksum. */
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10)
		/*
		* This indicates that there was an error in the TCP, UDP or ICMP
		* checksum.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20)
		/*
		* This indicates that there was an error in the tunnel IP header
		* checksum.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
		/* This indicates that there was an error in the tunnel UDP checksum. */
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
		/*
		* This indicates that there was a CRC error on either an FCoE or RoCE
		* packet. The itype indicates the packet type.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100)
		/*
		* This indicates that there was an error in the tunnel portion of the
		* packet when this field is non-zero.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
		/*
		* No additional error occurred on the tunnel portion of the
		* packet of the packet does not have a tunnel.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
		/*
		* Indicates that IP header version does not match expectation
		* from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
		/*
		* Indicates that header length is out of range in the tunnel
		* header. Valid for IPv4.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
		/*
		* Indicates that the physical packet is shorter than that
		* claimed by the PPPoE header length for a tunnel PPPoE packet.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9)
		/*
		* Indicates that physical packet is shorter than that claimed
		* by the tunnel l3 header length. Valid for IPv4, or IPv6
		* tunnel packet packets.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9)
		/*
		* Indicates that the physical packet is shorter than that
		* claimed by the tunnel UDP header length for a tunnel UDP
		* packet that is not fragmented.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9)
		/*
		* indicates that the IPv4 TTL or IPv6 hop limit check have
		* failed (e.g. TTL = 0) in the tunnel header. Valid for IPv4,
		* and IPv6.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
		/*
		* This indicates that there was an error in the inner portion of the
		* packet when this field is non-zero.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12
		/*
		* No additional error occurred on the tunnel portion of the
		* packet of the packet does not have a tunnel.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
		/*
		* Indicates that IP header version does not match expectation
		* from L2 Ethertype for IPv4 and IPv6 or that option other than
		* VFT was parsed on FCoE packet.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
		/*
		* indicates that header length is out of range. Valid for IPv4
		* and RoCE
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
		/*
		* indicates that the IPv4 TTL or IPv6 hop limit check have
		* failed (e.g. TTL = 0). Valid for IPv4, and IPv6
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
		/*
		* Indicates that physical packet is shorter than that claimed
		* by the l3 header length. Valid for IPv4, IPv6 packet or RoCE
		* packets.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
		/*
		* Indicates that the physical packet is shorter than that
		* claimed by the UDP header length for a UDP packet that is not
		* fragmented.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
		/*
		* Indicates that TCP header length > IP payload. Valid for TCP
		* packets only.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
		/* Indicates that TCP header length < 5. Valid for TCP. */
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12)
		/*
		* Indicates that TCP option headers result in a TCP header size
		* that does not match data offset in TCP header. Valid for TCP.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
		uint16_t raweth_qp1_cfa_code;
		/*
		* This field identifies the CFA action rule that was used for this
		* packet.
		*/
		uint64_t qp_handle;
		/*
		* This is an application level ID used to identify the QP and its SQ
		* and RQ.
		*/
		uint32_t raweth_qp1_flags2;
		/*
		* This indicates that the ip checksum was calculated for the inner
		* packet and that the ip_cs_error field indicates if there was an
		* error.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC UINT32_C(0x1)
		/*
		* This indicates that the TCP, UDP or ICMP checksum was calculated for
		* the inner packet and that the l4_cs_error field indicates if there
		* was an error.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC UINT32_C(0x2)
		/*
		* This indicates that the ip checksum was calculated for the tunnel
		* header and that the t_ip_cs_error field indicates if there was an
		* error.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
		/*
		* This indicates that the UDP checksum was calculated for the tunnel
		* packet and that the t_l4_cs_error field indicates if there was an
		* error.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
		/* This value indicates what format the raweth_qp1_metadata field is. */
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
		/* No metadata information. Value is zero. */
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
		/*
		* The raweth_qp1_metadata field contains the VLAN tag and TPID
		* value. - raweth_qp1_metadata[11:0] contains the vlan VID
		* value. - raweth_qp1_metadata[12] contains the vlan DE value.
		* - raweth_qp1_metadata[15:13] contains the vlan PRI value. -
		* raweth_qp1_metadata[31:16] contains the vlan TPID value.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN
		/*
		* This field indicates the IP type for the inner-most IP header. A
		* value of '0' indicates IPv4. A value of '1' indicates IPv6. This
		* value is only valid if itype indicates a packet with an IP header.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100)
		uint32_t raweth_qp1_metadata;
		/*
		* This is data from the CFA block as indicated by the meta_format
		* field.
		*/
		/* When meta_format=1, this value is the VLAN VID. */
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK UINT32_C(0xfff)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0
		/* When meta_format=1, this value is the VLAN DE. */
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE UINT32_C(0x1000)
		/* When meta_format=1, this value is the VLAN PRI. */
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK UINT32_C(0xe000)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13
		/* When meta_format=1, this value is the VLAN TPID. */
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK UINT32_C(0xffff0000)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16
		uint8_t cqe_type_toggle;
		/*
		* Indicate valid completion - written by the chip. Cumulus toggle this
		* bit each time it finished consuming all PBL entries
		*/
		#define CQ_RES_RAWETH_QP1_TOGGLE UINT32_C(0x1)
		/* This field defines the type of SQ WQE. */
		#define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK UINT32_C(0x1e)
		#define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1
		/*
		* Responder RawEth and QP1 Completion - This is used for RQ
		* completion for RawEth service and QP1 service QPs.
		*/
		#define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1)
		#define CQ_RES_RAWETH_QP1_RESERVED3_MASK UINT32_C(0xe0)
		#define CQ_RES_RAWETH_QP1_RESERVED3_SFT 5
		uint8_t status;
		/* This field indicates the status for the CQE. */
		/*
		* This indicates that the completion is without error. All
		* fields are valid.
		*/
		#define CQ_RES_RAWETH_QP1_STATUS_OK UINT32_C(0x0)
		/*
		* This indicates that write access was not allowed for at least
		* one of the SGEs in the WQE. This is a fatal error. Only the
		* srq_or_rq_wr_id is field is valid.
		*/
		#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
		/*
		* This indicates that the packet was too long for the WQE
		* provided on the RQ. This is not a fatal error. All the fields
		* are valid.
		*/
		#define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
		/* LOCAL_PROTECTION_ERR is 3 */
		#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
		/* LOCAL_QP_OPERATION_ERR is 4 */
		#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
		/* MEMORY_MGT_OPERATION_ERR is 5 */
		#define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
		/* WORK_REQUEST_FLUSHED_ERR is 7 */
		#define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
		/* HW_FLUSH_ERR is 8 */
		#define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
		uint16_t flags;
		/*
		* This flag indicates that the completion is for a SRQ entry rather
		* than for an RQ entry.
		*/
		#define CQ_RES_RAWETH_QP1_FLAGS_SRQ UINT32_C(0x1)
		/* CQE relates to RQ WQE. */
		#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ UINT32_C(0x0)
		/* CQE relates to SRQ WQE. */
		#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ UINT32_C(0x1)
		#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ
		uint32_t raweth_qp1_payload_offset_srq_or_rq_wr_id;
		/*
		* This value indicates the offset in bytes from the beginning of the
		* packet where the inner payload starts. This value is valid for TCP,
		* UDP, FCoE, and RoCE packets. A value of zero indicates an offset of
		* 256 bytes.
		*/
		/*
		* Opaque value from RQ or SRQ WQE. Used by driver/lib to reference the
		* WQE in order to claim the received data and reuse the WQE space
		*/
		#define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
		#define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0
		#define CQ_RES_RAWETH_QP1_RESERVED4_MASK UINT32_C(0xf00000)
		#define CQ_RES_RAWETH_QP1_RESERVED4_SFT 20
		/*
		* This value indicates the offset in bytes from the beginning of the
		* packet where the inner payload starts. This value is valid for TCP,
		* UDP, FCoE, and RoCE packets. A value of zero indicates an offset of
		* 256 bytes.
		*/
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000)
		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24
		} __attribute__((packed));

		/* Terminal CQE (32 bytes) */

		struct cq_terminal {
		uint64_t qp_handle;
		/*
		* This is an application level ID used to identify the QP and its SQ
		* and RQ.
		*/
		uint16_t sq_cons_idx;
		/*
		* Final SQ Consumer Index value. Any additional SQ WQEs will have to be
		* completed by the user provider.
		*/
		uint16_t rq_cons_idx;
		/*
		* Final RQ Consumer Index value. Any additional RQ WQEs will have to be
		* completed by the user provider.
		*/
		uint32_t reserved32_1;
		uint64_t reserved64_3;
		uint8_t cqe_type_toggle;
		/*
		* Indicate valid completion - written by the chip. Cumulus toggle this
		* bit each time it finished consuming all PBL entries
		*/
		#define CQ_TERMINAL_TOGGLE UINT32_C(0x1)
		/* This field defines the type of SQ WQE. */
		#define CQ_TERMINAL_CQE_TYPE_MASK UINT32_C(0x1e)
		#define CQ_TERMINAL_CQE_TYPE_SFT 1
		/*
		* Terminal completion - This is used to indicate that no
		* further completions will be made for this QP on this CQ.
		*/
		#define CQ_TERMINAL_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1)
		#define CQ_TERMINAL_RESERVED3_MASK UINT32_C(0xe0)
		#define CQ_TERMINAL_RESERVED3_SFT 5
		uint8_t status;
		/* This field indicates the status for the CQE. */
		/* OK is 0 */
		#define CQ_TERMINAL_STATUS_OK UINT32_C(0x0)
		uint16_t reserved16;
		uint32_t reserved32_2;
		} __attribute__((packed));

		/* Cutoff CQE (32 bytes) */

		struct cq_cutoff {
		uint64_t reserved64_1;
		uint64_t reserved64_2;
		uint64_t reserved64_3;
		uint8_t cqe_type_toggle;
		/*
		* Indicate valid completion - written by the chip. Cumulus toggle this
		* bit each time it finished consuming all PBL entries
		*/
		#define CQ_CUTOFF_TOGGLE UINT32_C(0x1)
		/* This field defines the type of SQ WQE. */
		#define CQ_CUTOFF_CQE_TYPE_MASK UINT32_C(0x1e)
		#define CQ_CUTOFF_CQE_TYPE_SFT 1
		/* Cut off CQE; for CQ resize see CQ and SRQ Resize */
		#define CQ_CUTOFF_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1)
		#define CQ_CUTOFF_RESERVED3_MASK UINT32_C(0xe0)
		#define CQ_CUTOFF_RESERVED3_SFT 5
		uint8_t status;
		/* This field indicates the status for the CQE. */
		/* OK is 0 */
		#define CQ_CUTOFF_STATUS_OK UINT32_C(0x0)
		uint16_t reserved16;
		uint32_t reserved32;
		} __attribute__((packed));

		/* Notification Queue (NQ) Structures */
		/*
		* Description: This completion indicates that the DBQ has reached the
		* programmed threshold value.
		*/
		/* Base NQ Record (16 bytes) */

		struct nq_base {
		uint16_t info10_type;
		/* info10 is 10 b */
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define NQ_BASE_TYPE_MASK UINT32_C(0x3f)
		#define NQ_BASE_TYPE_SFT 0
		/* CQ Notification */
		#define NQ_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
		/* SRQ Threshold Event */
		#define NQ_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
		/* DBQ Threshold Event */
		#define NQ_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
		/* QP Async Notification */
		#define NQ_BASE_TYPE_QP_EVENT UINT32_C(0x38)
		/* Function Async Notification */
		#define NQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
		/* info10 is 10 b */
		#define NQ_BASE_INFO10_MASK UINT32_C(0xffc0)
		#define NQ_BASE_INFO10_SFT 6
		uint16_t info16;
		/* info16 is 16 b */
		uint32_t info32;
		/* info32 is 32 b */
		uint64_t info63_v;
		/* info63 is 63 b */
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define NQ_BASE_V UINT32_C(0x1)
		/* info63 is 63 b */
		#define NQ_BASE_INFO63_MASK UINT32_C(0xfffffffe)
		#define NQ_BASE_INFO63_SFT 1
		} __attribute__((packed));

		/* Completion Queue Notification (16 bytes) */

		struct nq_cn {
		uint16_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define NQ_CN_TYPE_MASK UINT32_C(0x3f)
		#define NQ_CN_TYPE_SFT 0
		/* CQ Notification */
		#define NQ_CN_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
		#define NQ_CN_RESERVED9_MASK UINT32_C(0xffc0)
		#define NQ_CN_RESERVED9_SFT 6
		uint16_t reserved16;
		uint32_t cq_handle_low;
		/*
		* This is an application level ID used to identify the CQ. This field
		* carries the lower 32b of the value.
		*/
		uint32_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define NQ_CN_V UINT32_C(0x1)
		#define NQ_CN_RESERVED31_MASK UINT32_C(0xfffffffe)
		#define NQ_CN_RESERVED31_SFT 1
		uint32_t cq_handle_high;
		/*
		* This is an application level ID used to identify the CQ. This field
		* carries the upper 32b of the value.
		*/
		} __attribute__((packed));

		/* SRQ Event Notification (16 bytes) */

		struct nq_srq_event {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define NQ_SRQ_EVENT_TYPE_MASK UINT32_C(0x3f)
		#define NQ_SRQ_EVENT_TYPE_SFT 0
		/* SRQ Threshold Event */
		#define NQ_SRQ_EVENT_TYPE_SRQ_EVENT UINT32_C(0x32)
		#define NQ_SRQ_EVENT_RESERVED1_MASK UINT32_C(0xc0)
		#define NQ_SRQ_EVENT_RESERVED1_SFT 6
		uint8_t event;
		/* This value define what type of async event has occurred on the SRQ. */
		/* The threshold event has occurred on the specified SRQ. */
		#define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT UINT32_C(0x1)
		uint16_t reserved16;
		uint32_t srq_handle_low;
		/*
		* This is the SRQ handle value for the queue that has reached it's
		* event threshold. This field carries the lower 32b of the value.
		*/
		uint32_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define NQ_SRQ_EVENT_V UINT32_C(0x1)
		#define NQ_SRQ_EVENT_RESERVED31_MASK UINT32_C(0xfffffffe)
		#define NQ_SRQ_EVENT_RESERVED31_SFT 1
		uint32_t srq_handle_high;
		/*
		* This is the SRQ handle value for the queue that has reached it's
		* event threshold. This field carries the upper 32b of the value.
		*/
		} __attribute__((packed));

		/* DBQ Async Event Notification (16 bytes) */

		struct nq_dbq_event {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define NQ_DBQ_EVENT_TYPE_MASK UINT32_C(0x3f)
		#define NQ_DBQ_EVENT_TYPE_SFT 0
		/* DBQ Threshold Event */
		#define NQ_DBQ_EVENT_TYPE_DBQ_EVENT UINT32_C(0x34)
		#define NQ_DBQ_EVENT_RESERVED1_MASK UINT32_C(0xc0)
		#define NQ_DBQ_EVENT_RESERVED1_SFT 6
		uint8_t event;
		/* This value define what type of action the driver should take. */
		/*
		* The driver should start writing dummy values to the the
		* doorbell in an attempt to consume all the PCIE posted write
		* resources and prevent doorbell overflow.
		*/
		#define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT UINT32_C(0x1)
		uint16_t db_pfid;
		/*
		* This is the PFID of function that wrote the doorbell that crossed the
		* async event threshold.
		*/
		#define NQ_DBQ_EVENT_DB_PFID_MASK UINT32_C(0xf)
		#define NQ_DBQ_EVENT_DB_PFID_SFT 0
		#define NQ_DBQ_EVENT_RESERVED12_MASK UINT32_C(0xfff0)
		#define NQ_DBQ_EVENT_RESERVED12_SFT 4
		uint32_t db_dpi;
		/*
		* This is the DPI of the doorbell write that crossed the async event
		* threshold.
		*/
		#define NQ_DBQ_EVENT_DB_DPI_MASK UINT32_C(0xfffff)
		#define NQ_DBQ_EVENT_DB_DPI_SFT 0
		#define NQ_DBQ_EVENT_RESERVED12_2_MASK UINT32_C(0xfff00000)
		#define NQ_DBQ_EVENT_RESERVED12_2_SFT 20
		uint32_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define NQ_DBQ_EVENT_V UINT32_C(0x1)
		#define NQ_DBQ_EVENT_RESERVED32_MASK UINT32_C(0xfffffffe)
		#define NQ_DBQ_EVENT_RESERVED32_SFT 1
		uint32_t db_type_db_xid;
		/* DB 'type' field from doorbell that crossed the async event threshold. */
		/*
		* DB 'XID' field from doorbell that crossed the async event threshold.
		* This is a QPID, SID, or CID, depending on the db_type field.
		*/
		#define NQ_DBQ_EVENT_DB_XID_MASK UINT32_C(0xfffff)
		#define NQ_DBQ_EVENT_DB_XID_SFT 0
		#define NQ_DBQ_EVENT_RESERVED8_MASK UINT32_C(0xff00000)
		#define NQ_DBQ_EVENT_RESERVED8_SFT 20
		/* DB 'type' field from doorbell that crossed the async event threshold. */
		#define NQ_DBQ_EVENT_DB_TYPE_MASK UINT32_C(0xf0000000)
		#define NQ_DBQ_EVENT_DB_TYPE_SFT 28
		} __attribute__((packed));

		/* Read Request/Response Queue Structures */
		/*
		* Description: This queue messages is used on the ORRQ to indicate output read
		* requests to the RX side of the chip.
		*/
		/* Input Read Request Queue (IRRQ) Message (32 bytes) */

		struct xrrq_irrq {
		uint16_t credits_type;
		/*
		* The credit code calculated by Rx path when receiving the request. It
		* will be placed in the syndrome credit code with the acks on first and
		* last response.
		*/
		/* Type indication */
		#define XRRQ_IRRQ_TYPE UINT32_C(0x1)
		/* RDMA Read */
		#define XRRQ_IRRQ_TYPE_READ_REQ UINT32_C(0x0)
		/* Atomic */
		#define XRRQ_IRRQ_TYPE_ATOMIC_REQ UINT32_C(0x1)
		#define XRRQ_IRRQ_RESERVED10_MASK UINT32_C(0x7fe)
		#define XRRQ_IRRQ_RESERVED10_SFT 1
		/*
		* The credit code calculated by Rx path when receiving the request. It
		* will be placed in the syndrome credit code with the acks on first and
		* last response.
		*/
		#define XRRQ_IRRQ_CREDITS_MASK UINT32_C(0xf800)
		#define XRRQ_IRRQ_CREDITS_SFT 11
		uint16_t reserved16;
		uint32_t reserved32;
		uint32_t psn;
		/* The PSN of the outstanding incoming request */
		#define XRRQ_IRRQ_PSN_MASK UINT32_C(0xffffff)
		#define XRRQ_IRRQ_PSN_SFT 0
		#define XRRQ_IRRQ_RESERVED8_1_MASK UINT32_C(0xff000000)
		#define XRRQ_IRRQ_RESERVED8_1_SFT 24
		uint32_t msn;
		/*
		* The value of QPC.pending_ack_msn after it is incremented as a result
		* of receiving the read/atomic request. IRRQ.msn-1 will be placed in
		* the MSN field of the first response and IRRQ.msn will placed in the
		* MSN field of the last or only response.
		*/
		#define XRRQ_IRRQ_MSN_MASK UINT32_C(0xffffff)
		#define XRRQ_IRRQ_MSN_SFT 0
		#define XRRQ_IRRQ_RESERVED8_2_MASK UINT32_C(0xff000000)
		#define XRRQ_IRRQ_RESERVED8_2_SFT 24
		uint64_t va_or_atomic_result;
		/*
		* Virtual address on local host for RDMA READ In case of duplicate
		* Atomic, the VA is not required to be validated, only the PSN is, thus
		* this field is used to store the value returned in the Ack to the
		* atomic request, and if duplicate arrives, this value is used again
		* for resending the ack.
		*/
		uint32_t rdma_r_key;
		/* The key to the MR/W in the request */
		uint32_t length;
		/*
		* Length in bytes of the data requested. Length must be 8 if type is
		* atomic.
		*/
		} __attribute__((packed));

		/* Output Read Request Queue (ORRQ) Message (32 bytes) */

		struct xrrq_orrq {
		uint16_t num_sges_type;
		/*
		* Up to 6 SGEs. This value is 1 if type is atomic as one SGE is
		* required to store Atomic response result field. 2 more bits allocated
		* for future growth. Note that, if num_sges is 1 for an RDMA Read
		* request, then the first_sge_phy_or_sing_sge_va, single_sge_l_key, and
		* single_sge_size fields will be populated from the single SGE. If
		* num_sges is 2 or more for an RDMA Read request, then the
		* first_sge_phy_or_sing_sge_va field carries the physical address in
		* host memory where the first sge is stored. The single_sge_l_key and
		* single_sge_size fields are unused in this case. A special case is a
		* zero-length, zero-sge RDMA read request WQE. In this situation,
		* num_sges will be 1. However, first_sge_phy_or_sing_sge_va,
		* single_sge_l_key, and single_sge_size will all be populated with
		* zeros.
		*/
		/* Type indication */
		#define XRRQ_ORRQ_TYPE UINT32_C(0x1)
		/* RDMA Read */
		#define XRRQ_ORRQ_TYPE_READ_REQ UINT32_C(0x0)
		/* Atomic */
		#define XRRQ_ORRQ_TYPE_ATOMIC_REQ UINT32_C(0x1)
		#define XRRQ_ORRQ_RESERVED10_MASK UINT32_C(0x7fe)
		#define XRRQ_ORRQ_RESERVED10_SFT 1
		/*
		* Up to 6 SGEs. This value is 1 if type is atomic as one SGE is
		* required to store Atomic response result field. 2 more bits allocated
		* for future growth. Note that, if num_sges is 1 for an RDMA Read
		* request, then the first_sge_phy_or_sing_sge_va, single_sge_l_key, and
		* single_sge_size fields will be populated from the single SGE. If
		* num_sges is 2 or more for an RDMA Read request, then the
		* first_sge_phy_or_sing_sge_va field carries the physical address in
		* host memory where the first sge is stored. The single_sge_l_key and
		* single_sge_size fields are unused in this case. A special case is a
		* zero-length, zero-sge RDMA read request WQE. In this situation,
		* num_sges will be 1. However, first_sge_phy_or_sing_sge_va,
		* single_sge_l_key, and single_sge_size will all be populated with
		* zeros.
		*/
		#define XRRQ_ORRQ_NUM_SGES_MASK UINT32_C(0xf800)
		#define XRRQ_ORRQ_NUM_SGES_SFT 11
		uint16_t reserved16;
		uint32_t length;
		/*
		* Length in bytes of the data requested. Length must be 8 if type is
		* atomic.
		*/
		uint32_t psn;
		/* The PSN of the outstanding outgoing request */
		#define XRRQ_ORRQ_PSN_MASK UINT32_C(0xffffff)
		#define XRRQ_ORRQ_PSN_SFT 0
		#define XRRQ_ORRQ_RESERVED8_1_MASK UINT32_C(0xff000000)
		#define XRRQ_ORRQ_RESERVED8_1_SFT 24
		uint32_t end_psn;
		/*
		* The expected last PSN on a response to this request where an ack with
		* response, rather than just response, should arrive. If ack arrive
		* with smaller PSN than end_psn then it is considered a NAK.
		*/
		#define XRRQ_ORRQ_END_PSN_MASK UINT32_C(0xffffff)
		#define XRRQ_ORRQ_END_PSN_SFT 0
		#define XRRQ_ORRQ_RESERVED8_2_MASK UINT32_C(0xff000000)
		#define XRRQ_ORRQ_RESERVED8_2_SFT 24
		uint64_t first_sge_phy_or_sing_sge_va;
		/*
		* If num_sges == 1 this is the va of that SGE. Otherwise, physical
		* address to the first SGE specified by the WQE. Points to the first
		* SGE in the Request's WQE in the SQ. It is assumed that WQE does not
		* cross page boundaries! Driver is responsible to enforce that. SGEs
		* are 16B aligned 0b0000 lsb added to get 64 bit address.
		*/
		uint32_t single_sge_l_key;
		/* The L_Key of a single SGE if used */
		uint32_t single_sge_size;
		/* The size in bytes of the single SGE if used */
		} __attribute__((packed));

		/* Page Buffer List Memory Structures (PBL) */
		/*
		* Description: Page directory entries point to a page directories made up of
		* PTE values.
		*/
		/* Page Table Entry (PTE) (8 bytes) */

		struct ptu_pte {
		uint64_t page_next_to_last_last_valid;
		/*
		* This is the upper bits of the physical page controlled by this PTE.
		* If the page is larger than 4KB, then the unused lower bits of the
		* page address should be zero.
		*/
		/*
		* This field indicates if the PTE is valid. A value of '0' indicates
		* that the page is not valid. A value of '1' indicates that the page is
		* valid. A reference to an invalid page will return a PTU error.
		*/
		#define PTU_PTE_VALID UINT32_C(0x1)
		/*
		* This field is used only for "ring" PBLs that are used for SQ, RQ,
		* SRQ, or CQ structures. For all other PBL structures, this bit should
		* be zero. When this bit is '1', it indicates that the page pointed to
		* by this PTE is the last page in the ring. A prefetch for the ring
		* should use the first PTE in the PBL.
		*/
		#define PTU_PTE_LAST UINT32_C(0x2)
		/*
		* This field is used only for "ring" PBLs that are used for SQ, RQ,
		* SRQ, or CQ structures. For all other PBL structures, this bit should
		* be zero. When this bit is '1', it indicates that this is the next-to-
		* last page of the PBL.
		*/
		#define PTU_PTE_NEXT_TO_LAST UINT32_C(0x4)
		/* These bits should be programmed to zero. */
		/*
		* This is the upper bits of the physical page controlled by this PTE.
		* If the page is larger than 4KB, then the unused lower bits of the
		* page address should be zero.
		*/
		#define PTU_PTE_PAGE_MASK UINT32_C(0xfffff000)
		#define PTU_PTE_PAGE_SFT 12
		} __attribute__((packed));

		/* Page Directory Entry (PDE) (8 bytes) */

		struct ptu_pde {
		uint64_t page_valid;
		/*
		* This is the upper bits of the physical page controlled by this PTE.
		* If the page is larger than 4KB, then the unused lower bits of the
		* page address should be zero.
		*/
		/*
		* This field indicates if the PTE is valid. A value of '0' indicates
		* that the page is not valid. A value of '1' indicates that the page is
		* valid. A reference to an invalid page will return a PTU error.
		*/
		#define PTU_PDE_VALID UINT32_C(0x1)
		/* These bits should be programmed to zero. */
		/*
		* This is the upper bits of the physical page controlled by this PTE.
		* If the page is larger than 4KB, then the unused lower bits of the
		* page address should be zero.
		*/
		#define PTU_PDE_PAGE_MASK UINT32_C(0xfffff000)
		#define PTU_PDE_PAGE_SFT 12
		} __attribute__((packed));

		/* RoCE Fastpath Host Structures */
		/*
		* Note: This section documents the host structures used between RoCE state
		* machines and RoCE drivers/libraries.
		*/
	/* hwrm_ver_get */	/* hwrm_ver_get */
	/*	/*
	* Description: This function is called by a driver to determine the HWRM	* Description: This function is called by a driver to determine the HWRM
Context not available.
	* firmware branches or customer specific releases tied to a specific	* firmware branches or customer specific releases tied to a specific
	* (major,minor,update) version	* (major,minor,update) version
	*/	*/
	uint32_t reserved1;	uint32_t dev_caps_cfg;
	/*	/*
	* This field is reserved for future use. The responder should set it to	* This field is used to indicate device's capabilities and
	* 0. The requester should ignore this field.	* configurations.
	*/	*/
		/*
		* If set to 1, then secure firmware update behavior is supported. If
		* set to 0, then secure firmware update behavior is not supported.
		*/
		#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED UINT32_C(0x1)
		/*
		* If set to 1, then firmware based DCBX agent is supported. If set to
		* 0, then firmware based DCBX agent capability is not supported on this
		* device.
		*/
		#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED UINT32_C(0x2)
		/*
		* If set to 1, then HWRM short command format is supported. If set to
		* 0, then HWRM short command format is not supported.
		*/
		#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED UINT32_C(0x4)
		/*
		* If set to 1, then HWRM short command format is required. If set to 0,
		* then HWRM short command format is not required.
		*/
		#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED UINT32_C(0x8)
	uint8_t roce_fw_maj;	uint8_t roce_fw_maj;
	/*	/*
	* This field represents the major version of RoCE firmware. A change in	* This field represents the major version of RoCE firmware. A change in
Context not available.
	/* This field returns the maximum value of response buffer in bytes. */	/* This field returns the maximum value of response buffer in bytes. */
	uint16_t def_req_timeout;	uint16_t def_req_timeout;
	/* This field returns the default request timeout value in milliseconds. */	/* This field returns the default request timeout value in milliseconds. */
		uint8_t init_pending;
		/* This field will indicate if any subsystems is not fully initialized. */
		/*
		* If set to 1, device is not ready. If set to 0, device is ready to
		* accept all HWRM commands.
		*/
		#define HWRM_VER_GET_OUTPUT_INIT_PENDING_DEV_NOT_RDY UINT32_C(0x1)
	uint8_t unused_0;	uint8_t unused_0;
	uint8_t unused_1;	uint8_t unused_1;
	uint8_t unused_2;
	uint8_t valid;	uint8_t valid;
	/*	/*
	* This field is used in Output records to indicate that the output is	* This field is used in Output records to indicate that the output is
Context not available.
	/*	/*
	* This value is the PCI ID of the queried function. If ARI is enabled,	* This value is the PCI ID of the queried function. If ARI is enabled,
	* then it is Bus Number (8b):Function Number(8b). Otherwise, it is Bus	* then it is Bus Number (8b):Function Number(8b). Otherwise, it is Bus
	* Number (8b):Device Number (4b):Function Number(4b).	* Number (8b):Device Number (5b):Function Number(3b).
	*/	*/
	uint16_t unused_0;	uint16_t unused_0;
	} __attribute__((packed));	} __attribute__((packed));
Context not available.
	*/	*/
	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED UINT32_C(0x10)	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED UINT32_C(0x10)
	/*	/*
	* If 1, then control and configuration of WoL magic packet is supported	* If 1, then control and configuration of WoL magic packet are
	* on this function.	* supported on this function.
	*/	*/
	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED UINT32_C(0x20)	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED UINT32_C(0x20)
	/*	/*
	* If 1, then control and configuration of bitmap pattern packet is	* If 1, then control and configuration of bitmap pattern packet are
	* supported on this function.	* supported on this function.
	*/	*/
	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED UINT32_C(0x40)	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED UINT32_C(0x40)
		/*
		* If set to 1, then the control and configuration of rate limit of an
		* allocated TX ring on the queried function is supported.
		*/
		#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED UINT32_C(0x80)
		/*
		* If 1, then control and configuration of minimum and maximum
		* bandwidths are supported on the queried function.
		*/
		#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED UINT32_C(0x100)
		/*
		* If the query is for a VF, then this flag shall be ignored. If this
		* query is for a PF and this flag is set to 1, then the PF has the
		* capability to set the rate limits on the TX rings of its children
		* VFs. If this query is for a PF and this flag is set to 0, then the PF
		* does not have the capability to set the rate limits on the TX rings
		* of its children VFs.
		*/
		#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED UINT32_C(0x200)
		/*
		* If the query is for a VF, then this flag shall be ignored. If this
		* query is for a PF and this flag is set to 1, then the PF has the
		* capability to set the minimum and/or maximum bandwidths for its
		* children VFs. If this query is for a PF and this flag is set to 0,
		* then the PF does not have the capability to set the minimum or
		* maximum bandwidths for its children VFs.
		*/
		#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED UINT32_C(0x400)
		/*
		* Standard TX Ring mode is used for the allocation of TX ring and
		* underlying scheduling resources that allow bandwidth reservation and
		* limit settings on the queried function. If set to 1, then standard TX
		* ring mode is supported on the queried function. If set to 0, then
		* standard TX ring mode is not available on the queried function.
		*/
		#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED UINT32_C(0x800)
	uint8_t mac_address[6];	uint8_t mac_address[6];
	/*	/*
	* This value is current MAC address configured for this function. A	* This value is current MAC address configured for this function. A
Context not available.
	* The maximum number of HW ring groups that can be supported on this	* The maximum number of HW ring groups that can be supported on this
	* function.	* function.
	*/	*/
		uint16_t max_sp_tx_rings;
		/*
		* The maximum number of strict priority transmit rings that can be
		* allocated to the function. This number indicates the maximum number
		* of TX rings that can be assigned strict priorities out of the maximum
		* number of TX rings that can be allocated (max_tx_rings) to the
		* function.
		*/
	uint8_t unused_0;	uint8_t unused_0;
	uint8_t unused_1;
	uint8_t unused_2;
	uint8_t valid;	uint8_t valid;
	/*	/*
	* This field is used in Output records to indicate that the output is	* This field is used in Output records to indicate that the output is
Context not available.
	* allows a physical function driver to query virtual functions that are	* allows a physical function driver to query virtual functions that are
	* children of the physical function. The output FID value is needed to	* children of the physical function. The output FID value is needed to
	* configure Rings and MSI-X vectors so their DMA operations appear correctly on	* configure Rings and MSI-X vectors so their DMA operations appear correctly on
	* the PCI bus.	* the PCI bus. This command should be called by every driver after
		* 'hwrm_func_cfg' to get the actual number of resources allocated by the HWRM.
		* The values returned by hwrm_func_qcfg are the values the driver shall use.
		* These values may be different than what was originally requested in the
		* 'hwrm_func_cfg' command.
	*/	*/
	/* Input (24 bytes) */	/* Input (24 bytes) */

Context not available.
	* the port associated with this function.	* the port associated with this function.
	*/	*/
	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED UINT32_C(0x2)	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED UINT32_C(0x2)
		/*
		* If set to 1, then FW based DCBX agent is enabled and running on the
		* port associated with this function. If set to 0, then DCBX agent is
		* not running in the firmware.
		*/
		#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED UINT32_C(0x4)
		/*
		* Standard TX Ring mode is used for the allocation of TX ring and
		* underlying scheduling resources that allow bandwidth reservation and
		* limit settings on the queried function. If set to 1, then standard TX
		* ring mode is enabled on the queried function. If set to 0, then the
		* standard TX ring mode is disabled on the queried function. In this
		* extended TX ring resource mode, the minimum and maximum bandwidth
		* settings are not supported to allow the allocation of TX rings to
		* span multiple scheduler nodes.
		*/
		#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED UINT32_C(0x8)
		/*
		* If set to 1 then FW based LLDP agent is enabled and running on the
		* port associated with this function. If set to 0 then the LLDP agent
		* is not running in the firmware.
		*/
		#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED UINT32_C(0x10)
		/*
		* If set to 1, then multi-host mode is active for this function. If set
		* to 0, then multi-host mode is inactive for this function or not
		* applicable for this device.
		*/
		#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST UINT32_C(0x20)
	uint8_t mac_address[6];	uint8_t mac_address[6];
	/*	/*
	* This value is current MAC address configured for this function. A	* This value is current MAC address configured for this function. A
Context not available.
	/*	/*
	* This value is current PCI ID of this function. If ARI is enabled,	* This value is current PCI ID of this function. If ARI is enabled,
	* then it is Bus Number (8b):Function Number(8b). Otherwise, it is Bus	* then it is Bus Number (8b):Function Number(8b). Otherwise, it is Bus
	* Number (8b):Device Number (4b):Function Number(4b).	* Number (8b):Device Number (4b):Function Number(4b). If multi-host
		* mode is active, the 4 lsb will indicate the PF index for this
		* function.
	*/	*/
	uint16_t alloc_rsscos_ctx;	uint16_t alloc_rsscos_ctx;
	/* The number of RSS/COS contexts currently allocated to the function. */	/* The number of RSS/COS contexts currently allocated to the function. */
Context not available.
	#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)	#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
	/* Unknown */	/* Unknown */
	#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN UINT32_C(0xff)	#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN UINT32_C(0xff)
	uint8_t unused_0;	uint8_t port_pf_cnt;
		/*
		* This field will indicate number of physical functions on this
		* port_partition. HWRM shall return unavail (i.e. value of 0) for this
		* field when this command is used to query VF's configuration or from
		* older firmware that doesn't support this field.
		*/
		/* number of PFs is not available */
		#define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
	uint16_t dflt_vnic_id;	uint16_t dflt_vnic_id;
	/* The default VNIC ID assigned to a function that is being queried. */	/* The default VNIC ID assigned to a function that is being queried. */
		uint8_t unused_0;
	uint8_t unused_1;	uint8_t unused_1;
	uint8_t unused_2;
	uint32_t min_bw;	uint32_t min_bw;
	/*	/*
	* Minimum BW allocated for this function in Mbps. The HWRM will	* Minimum BW allocated for this function. The HWRM will translate this
	* translate this value into byte counter and time interval used for the	* value into byte counter and time interval used for the scheduler
	* scheduler inside the device. A value of 0 indicates the minimum	* inside the device. A value of 0 indicates the minimum bandwidth is
	* bandwidth is not configured.	* not configured.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t max_bw;	uint32_t max_bw;
	/*	/*
	* Maximum BW allocated for this function in Mbps. The HWRM will	* Maximum BW allocated for this function. The HWRM will translate this
	* translate this value into byte counter and time interval used for the	* value into byte counter and time interval used for the scheduler
	* scheduler inside the device. A value of 0 indicates that the maximum	* inside the device. A value of 0 indicates that the maximum bandwidth
	* bandwidth is not configured.	* is not configured.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t evb_mode;	uint8_t evb_mode;
	/*	/*
	* This value indicates the Edge virtual bridge mode for the domain that	* This value indicates the Edge virtual bridge mode for the domain that
Context not available.
	#define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)	#define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
	/* Virtual Ethernet Port Aggregator (VEPA) */	/* Virtual Ethernet Port Aggregator (VEPA) */
	#define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)	#define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
	uint8_t unused_3;	uint8_t unused_2;
	uint16_t unused_4;	uint16_t alloc_vfs;
		/*
		* The number of VFs that are allocated to the function. This is valid
		* only on the PF with SR-IOV enabled. 0xFF... (All Fs) if this command
		* is called on a PF with SR-IOV disabled or on a VF.
		*/
	uint32_t alloc_mcast_filters;	uint32_t alloc_mcast_filters;
	/*	/*
	* The number of allocated multicast filters for this function on the RX	* The number of allocated multicast filters for this function on the RX
Context not available.
	*/	*/
	uint32_t alloc_hw_ring_grps;	uint32_t alloc_hw_ring_grps;
	/* The number of allocated HW ring groups for this function. */	/* The number of allocated HW ring groups for this function. */
		uint16_t alloc_sp_tx_rings;
		/*
		* The number of strict priority transmit rings out of currently
		* allocated TX rings to the function (alloc_tx_rings).
		*/
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_func_vlan_qcfg */
		/*
		* Description: This command should be called by PF driver to get the current
		* C-TAG, S-TAG and correcponsing PCP and TPID values configured for the
		* function.
		*/
		/* Input (24 bytes) */

		struct hwrm_func_vlan_qcfg_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t fid;
		/*
		* Function ID of the function that is being configured. If set to
		* 0xFF... (All Fs), then the configuration is for the requesting
		* function.
		*/
		uint16_t unused_0[3];
		} __attribute__((packed));

		/* Output (40 bytes) */

		struct hwrm_func_vlan_qcfg_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		uint16_t stag_vid;
		/* S-TAG VLAN identifier configured for the function. */
		uint8_t stag_pcp;
		/* S-TAG PCP value configured for the function. */
		uint8_t unused_4;
		uint16_t stag_tpid; /* big endian */
		/*
		* S-TAG TPID value configured for the function. This field is specified
		* in network byte order.
		*/
		uint16_t ctag_vid;
		/* C-TAG VLAN identifier configured for the function. */
		uint8_t ctag_pcp;
		/* C-TAG PCP value configured for the function. */
	uint8_t unused_5;	uint8_t unused_5;
	uint8_t unused_6;	uint16_t ctag_tpid; /* big endian */
	uint8_t unused_7;	/*
		* C-TAG TPID value configured for the function. This field is specified
		* in network byte order.
		*/
		uint32_t rsvd2;
		/* Future use. */
		uint32_t rsvd3;
		/* Future use. */
		uint32_t unused_6;
		} __attribute__((packed));

		/* hwrm_func_vlan_cfg */
		/*
		* Description: This command allows PF driver to configure C-TAG, S-TAG and
		* corresponding PCP and TPID values for a function.
		*/
		/* Input (48 bytes) */

		struct hwrm_func_vlan_cfg_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t fid;
		/*
		* Function ID of the function that is being configured. If set to
		* 0xFF... (All Fs), then the configuration is for the requesting
		* function.
		*/
		uint8_t unused_0;
		uint8_t unused_1;
		uint32_t enables;
		/* This bit must be '1' for the stag_vid field to be configured. */
		#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
		/* This bit must be '1' for the ctag_vid field to be configured. */
		#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
		/* This bit must be '1' for the stag_pcp field to be configured. */
		#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
		/* This bit must be '1' for the ctag_pcp field to be configured. */
		#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
		/* This bit must be '1' for the stag_tpid field to be configured. */
		#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
		/* This bit must be '1' for the ctag_tpid field to be configured. */
		#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
		uint16_t stag_vid;
		/* S-TAG VLAN identifier configured for the function. */
		uint8_t stag_pcp;
		/* S-TAG PCP value configured for the function. */
		uint8_t unused_2;
		uint16_t stag_tpid; /* big endian */
		/*
		* S-TAG TPID value configured for the function. This field is specified
		* in network byte order.
		*/
		uint16_t ctag_vid;
		/* C-TAG VLAN identifier configured for the function. */
		uint8_t ctag_pcp;
		/* C-TAG PCP value configured for the function. */
		uint8_t unused_3;
		uint16_t ctag_tpid; /* big endian */
		/*
		* C-TAG TPID value configured for the function. This field is specified
		* in network byte order.
		*/
		uint32_t rsvd1;
		/* Future use. */
		uint32_t rsvd2;
		/* Future use. */
		uint32_t unused_4;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_func_vlan_cfg_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
	uint8_t valid;	uint8_t valid;
	/*	/*
	* This field is used in Output records to indicate that the output is	* This field is used in Output records to indicate that the output is
Context not available.
	* set MTU/MRU for a VF using this command. This is to allow MTU/MRU setting by	* set MTU/MRU for a VF using this command. This is to allow MTU/MRU setting by
	* the VF driver. If the MTU or MRU for a VF is set by the PF driver, then the	* the VF driver. If the MTU or MRU for a VF is set by the PF driver, then the
	* HWRM should ignore it. A function's MTU/MRU should be set prior to allocating	* HWRM should ignore it. A function's MTU/MRU should be set prior to allocating
	* RX VNICs or TX rings.	* RX VNICs or TX rings. A PF driver calls hwrm_func_cfg to allocate resources
		* for itself or its children VFs. All function drivers shall call hwrm_func_cfg
		* to reserve resources. A request to hwrm_func_cfg may not be fully granted;
		* that is, a request for resources may be larger than what can be supported by
		* the device and the HWRM will allocate the best set of resources available,
		* but that may be less than requested. If all the amounts requested could not
		* be fulfilled, the HWRM shall allocate what it could and return a status code
		* of success. A function driver should call hwrm_func_qcfg immediately after
		* hwrm_func_cfg to determine what resources were assigned to the configured
		* function. A call by a PF driver to hwrm_func_cfg to allocate resources for
		* itself shall only allocate resources for the PF driver to use, not for its
		* children VFs. Likewise, a call to hwrm_func_qcfg shall return the resources
		* available for the PF driver to use, not what is available to its children
		* VFs.
	*/	*/
	/* Input (88 bytes) */	/* Input (88 bytes) */

Context not available.
	uint8_t unused_1;	uint8_t unused_1;
	uint32_t flags;	uint32_t flags;
	/*	/*
	* When this bit is '1', the function is requested to be put in the	* When this bit is '1', the function is disabled with source MAC
	* promiscuous mode.	* address check. This is an anti-spoofing check. If this flag is set,
		* then the function shall be configured to disallow transmission of
		* frames with the source MAC address that is configured for this
		* function.
	*/	*/
	#define HWRM_FUNC_CFG_INPUT_FLAGS_PROM_MODE UINT32_C(0x1)	#define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE UINT32_C(0x1)
	/*	/*
	* When this bit is '1', the function is enabled with source MAC address	* When this bit is '1', the function is enabled with source MAC address
	* check. This is an anti-spoofing check. If this flag is set, then the	* check. This is an anti-spoofing check. If this flag is set, then the
	* function shall be configured to allow transmission of frames with the	* function shall be configured to allow transmission of frames with the
	* source MAC address that is configured for this function.	* source MAC address that is configured for this function.
	*/	*/
	#define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK UINT32_C(0x2)	#define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE UINT32_C(0x2)
		/* reserved */
		#define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK UINT32_C(0x1fc)
		#define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
	/*	/*
	* When this bit is '1', the function is enabled with source IP address	* Standard TX Ring mode is used for the allocation of TX ring and
	* check. This is an anti-spoofing check. If this flag is set, then the	* underlying scheduling resources that allow bandwidth reservation and
	* function shall be configured to allow transmission of frames with the	* limit settings on the queried function. If set to 1, then standard TX
	* source IP address that is configured for this function.	* ring mode is requested to be enabled on the function being
		* configured.
	*/	*/
	#define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_IP_ADDR_CHECK UINT32_C(0x4)	#define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE UINT32_C(0x200)
	/*	/*
	* When this bit is set to '1', the function shall be configured with	* Standard TX Ring mode is used for the allocation of TX ring and
	* VLAN priority match. If the VLAN PRI of a packet originated from this	* underlying scheduling resources that allow bandwidth reservation and
	* function does not match, then the packet shall be discarded.	* limit settings on the queried function. If set to 1, then the
		* standard TX ring mode is requested to be disabled on the function
		* being configured. In this extended TX ring resource mode, the minimum
		* and maximum bandwidth settings are not supported to allow the
		* allocation of TX rings to span multiple scheduler nodes.
	*/	*/
	#define HWRM_FUNC_CFG_INPUT_FLAGS_VLAN_PRI_MATCH UINT32_C(0x8)	#define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE UINT32_C(0x400)
	/*	/*
	* When this bit is set to '1', the function shall be configured to	* If this bit is set, virtual mac address configured in this command
	* check for VLAN priority match. If the VLAN PRI of a packet originated	* will be persistent over warm boot.
	* from this function does not match, then the default VLAN PRI shall be
	* used.
	*/	*/
	#define HWRM_FUNC_CFG_INPUT_FLAGS_DFLT_PRI_NOMATCH UINT32_C(0x10)	#define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST UINT32_C(0x800)
	/*	/*
	* When this bit is set to '1', the function shall be configured to not	* This bit only applies to the VF. If this bit is set, the statistic
	* allow the transmission of pause frames. PAUSE frames use 48-bit	* context counters will not be cleared when the statistic context is
	* destination multicast MAC address 01-80-C2-00-00-01.	* freed or a function reset is called on VF. This bit will be cleared
		* when the PF is unloaded or a function reset is called on the PF.
	*/	*/
	#define HWRM_FUNC_CFG_INPUT_FLAGS_DISABLE_PAUSE UINT32_C(0x20)	#define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC UINT32_C(0x1000)
	/*	/*
	* When this bit is set to '1', the function shall be configured to not	* This bit requests that the firmware test to see if all the assets
	* allow the transmission of Spanning Tree Protocol (STP) frames. STP	* requested in this command (i.e. number of TX rings) are available.
	* frames use Ethertype 0x0802 and 48-bit destination multicast MAC	* The firmware will return an error if the requested assets are not
	* address 01-80-C2-00-00-00 and 01-80-C2-00-00-08 for 802.1D and	* available. The firwmare will NOT reserve the assets if they are
	* 802.1ad respectively.	* available.
	*/	*/
	#define HWRM_FUNC_CFG_INPUT_FLAGS_DISABLE_STP UINT32_C(0x40)	#define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST UINT32_C(0x2000)
	/*
	* When this bit is set to '1', the function shall be configured to not
	* allow the transmission of Link Layer Discovery Protocol (LLDP)
	* frames. LLDP frames use Ethertype 0x88CC and 48-bit destination
	* multicast MAC address 01-80-C2-00-00-00 or 01-80-C2-00-00-03 or
	* 01-80-C2-00-00-0E.
	*/
	#define HWRM_FUNC_CFG_INPUT_FLAGS_DISABLE_LLDP UINT32_C(0x80)
	/*
	* When this bit is set to '1', the function shall be configured to not
	* allow the transmission of Precision Time Protocol (PTP) v2 frames.
	* PTP frames use Ethertype 0x88F7 and 48-bit destination multicast MAC
	* address 01-80-C2-00-00-0E or 01-1B-19-00-00-00.
	*/
	#define HWRM_FUNC_CFG_INPUT_FLAGS_DISABLE_PTPV2 UINT32_C(0x100)
	uint32_t enables;	uint32_t enables;
	/* This bit must be '1' for the mtu field to be configured. */	/* This bit must be '1' for the mtu field to be configured. */
	#define HWRM_FUNC_CFG_INPUT_ENABLES_MTU UINT32_C(0x1)	#define HWRM_FUNC_CFG_INPUT_ENABLES_MTU UINT32_C(0x1)
Context not available.
	*/	*/
	uint32_t min_bw;	uint32_t min_bw;
	/*	/*
	* Minimum BW allocated for this function in Mbps. The HWRM will	* Minimum BW allocated for this function. The HWRM will translate this
	* translate this value into byte counter and time interval used for the	* value into byte counter and time interval used for the scheduler
	* scheduler inside the device.	* inside the device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t max_bw;	uint32_t max_bw;
	/*	/*
	* Maximum BW allocated for this function in Mbps. The HWRM will	* Maximum BW allocated for this function. The HWRM will translate this
	* translate this value into byte counter and time interval used for the	* value into byte counter and time interval used for the scheduler
	* scheduler inside the device.	* inside the device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
	uint16_t async_event_cr;	uint16_t async_event_cr;
	/*	/*
	* ID of the target completion ring for receiving asynchronous event	* ID of the target completion ring for receiving asynchronous event
Context not available.
	/* Number of transmitted multicast packets on the function. */	/* Number of transmitted multicast packets on the function. */
	uint64_t tx_bcast_pkts;	uint64_t tx_bcast_pkts;
	/* Number of transmitted broadcast packets on the function. */	/* Number of transmitted broadcast packets on the function. */
	uint64_t tx_err_pkts;	uint64_t tx_discard_pkts;
	/*	/*
	* Number of transmitted packets that were dropped due to internal NIC	* Number of transmitted packets that were discarded due to internal NIC
	* resource problems. For transmit, this can only happen if TMP is	* resource problems. For transmit, this can only happen if TMP is
	* configured to allow dropping in HOL blocking conditions, which is not	* configured to allow dropping in HOL blocking conditions, which is not
	* a normal configuration.	* a normal configuration.
Context not available.
	/* Number of received multicast packets on the function. */	/* Number of received multicast packets on the function. */
	uint64_t rx_bcast_pkts;	uint64_t rx_bcast_pkts;
	/* Number of received broadcast packets on the function. */	/* Number of received broadcast packets on the function. */
	uint64_t rx_err_pkts;	uint64_t rx_discard_pkts;
	/*	/*
	* Number of received packets that were dropped on the function due to	* Number of received packets that were discarded on the function due to
	* resource limitations. This can happen for 3 reasons. # The BD used	* resource limitations. This can happen for 3 reasons. # The BD used
	* for the packet has a bad format. # There were no BDs available in the	* for the packet has a bad format. # There were no BDs available in the
	* ring for the packet. # There were no BDs available on-chip for the	* ring for the packet. # There were no BDs available on-chip for the
Context not available.
	/* This bit must be '1' for the async_event_fwd field to be configured. */	/* This bit must be '1' for the async_event_fwd field to be configured. */
	#define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD UINT32_C(0x10)	#define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD UINT32_C(0x10)
	uint16_t os_type;	uint16_t os_type;
	/* This value indicates the type of OS. */	/*
		* This value indicates the type of OS. The values are based on
		* CIM_OperatingSystem.mof file as published by the DMTF.
		*/
	/* Unknown */	/* Unknown */
	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
	/* Other OS not listed below. */	/* Other OS not listed below. */
Context not available.
	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
	/* Microsoft Windows Server 2012 R2 OS. */	/* Microsoft Windows Server 2012 R2 OS. */
	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
		/* UEFI driver. */
		#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
	uint8_t ver_maj;	uint8_t ver_maj;
	/* This is the major version of the driver. */	/* This is the major version of the driver. */
	uint8_t ver_min;	uint8_t ver_min;
Context not available.
	* has been completely written to memory.	* has been completely written to memory.
	*/	*/
	uint16_t os_type;	uint16_t os_type;
	/* This value indicates the type of OS. */	/*
		* This value indicates the type of OS. The values are based on
		* CIM_OperatingSystem.mof file as published by the DMTF.
		*/
	/* Unknown */	/* Unknown */
	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
	/* Other OS not listed below. */	/* Other OS not listed below. */
Context not available.
	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
	/* Microsoft Windows Server 2012 R2 OS. */	/* Microsoft Windows Server 2012 R2 OS. */
	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
		/* UEFI driver. */
		#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
	uint8_t ver_maj;	uint8_t ver_maj;
	/* This is the major version of the driver. */	/* This is the major version of the driver. */
	uint8_t ver_min;	uint8_t ver_min;
Context not available.
	* command.	* command.
	*/	*/
	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1)	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1)
		/* deprecated bit. Do not use!!! */
		#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED UINT32_C(0x2)
	/*	/*
	* When this bit is set to '1', the link shall be forced to be taken
	* down. # When this bit is set to '1", all other command input settings
	* related to the link speed shall be ignored. Once the link state is
	* forced down, it can be explicitly cleared from that state by setting
	* this flag to '0'. # If this flag is set to '0', then the link shall
	* be cleared from forced down state if the link is in forced down
	* state. There may be conditions (e.g. out-of-band or sideband
	* configuration changes for the link) outside the scope of the HWRM
	* implementation that may clear forced down link state.
	*/
	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN UINT32_C(0x2)
	/*
	* When this bit is set to '1', the link shall be forced to the	* When this bit is set to '1', the link shall be forced to the
	* force_link_speed value. When this bit is set to '1', the HWRM client	* force_link_speed value. When this bit is set to '1', the HWRM client
	* should not enable any of the auto negotiation related fields	* should not enable any of the auto negotiation related fields
Context not available.
	* shall ignore this flag.	* shall ignore this flag.
	*/	*/
	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE UINT32_C(0x2000)	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE UINT32_C(0x2000)
		/*
		* When this bit is set to '1', the link shall be forced to be taken
		* down. # When this bit is set to '1", all other command input settings
		* related to the link speed shall be ignored. Once the link state is
		* forced down, it can be explicitly cleared from that state by setting
		* this flag to '0'. # If this flag is set to '0', then the link shall
		* be cleared from forced down state if the link is in forced down
		* state. There may be conditions (e.g. out-of-band or sideband
		* configuration changes for the link) outside the scope of the HWRM
		* implementation that may clear forced down link state.
		*/
		#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN UINT32_C(0x4000)
	uint32_t enables;	uint32_t enables;
	/* This bit must be '1' for the auto_mode field to be configured. */	/* This bit must be '1' for the auto_mode field to be configured. */
	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE UINT32_C(0x1)	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE UINT32_C(0x1)
Context not available.
	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
	/* 10Mb link speed */	/* 10Mb link speed */
	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
	uint8_t duplex;	uint8_t duplex_cfg;
	/* This value is indicates the duplex of the current connection. */	/* This value is indicates the duplex of the current configuration. */
	/* Half Duplex connection. */	/* Half Duplex connection. */
	#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_HALF UINT32_C(0x0)	#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
	/* Full duplex connection. */	/* Full duplex connection. */
	#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_FULL UINT32_C(0x1)	#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
	uint8_t pause;	uint8_t pause;
	/*	/*
	* This value is used to indicate the current pause configuration. When	* This value is used to indicate the current pause configuration. When
Context not available.
	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE UINT32_C(0x9)	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE UINT32_C(0x9)
	/* SGMII connected external PHY */	/* SGMII connected external PHY */
	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY UINT32_C(0xa)	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY UINT32_C(0xa)
		/* 25G_BASECR_CA_L */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L UINT32_C(0xb)
		/* 25G_BASECR_CA_S */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S UINT32_C(0xc)
		/* 25G_BASECR_CA_N */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N UINT32_C(0xd)
		/* 25G_BASESR */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR UINT32_C(0xe)
		/* 100G_BASECR4 */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 UINT32_C(0xf)
		/* 100G_BASESR4 */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 UINT32_C(0x10)
		/* 100G_BASELR4 */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 UINT32_C(0x11)
		/* 100G_BASEER4 */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 UINT32_C(0x12)
		/* 100G_BASESR10 */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 UINT32_C(0x13)
		/* 40G_BASECR4 */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 UINT32_C(0x14)
		/* 40G_BASESR4 */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 UINT32_C(0x15)
		/* 40G_BASELR4 */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 UINT32_C(0x16)
		/* 40G_BASEER4 */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 UINT32_C(0x17)
		/* 40G_ACTIVE_CABLE */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE UINT32_C(0x18)
		/* 1G_baseT */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET UINT32_C(0x19)
		/* 1G_baseSX */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX UINT32_C(0x1a)
		/* 1G_baseCX */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX UINT32_C(0x1b)
	uint8_t media_type;	uint8_t media_type;
	/* This value represents a media type. */	/* This value represents a media type. */
	/* Unknown */	/* Unknown */
Context not available.
	* supported on this port.	* supported on this port.
	*/	*/
	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED UINT32_C(0x40)	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED UINT32_C(0x40)
		uint8_t duplex_state;
		/* This value is indicates the duplex of the current connection state. */
		/* Half Duplex connection. */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
		/* Full duplex connection. */
		#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
	uint8_t unused_1;	uint8_t unused_1;
	uint8_t unused_2;
	char phy_vendor_name[16];	char phy_vendor_name[16];
	/*	/*
	* Up to 16 bytes of null padded ASCII string representing PHY vendor.	* Up to 16 bytes of null padded ASCII string representing PHY vendor.
Context not available.
	* specific part number of the PHY. If the string is set to null, then	* specific part number of the PHY. If the string is set to null, then
	* the vendor specific part number is not available.	* the vendor specific part number is not available.
	*/	*/
	uint32_t unused_3;	uint32_t unused_2;
		uint8_t unused_3;
	uint8_t unused_4;	uint8_t unused_4;
	uint8_t unused_5;	uint8_t unused_5;
	uint8_t unused_6;
	uint8_t valid;	uint8_t valid;
	/*	/*
	* This field is used in Output records to indicate that the output is	* This field is used in Output records to indicate that the output is
Context not available.
	} __attribute__((packed));	} __attribute__((packed));

	/* hwrm_port_mac_cfg */	/* hwrm_port_mac_cfg */
	/* Description: This command configures the MAC block for the port. */	/*
		* Description: This command configures the MAC block for the port. # Only PF
		* drivers shall be allowed to configure MAC. # A VF driver should not be
		* allowed to configure MAC using this command. # In a network partition mode, a
		* PF driver should not be allowed to configure MAC using this command. The QoS
		* settings in port_mac_cfg() are global for all ports/functions. If multiple PF
		* drivers on different ports are configuring QoS settings, then the HWRM is not
		* responsible for maintaining consistency between them. A PF driver changing
		* global QoS settings using this command may impact other PF drivers on
		* different ports.
		*/
	/* Input (40 bytes) */	/* Input (40 bytes) */

	struct hwrm_port_mac_cfg_input {	struct hwrm_port_mac_cfg_input {
Context not available.
	*/	*/
	uint32_t flags;	uint32_t flags;
	/*	/*
		* In this field, there are a number of CoS mappings related flags that
		* are used to configure CoS mappings and their corresponding priorities
		* in the hardware. For the priorities of CoS mappings, the HWRM uses
		* the following priority order (high to low) by default: # vlan pri #
		* ip_dscp # tunnel_vlan_pri # default cos A subset of CoS mappings can
		* be enabled. If a priority is not specified for an enabled CoS
		* mapping, the priority will be assigned in the above order for the
		* enabled CoS mappings. For example, if vlan_pri and ip_dscp CoS
		* mappings are enabled and their priorities are not specified, the
		* following priority order (high to low) will be used by the HWRM: #
		* vlan_pri # ip_dscp # default cos vlan_pri CoS mapping together with
		* default CoS with lower priority are enabled by default by the HWRM.
		*/
		/*
	* When this bit is '1', this command will configure the MAC to match	* When this bit is '1', this command will configure the MAC to match
	* the current link state of the PHY. If the link is not established on	* the current link state of the PHY. If the link is not established on
	* the PHY, then this bit has no effect.	* the PHY, then this bit has no effect.
	*/	*/
	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK UINT32_C(0x1)	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK UINT32_C(0x1)
	/*	/*
	* When this bit is '1', the CoS assignment logic is enabled. When this	* When this bit is set to '1', the inner VLAN PRI to CoS mapping is
	* logic is enabled, then inner VLAN PRI to CoS mapping is enabled. If	* requested to be enabled.
	* this bit is '0', then the default CoS is used.
	*/	*/
	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_COS_ASSIGNMENT_ENABLE UINT32_C(0x2)	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE UINT32_C(0x2)
	/*	/*
	* When this bit is '1', tunnel or outer VLAN PRI field to CoS mapping	* When this bit is set to '1', tunnel VLAN PRI field to CoS mapping is
	* is enabled. If this bit is '0', then outer VLAN PRI bits are not used	* requested to be enabled.
	* in determining CoS.
	*/	*/
	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE UINT32_C(0x4)	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE UINT32_C(0x4)
	/*	/*
	* When this bit is '1', the IP DSCP to CoS mapping is enabled. If this	* When this bit is set to '1', the IP DSCP to CoS mapping is requested
	* bit is '0', then IP DSCP bits are not used in determining CoS.	* to be enabled.
	*/	*/
	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE UINT32_C(0x8)	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE UINT32_C(0x8)
	/*	/*
Context not available.
	* disabled on this port.	* disabled on this port.
	*/	*/
	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE UINT32_C(0x200)	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE UINT32_C(0x200)
		/*
		* When this bit is set to '1', the inner VLAN PRI to CoS mapping is
		* requested to be disabled.
		*/
		#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE UINT32_C(0x400)
		/*
		* When this bit is set to '1', tunnel VLAN PRI field to CoS mapping is
		* requested to be disabled.
		*/
		#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE UINT32_C(0x800)
		/*
		* When this bit is set to '1', the IP DSCP to CoS mapping is requested
		* to be disabled.
		*/
		#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE UINT32_C(0x1000)
	uint32_t enables;	uint32_t enables;
	/* This bit must be '1' for the ipg field to be configured. */	/* This bit must be '1' for the ipg field to be configured. */
	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG UINT32_C(0x1)	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG UINT32_C(0x1)
	/* This bit must be '1' for the lpbk field to be configured. */	/* This bit must be '1' for the lpbk field to be configured. */
	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK UINT32_C(0x2)	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK UINT32_C(0x2)
	/*	/*
	* This bit must be '1' for the ivlan_pri2cos_map_pri field to be	* This bit must be '1' for the vlan_pri2cos_map_pri field to be
	* configured.	* configured.
	*/	*/
	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IVLAN_PRI2COS_MAP_PRI UINT32_C(0x4)	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI UINT32_C(0x4)
	/* This bit must be '1' for the lcos_map_pri field to be configured. */	/* This bit must be '1' for the Reserved1 field to be configured. */
	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LCOS_MAP_PRI UINT32_C(0x8)	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RESERVED1 UINT32_C(0x8)
	/*	/*
	* This bit must be '1' for the tunnel_pri2cos_map_pri field to be	* This bit must be '1' for the tunnel_pri2cos_map_pri field to be
	* configured.	* configured.
Context not available.
	* configured.	* configured.
	*/	*/
	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x80)	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x80)
		/* This bit must be '1' for the cos_field_cfg field to be configured. */
		#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG UINT32_C(0x100)
	uint16_t port_id;	uint16_t port_id;
	/* Port ID of port that is to be configured. */	/* Port ID of port that is to be configured. */
	uint8_t ipg;	uint8_t ipg;
Context not available.
	* received.	* received.
	*/	*/
	#define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)	#define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
	uint8_t ivlan_pri2cos_map_pri;	uint8_t vlan_pri2cos_map_pri;
	/*	/*
	* This value controls the priority of mapping. Valid values: 1-4 Higher	* This value controls the priority setting of VLAN PRI to CoS mapping
	* the number, higher the priority	* based on VLAN Tags of inner packet headers of tunneled packets or
		* packet headers of non-tunneled packets. # Each XXX_pri variable shall
		* have a unique priority value when it is being specified. # When
		* comparing priorities of mappings, higher value indicates higher
		* priority. For example, a value of 0-3 is returned where 0 is being
		* the lowest priority and 3 is being the highest priority.
	*/	*/
	uint8_t lcos_map_pri;	uint8_t reserved1;
	/*	/* Reserved field */
	* This value controls the priority of mapping. Valid values: 1-4 Higher
	* the number, higher the priority
	*/
	uint8_t tunnel_pri2cos_map_pri;	uint8_t tunnel_pri2cos_map_pri;
	/*	/*
	* This value controls the priority of mapping. Valid values: 1-4 Higher	* This value controls the priority setting of VLAN PRI to CoS mapping
	* the number, higher the priority	* based on VLAN Tags of tunneled header. This mapping only applies when
		* tunneled headers are present. # Each XXX_pri variable shall have a
		* unique priority value when it is being specified. # When comparing
		* priorities of mappings, higher value indicates higher priority. For
		* example, a value of 0-3 is returned where 0 is being the lowest
		* priority and 3 is being the highest priority.
	*/	*/
	uint8_t dscp2pri_map_pri;	uint8_t dscp2pri_map_pri;
	/*	/*
	* This value controls the priority of mapping. Valid values: 1-4 Higher	* This value controls the priority setting of IP DSCP to CoS mapping
	* the number, higher the priority	* based on inner IP header of tunneled packets or IP header of non-
		* tunneled packets. # Each XXX_pri variable shall have a unique
		* priority value when it is being specified. # When comparing
		* priorities of mappings, higher value indicates higher priority. For
		* example, a value of 0-3 is returned where 0 is being the lowest
		* priority and 3 is being the highest priority.
	*/	*/
	uint16_t rx_ts_capture_ptp_msg_type;	uint16_t rx_ts_capture_ptp_msg_type;
	/*	/*
Context not available.
	* transmit sied of the port to capture the time stamp of every	* transmit sied of the port to capture the time stamp of every
	* transmitted PTP message with messageType field value set to i.	* transmitted PTP message with messageType field value set to i.
	*/	*/
	uint32_t unused_0;	uint8_t cos_field_cfg;
		/* Configuration of CoS fields. */
		/* Reserved. */
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 UINT32_C(0x1)
		/*
		* This field is used to specify selection of VLAN PRI value based on
		* whether one or two VLAN Tags are present in the inner packet headers
		* of tunneled packets or non-tunneled packets. This field is valid only
		* if inner VLAN PRI to CoS mapping is enabled. If VLAN PRI to CoS
		* mapping is not enabled, then this field shall be ignored.
		*/
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK UINT32_C(0x6)
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
		/*
		* Select inner VLAN PRI when 1 or 2 VLAN Tags are present in
		* the inner packet headers
		*/
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 1)
		/*
		* Select outer VLAN Tag PRI when 2 VLAN Tags are present in the
		* inner packet headers. No VLAN PRI shall be selected for this
		* configuration if only one VLAN Tag is present in the inner
		* packet headers.
		*/
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 1)
		/*
		* Select outermost VLAN PRI when 1 or 2 VLAN Tags are present
		* in the inner packet headers
		*/
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 1)
		/* Unspecified */
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 1)
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
		/*
		* This field is used to specify selection of tunnel VLAN PRI value
		* based on whether one or two VLAN Tags are present in tunnel headers.
		* This field is valid only if tunnel VLAN PRI to CoS mapping is
		* enabled. If tunnel VLAN PRI to CoS mapping is not enabled, then this
		* field shall be ignored.
		*/
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK UINT32_C(0x18)
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
		/*
		* Select inner VLAN PRI when 1 or 2 VLAN Tags are present in
		* the tunnel packet headers
		*/
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 3)
		/*
		* Select outer VLAN Tag PRI when 2 VLAN Tags are present in the
		* tunnel packet headers. No tunnel VLAN PRI shall be selected
		* for this configuration if only one VLAN Tag is present in the
		* tunnel packet headers.
		*/
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 3)
		/*
		* Select outermost VLAN PRI when 1 or 2 VLAN Tags are present
		* in the tunnel packet headers
		*/
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 3)
		/* Unspecified */
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 3)
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
		/*
		* This field shall be used to provide default CoS value that has been
		* configured on this port. This field is valid only if default CoS
		* mapping is enabled. If default CoS mapping is not enabled, then this
		* field shall be ignored.
		*/
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK UINT32_C(0xe0)
		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT 5
		uint8_t unused_0[3];
	} __attribute__((packed));	} __attribute__((packed));

	/* Output (16 bytes) */	/* Output (16 bytes) */
Context not available.
	* received.	* received.
	*/	*/
	#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)	#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
	uint8_t ivlan_pri2cos_map_pri;	uint8_t vlan_pri2cos_map_pri;
	/*	/*
	* Priority of pri to CoS mapping. Valid values: 1-4 Higher the number,	* Priority setting for VLAN PRI to CoS mapping. # Each XXX_pri variable
	* higher the priority Value 0 indicates that this mapping is not used.	* shall have a unique priority value when it is being used. # When
		* comparing priorities of mappings, higher value indicates higher
		* priority. For example, a value of 0-3 is returned where 0 is being
		* the lowest priority and 3 is being the highest priority. # If the
		* correspoding CoS mapping is not enabled, then this field should be
		* ignored. # This value indicates the normalized priority value
		* retained in the HWRM.
	*/	*/
	uint8_t lcos_map_pri;	uint8_t flags;
	/*	/*
	* Priority of local CoS to PRI mapping. Valid values: 1-4 Higher the	* In this field, a number of CoS mappings related flags are used to
	* number, higher the priority Value 0 indicates that this mapping is	* indicate configured CoS mappings.
	* not used.
	*/	*/
		/*
		* When this bit is set to '1', the inner VLAN PRI to CoS mapping is
		* enabled.
		*/
		#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE UINT32_C(0x1)
		/*
		* When this bit is set to '1', tunnel VLAN PRI field to CoS mapping is
		* enabled.
		*/
		#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE UINT32_C(0x2)
		/* When this bit is set to '1', the IP DSCP to CoS mapping is enabled. */
		#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE UINT32_C(0x4)
		/* When this bit is '1', the Out-Of-Box WoL is enabled on this port. */
		#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE UINT32_C(0x8)
		/* When this bit is '1', PTP is enabled for RX on this port. */
		#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE UINT32_C(0x10)
		/* When this bit is '1', PTP is enabled for TX on this port. */
		#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE UINT32_C(0x20)
	uint8_t tunnel_pri2cos_map_pri;	uint8_t tunnel_pri2cos_map_pri;
	/*	/*
	* Priority of tunnel PRI to CoS mapping. Valid values: 1-4 Higher the	* Priority setting for tunnel VLAN PRI to CoS mapping. # Each XXX_pri
	* number, higher the priority Value 0 indicates that this mapping is	* variable shall have a unique priority value when it is being used. #
	* not used.	* When comparing priorities of mappings, higher value indicates higher
		* priority. For example, a value of 0-3 is returned where 0 is being
		* the lowest priority and 3 is being the highest priority. # If the
		* correspoding CoS mapping is not enabled, then this field should be
		* ignored. # This value indicates the normalized priority value
		* retained in the HWRM.
	*/	*/
	uint8_t dscp2pri_map_pri;	uint8_t dscp2pri_map_pri;
	/*	/*
	* Priority of DSCP to PRI mapping. Valid values: 1-4 Higher the number,	* Priority setting for DSCP to PRI mapping. # Each XXX_pri variable
	* higher the priority Value 0 indicates that this mapping is not used.	* shall have a unique priority value when it is being used. # When
		* comparing priorities of mappings, higher value indicates higher
		* priority. For example, a value of 0-3 is returned where 0 is being
		* the lowest priority and 3 is being the highest priority. # If the
		* correspoding CoS mapping is not enabled, then this field should be
		* ignored. # This value indicates the normalized priority value
		* retained in the HWRM.
	*/	*/
	uint16_t rx_ts_capture_ptp_msg_type;	uint16_t rx_ts_capture_ptp_msg_type;
	/*	/*
Context not available.
	* to 1, then the transmit side of the port is configured to capture	* to 1, then the transmit side of the port is configured to capture
	* timestamp for all PTP messages.	* timestamp for all PTP messages.
	*/	*/
		uint8_t cos_field_cfg;
		/* Configuration of CoS fields. */
		/* Reserved */
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD UINT32_C(0x1)
		/*
		* This field is used for selecting VLAN PRI value based on whether one
		* or two VLAN Tags are present in the inner packet headers of tunneled
		* packets or non-tunneled packets.
		*/
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK UINT32_C(0x6)
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
		/*
		* Select inner VLAN PRI when 1 or 2 VLAN Tags are present in
		* the inner packet headers
		*/
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 1)
		/*
		* Select outer VLAN Tag PRI when 2 VLAN Tags are present in the
		* inner packet headers. No VLAN PRI is selected for this
		* configuration if only one VLAN Tag is present in the inner
		* packet headers.
		*/
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 1)
		/*
		* Select outermost VLAN PRI when 1 or 2 VLAN Tags are present
		* in the inner packet headers
		*/
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 1)
		/* Unspecified */
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 1)
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
		/*
		* This field is used for selecting tunnel VLAN PRI value based on
		* whether one or two VLAN Tags are present in the tunnel headers of
		* tunneled packets. This selection does not apply to non-tunneled
		* packets.
		*/
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK UINT32_C(0x18)
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
		/*
		* Select inner VLAN PRI when 1 or 2 VLAN Tags are present in
		* the tunnel packet headers
		*/
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 3)
		/*
		* Select outer VLAN Tag PRI when 2 VLAN Tags are present in the
		* tunnel packet headers. No VLAN PRI is selected for this
		* configuration if only one VLAN Tag is present in the tunnel
		* packet headers.
		*/
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 3)
		/*
		* Select outermost VLAN PRI when 1 or 2 VLAN Tags are present
		* in the tunnel packet headers
		*/
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 3)
		/* Unspecified */
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 3)
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
		/*
		* This field is used to provide default CoS value that has been
		* configured on this port.
		*/
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK UINT32_C(0xe0)
		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT 5
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_port_mac_ptp_qcfg */
		/* Description: This command queries the PTP information for the port. */
		/* Input (24 bytes) */

		struct hwrm_port_mac_ptp_qcfg_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t port_id;
		/* Port ID of port that is being queried. */
		uint16_t unused_0[3];
		} __attribute__((packed));

		/* Output (80 bytes) */

		struct hwrm_port_mac_ptp_qcfg_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint8_t flags;
		/*
		* In this field, a number of PTP related flags are used to indicate
		* configured PTP capabilities.
		*/
		/*
		* When this bit is set to '1', the PTP related registers are directly
		* accessible by the host.
		*/
		#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS UINT32_C(0x1)
		/*
		* When this bit is set to '1', the PTP information is accessible via
		* HWRM commands.
		*/
		#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS UINT32_C(0x2)
	uint8_t unused_0;	uint8_t unused_0;
		uint16_t unused_1;
		uint32_t rx_ts_reg_off_lower;
		/* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
		uint32_t rx_ts_reg_off_upper;
		/* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
		uint32_t rx_ts_reg_off_seq_id;
		/* Offset of the PTP register for the sequence ID for RX. */
		uint32_t rx_ts_reg_off_src_id_0;
		/* Offset of the first PTP source ID for RX. */
		uint32_t rx_ts_reg_off_src_id_1;
		/* Offset of the second PTP source ID for RX. */
		uint32_t rx_ts_reg_off_src_id_2;
		/* Offset of the third PTP source ID for RX. */
		uint32_t rx_ts_reg_off_domain_id;
		/* Offset of the domain ID for RX. */
		uint32_t rx_ts_reg_off_fifo;
		/* Offset of the PTP FIFO register for RX. */
		uint32_t rx_ts_reg_off_fifo_adv;
		/* Offset of the PTP advance FIFO register for RX. */
		uint32_t rx_ts_reg_off_granularity;
		/* PTP timestamp granularity for RX. */
		uint32_t tx_ts_reg_off_lower;
		/* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
		uint32_t tx_ts_reg_off_upper;
		/* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
		uint32_t tx_ts_reg_off_seq_id;
		/* Offset of the PTP register for the sequence ID for TX. */
		uint32_t tx_ts_reg_off_fifo;
		/* Offset of the PTP FIFO register for TX. */
		uint32_t tx_ts_reg_off_granularity;
		/* PTP timestamp granularity for TX. */
		uint32_t unused_2;
		uint8_t unused_3;
		uint8_t unused_4;
		uint8_t unused_5;
	uint8_t valid;	uint8_t valid;
	/*	/*
	* This field is used in Output records to indicate that the output is	* This field is used in Output records to indicate that the output is
Context not available.
	*/	*/
	} __attribute__((packed));	} __attribute__((packed));

	/* hwrm_port_blink_led */
	/*
	* Description: This function blinks the port LED for the specified number of
	* times.
	*/
	/* Input (24 bytes) */

	struct hwrm_port_blink_led_input {
	uint16_t req_type;
	/*
	* This value indicates what type of request this is. The format for the
	* rest of the command is determined by this field.
	*/
	uint16_t cmpl_ring;
	/*
	* This value indicates the what completion ring the request will be
	* optionally completed on. If the value is -1, then no CR completion
	* will be generated. Any other value must be a valid CR ring_id value
	* for this function.
	*/
	uint16_t seq_id;
	/* This value indicates the command sequence number. */
	uint16_t target_id;
	/*
	* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
	* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
	*/
	uint64_t resp_addr;
	/*
	* This is the host address where the response will be written when the
	* request is complete. This area must be 16B aligned and must be
	* cleared to zero before the request is made.
	*/
	uint32_t num_blinks;
	/* Number of blinks. */
	uint32_t unused_0;
	} __attribute__((packed));

	/* Output (16 bytes) */

	struct hwrm_port_blink_led_output {
	uint16_t error_code;
	/*
	* Pass/Fail or error type Note: receiver to verify the in parameters,
	* and fail the call with an error when appropriate
	*/
	uint16_t req_type;
	/* This field returns the type of original request. */
	uint16_t seq_id;
	/* This field provides original sequence number of the command. */
	uint16_t resp_len;
	/*
	* This field is the length of the response in bytes. The last byte of
	* the response is a valid flag that will read as '1' when the command
	* has been completely written to memory.
	*/
	uint32_t unused_0;
	uint8_t unused_1;
	uint8_t unused_2;
	uint8_t unused_3;
	uint8_t valid;
	/*
	* This field is used in Output records to indicate that the output is
	* completely written to RAM. This field should be read as '1' to
	* indicate that the output has been completely written. When writing a
	* command completion or response to an internal processor, the order of
	* writes has to be such that this field is written last.
	*/
	} __attribute__((packed));

	/* hwrm_port_ts_query */	/* hwrm_port_ts_query */
	/*	/*
	* Description: This function is used to read timestamp information captured for	* Description: This function is used to read timestamp information captured for
Context not available.
	* the response is a valid flag that will read as '1' when the command	* the response is a valid flag that will read as '1' when the command
	* has been completely written to memory.	* has been completely written to memory.
	*/	*/
	uint8_t eee_supported;	uint8_t flags;
		/* PHY capability flags */
	/*	/*
	* Reserved field. The HWRM shall set this field to 0. An HWRM client
	* shall ignore this field.
	*/
	/*
	* If set to 1, then this field indicates that the link is capable of	* If set to 1, then this field indicates that the link is capable of
	* supporting EEE.	* supporting EEE.
	*/	*/
	#define HWRM_PORT_PHY_QCAPS_OUTPUT_EEE_SUPPORTED UINT32_C(0x1)	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED UINT32_C(0x1)
	/*	/*
	* Reserved field. The HWRM shall set this field to 0. An HWRM client	* Reserved field. The HWRM shall set this field to 0. An HWRM client
	* shall ignore this field.	* shall ignore this field.
	*/	*/
	#define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD1_MASK UINT32_C(0xfe)	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK UINT32_C(0xfe)
	#define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD1_SFT 1	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 1
	uint8_t unused_0;	uint8_t port_cnt;
		/* Number of front panel ports for this device. */
		/* Not supported or unknown */
		#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
		/* single port device */
		#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
		/* 2-port device */
		#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
		/* 3-port device */
		#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
		/* 4-port device */
		#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
	uint16_t supported_speeds_force_mode;	uint16_t supported_speeds_force_mode;
	/*	/*
	* This is a bit mask to indicate what speeds are supported as forced	* This is a bit mask to indicate what speeds are supported as forced
Context not available.
	#define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24	#define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
	} __attribute__((packed));	} __attribute__((packed));

		/* hwrm_port_phy_i2c_write */
		/* Note: Write data at a specific location addressable on PHY I2C bus. */
		/* Input (48 bytes) */

		struct hwrm_port_phy_i2c_write_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint32_t flags;
		uint32_t enables;
		/* This bit must be '1' for the page_offset field to be configured. */
		#define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_PAGE_OFFSET UINT32_C(0x1)
		uint16_t port_id;
		/* Port ID of port. */
		uint8_t i2c_slave_addr;
		/* 8-bit I2C slave address. */
		uint8_t unused_0;
		uint16_t page_number;
		/* The page number that is being accessed over I2C. */
		uint16_t page_offset;
		/* Offset within the page that is being accessed over I2C. */
		uint8_t data_length;
		/*
		* Length of data to write, in bytes starting at the offset specified
		* above. If the offset is not specified, then the data shall be written
		* from the beginning of the page.
		*/
		uint8_t unused_1;
		uint16_t unused_2;
		uint16_t unused_3;
		uint16_t unused_4;
		uint32_t data[16];
		/* Up to 64B of data. */
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_port_phy_i2c_write_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_port_phy_i2c_read */
		/* Note: Write data at a specific location addressable on PHY I2C bus. */
		/* Input (40 bytes) */

		struct hwrm_port_phy_i2c_read_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint32_t flags;
		uint32_t enables;
		/* This bit must be '1' for the page_offset field to be configured. */
		#define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET UINT32_C(0x1)
		uint16_t port_id;
		/* Port ID of port. */
		uint8_t i2c_slave_addr;
		/* 8-bit I2C slave address. */
		uint8_t unused_0;
		uint16_t page_number;
		/* The page number that is being accessed over I2C. */
		uint16_t page_offset;
		/* Offset within the page that is being accessed over I2C. */
		uint8_t data_length;
		/*
		* Length of data to read, in bytes starting at the offset specified
		* above. If the offset is not specified, then the data shall be read
		* from the beginning of the page.
		*/
		uint8_t unused_1[7];
		} __attribute__((packed));

		/* Output (80 bytes) */

		struct hwrm_port_phy_i2c_read_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t data[16];
		/* Up to 64B of data. */
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_port_led_cfg */
		/*
		* Description: This function is used to configure LEDs on a given port. Each
		* port has individual set of LEDs associated with it. These LEDs are used for
		* speed/link configuration as well as activity indicator configuration. Up to
		* three LEDs can be configured, one for activity and two for speeds.
		*/
		/* Input (64 bytes) */

		struct hwrm_port_led_cfg_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint32_t enables;
		/* This bit must be '1' for the led0_id field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID UINT32_C(0x1)
		/* This bit must be '1' for the led0_state field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE UINT32_C(0x2)
		/* This bit must be '1' for the led0_color field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR UINT32_C(0x4)
		/* This bit must be '1' for the led0_blink_on field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON UINT32_C(0x8)
		/* This bit must be '1' for the led0_blink_off field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF UINT32_C(0x10)
		/* This bit must be '1' for the led0_group_id field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID UINT32_C(0x20)
		/* This bit must be '1' for the led1_id field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID UINT32_C(0x40)
		/* This bit must be '1' for the led1_state field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE UINT32_C(0x80)
		/* This bit must be '1' for the led1_color field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR UINT32_C(0x100)
		/* This bit must be '1' for the led1_blink_on field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON UINT32_C(0x200)
		/* This bit must be '1' for the led1_blink_off field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF UINT32_C(0x400)
		/* This bit must be '1' for the led1_group_id field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID UINT32_C(0x800)
		/* This bit must be '1' for the led2_id field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID UINT32_C(0x1000)
		/* This bit must be '1' for the led2_state field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE UINT32_C(0x2000)
		/* This bit must be '1' for the led2_color field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR UINT32_C(0x4000)
		/* This bit must be '1' for the led2_blink_on field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON UINT32_C(0x8000)
		/* This bit must be '1' for the led2_blink_off field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF UINT32_C(0x10000)
		/* This bit must be '1' for the led2_group_id field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID UINT32_C(0x20000)
		/* This bit must be '1' for the led3_id field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID UINT32_C(0x40000)
		/* This bit must be '1' for the led3_state field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE UINT32_C(0x80000)
		/* This bit must be '1' for the led3_color field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR UINT32_C(0x100000)
		/* This bit must be '1' for the led3_blink_on field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON UINT32_C(0x200000)
		/* This bit must be '1' for the led3_blink_off field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF UINT32_C(0x400000)
		/* This bit must be '1' for the led3_group_id field to be configured. */
		#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID UINT32_C(0x800000)
		uint16_t port_id;
		/* Port ID of port whose LEDs are configured. */
		uint8_t num_leds;
		/*
		* The number of LEDs that are being configured. Up to 4 LEDs can be
		* configured with this command.
		*/
		uint8_t rsvd;
		/* Reserved field. */
		uint8_t led0_id;
		/* An identifier for the LED #0. */
		uint8_t led0_state;
		/* The requested state of the LED #0. */
		/* Default state of the LED */
		#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
		/* Off */
		#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
		/* On */
		#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
		/* Blink */
		#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
		/* Blink Alternately */
		#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
		uint8_t led0_color;
		/* The requested color of LED #0. */
		/* Default */
		#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
		/* Amber */
		#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
		/* Green */
		#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
		/* Green or Amber */
		#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
		uint8_t unused_0;
		uint16_t led0_blink_on;
		/*
		* If the LED #0 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED on between
		* cycles.
		*/
		uint16_t led0_blink_off;
		/*
		* If the LED #0 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED off between
		* cycles.
		*/
		uint8_t led0_group_id;
		/*
		* An identifier for the group of LEDs that LED #0 belongs to. If set to
		* 0, then the LED #0 shall not be grouped and shall be treated as an
		* individual resource. For all other non-zero values of this field, LED
		* #0 shall be grouped together with the LEDs with the same group ID
		* value.
		*/
		uint8_t rsvd0;
		/* Reserved field. */
		uint8_t led1_id;
		/* An identifier for the LED #1. */
		uint8_t led1_state;
		/* The requested state of the LED #1. */
		/* Default state of the LED */
		#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
		/* Off */
		#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
		/* On */
		#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
		/* Blink */
		#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
		/* Blink Alternately */
		#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
		uint8_t led1_color;
		/* The requested color of LED #1. */
		/* Default */
		#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
		/* Amber */
		#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
		/* Green */
		#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
		/* Green or Amber */
		#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
		uint8_t unused_1;
		uint16_t led1_blink_on;
		/*
		* If the LED #1 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED on between
		* cycles.
		*/
		uint16_t led1_blink_off;
		/*
		* If the LED #1 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED off between
		* cycles.
		*/
		uint8_t led1_group_id;
		/*
		* An identifier for the group of LEDs that LED #1 belongs to. If set to
		* 0, then the LED #1 shall not be grouped and shall be treated as an
		* individual resource. For all other non-zero values of this field, LED
		* #1 shall be grouped together with the LEDs with the same group ID
		* value.
		*/
		uint8_t rsvd1;
		/* Reserved field. */
		uint8_t led2_id;
		/* An identifier for the LED #2. */
		uint8_t led2_state;
		/* The requested state of the LED #2. */
		/* Default state of the LED */
		#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
		/* Off */
		#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
		/* On */
		#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
		/* Blink */
		#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
		/* Blink Alternately */
		#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
		uint8_t led2_color;
		/* The requested color of LED #2. */
		/* Default */
		#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
		/* Amber */
		#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
		/* Green */
		#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
		/* Green or Amber */
		#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
		uint8_t unused_2;
		uint16_t led2_blink_on;
		/*
		* If the LED #2 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED on between
		* cycles.
		*/
		uint16_t led2_blink_off;
		/*
		* If the LED #2 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED off between
		* cycles.
		*/
		uint8_t led2_group_id;
		/*
		* An identifier for the group of LEDs that LED #2 belongs to. If set to
		* 0, then the LED #2 shall not be grouped and shall be treated as an
		* individual resource. For all other non-zero values of this field, LED
		* #2 shall be grouped together with the LEDs with the same group ID
		* value.
		*/
		uint8_t rsvd2;
		/* Reserved field. */
		uint8_t led3_id;
		/* An identifier for the LED #3. */
		uint8_t led3_state;
		/* The requested state of the LED #3. */
		/* Default state of the LED */
		#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
		/* Off */
		#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
		/* On */
		#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
		/* Blink */
		#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
		/* Blink Alternately */
		#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
		uint8_t led3_color;
		/* The requested color of LED #3. */
		/* Default */
		#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
		/* Amber */
		#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
		/* Green */
		#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
		/* Green or Amber */
		#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
		uint8_t unused_3;
		uint16_t led3_blink_on;
		/*
		* If the LED #3 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED on between
		* cycles.
		*/
		uint16_t led3_blink_off;
		/*
		* If the LED #3 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED off between
		* cycles.
		*/
		uint8_t led3_group_id;
		/*
		* An identifier for the group of LEDs that LED #3 belongs to. If set to
		* 0, then the LED #3 shall not be grouped and shall be treated as an
		* individual resource. For all other non-zero values of this field, LED
		* #3 shall be grouped together with the LEDs with the same group ID
		* value.
		*/
		uint8_t rsvd3;
		/* Reserved field. */
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_port_led_cfg_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_port_led_qcfg */
		/*
		* Description: This function is used to query configuration of LEDs on a given
		* port. Each port has individual set of LEDs associated with it. These LEDs are
		* used for speed/link configuration as well as activity indicator
		* configuration. Up to three LEDs can be configured, one for activity and two
		* for speeds.
		*/
		/* Input (24 bytes) */

		struct hwrm_port_led_qcfg_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t port_id;
		/* Port ID of port whose LED configuration is being queried. */
		uint16_t unused_0[3];
		} __attribute__((packed));

		/* Output (56 bytes) */

		struct hwrm_port_led_qcfg_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint8_t num_leds;
		/*
		* The number of LEDs that are configured on this port. Up to 4 LEDs can
		* be returned in the response.
		*/
		uint8_t led0_id;
		/* An identifier for the LED #0. */
		uint8_t led0_type;
		/* The type of LED #0. */
		/* Speed LED */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
		/* Activity LED */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
		/* Invalid */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
		uint8_t led0_state;
		/* The current state of the LED #0. */
		/* Default state of the LED */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
		/* Off */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
		/* On */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
		/* Blink */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
		/* Blink Alternately */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
		uint8_t led0_color;
		/* The color of LED #0. */
		/* Default */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
		/* Amber */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
		/* Green */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
		/* Green or Amber */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
		uint8_t unused_0;
		uint16_t led0_blink_on;
		/*
		* If the LED #0 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED on between
		* cycles.
		*/
		uint16_t led0_blink_off;
		/*
		* If the LED #0 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED off between
		* cycles.
		*/
		uint8_t led0_group_id;
		/*
		* An identifier for the group of LEDs that LED #0 belongs to. If set to
		* 0, then the LED #0 is not grouped. For all other non-zero values of
		* this field, LED #0 is grouped together with the LEDs with the same
		* group ID value.
		*/
		uint8_t led1_id;
		/* An identifier for the LED #1. */
		uint8_t led1_type;
		/* The type of LED #1. */
		/* Speed LED */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
		/* Activity LED */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
		/* Invalid */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
		uint8_t led1_state;
		/* The current state of the LED #1. */
		/* Default state of the LED */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
		/* Off */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
		/* On */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
		/* Blink */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
		/* Blink Alternately */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
		uint8_t led1_color;
		/* The color of LED #1. */
		/* Default */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
		/* Amber */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
		/* Green */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
		/* Green or Amber */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
		uint8_t unused_1;
		uint16_t led1_blink_on;
		/*
		* If the LED #1 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED on between
		* cycles.
		*/
		uint16_t led1_blink_off;
		/*
		* If the LED #1 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED off between
		* cycles.
		*/
		uint8_t led1_group_id;
		/*
		* An identifier for the group of LEDs that LED #1 belongs to. If set to
		* 0, then the LED #1 is not grouped. For all other non-zero values of
		* this field, LED #1 is grouped together with the LEDs with the same
		* group ID value.
		*/
		uint8_t led2_id;
		/* An identifier for the LED #2. */
		uint8_t led2_type;
		/* The type of LED #2. */
		/* Speed LED */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
		/* Activity LED */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
		/* Invalid */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
		uint8_t led2_state;
		/* The current state of the LED #2. */
		/* Default state of the LED */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
		/* Off */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
		/* On */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
		/* Blink */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
		/* Blink Alternately */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
		uint8_t led2_color;
		/* The color of LED #2. */
		/* Default */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
		/* Amber */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
		/* Green */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
		/* Green or Amber */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
		uint8_t unused_2;
		uint16_t led2_blink_on;
		/*
		* If the LED #2 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED on between
		* cycles.
		*/
		uint16_t led2_blink_off;
		/*
		* If the LED #2 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED off between
		* cycles.
		*/
		uint8_t led2_group_id;
		/*
		* An identifier for the group of LEDs that LED #2 belongs to. If set to
		* 0, then the LED #2 is not grouped. For all other non-zero values of
		* this field, LED #2 is grouped together with the LEDs with the same
		* group ID value.
		*/
		uint8_t led3_id;
		/* An identifier for the LED #3. */
		uint8_t led3_type;
		/* The type of LED #3. */
		/* Speed LED */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
		/* Activity LED */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
		/* Invalid */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
		uint8_t led3_state;
		/* The current state of the LED #3. */
		/* Default state of the LED */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
		/* Off */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
		/* On */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
		/* Blink */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
		/* Blink Alternately */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
		uint8_t led3_color;
		/* The color of LED #3. */
		/* Default */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
		/* Amber */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
		/* Green */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
		/* Green or Amber */
		#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
		uint8_t unused_3;
		uint16_t led3_blink_on;
		/*
		* If the LED #3 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED on between
		* cycles.
		*/
		uint16_t led3_blink_off;
		/*
		* If the LED #3 state is "blink" or "blinkalt", then this field
		* represents the requested time in milliseconds to keep LED off between
		* cycles.
		*/
		uint8_t led3_group_id;
		/*
		* An identifier for the group of LEDs that LED #3 belongs to. If set to
		* 0, then the LED #3 is not grouped. For all other non-zero values of
		* this field, LED #3 is grouped together with the LEDs with the same
		* group ID value.
		*/
		uint8_t unused_4;
		uint16_t unused_5;
		uint8_t unused_6;
		uint8_t unused_7;
		uint8_t unused_8;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_port_led_qcaps */
		/*
		* Description: This function is used to query capabilities of LEDs on a given
		* port. Each port has individual set of LEDs associated with it. These LEDs are
		* used for speed/link configuration as well as activity indicator
		* configuration.
		*/
		/* Input (24 bytes) */

		struct hwrm_port_led_qcaps_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t port_id;
		/* Port ID of port whose LED configuration is being queried. */
		uint16_t unused_0[3];
		} __attribute__((packed));

		/* Output (48 bytes) */

		struct hwrm_port_led_qcaps_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint8_t num_leds;
		/*
		* The number of LEDs that are configured on this port. Up to 4 LEDs can
		* be returned in the response.
		*/
		uint8_t unused_0[3];
		/* Reserved for future use. */
		uint8_t led0_id;
		/* An identifier for the LED #0. */
		uint8_t led0_type;
		/* The type of LED #0. */
		/* Speed LED */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
		/* Activity LED */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
		/* Invalid */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
		uint8_t led0_group_id;
		/*
		* An identifier for the group of LEDs that LED #0 belongs to. If set to
		* 0, then the LED #0 cannot be grouped. For all other non-zero values
		* of this field, LED #0 is grouped together with the LEDs with the same
		* group ID value.
		*/
		uint8_t unused_1;
		uint16_t led0_state_caps;
		/* The states supported by LED #0. */
		/* If set to 1, this LED is enabled. If set to 0, this LED is disabled. */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED UINT32_C(0x1)
		/*
		* If set to 1, off state is supported on this LED. If set to 0, off
		* state is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
		/*
		* If set to 1, on state is supported on this LED. If set to 0, on state
		* is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
		/*
		* If set to 1, blink state is supported on this LED. If set to 0, blink
		* state is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
		/*
		* If set to 1, blink_alt state is supported on this LED. If set to 0,
		* blink_alt state is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
		uint16_t led0_color_caps;
		/* The colors supported by LED #0. */
		/* reserved */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD UINT32_C(0x1)
		/*
		* If set to 1, Amber color is supported on this LED. If set to 0, Amber
		* color is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
		/*
		* If set to 1, Green color is supported on this LED. If set to 0, Green
		* color is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
		uint8_t led1_id;
		/* An identifier for the LED #1. */
		uint8_t led1_type;
		/* The type of LED #1. */
		/* Speed LED */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
		/* Activity LED */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
		/* Invalid */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
		uint8_t led1_group_id;
		/*
		* An identifier for the group of LEDs that LED #1 belongs to. If set to
		* 0, then the LED #0 cannot be grouped. For all other non-zero values
		* of this field, LED #0 is grouped together with the LEDs with the same
		* group ID value.
		*/
		uint8_t unused_2;
		uint16_t led1_state_caps;
		/* The states supported by LED #1. */
		/* If set to 1, this LED is enabled. If set to 0, this LED is disabled. */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED UINT32_C(0x1)
		/*
		* If set to 1, off state is supported on this LED. If set to 0, off
		* state is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
		/*
		* If set to 1, on state is supported on this LED. If set to 0, on state
		* is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
		/*
		* If set to 1, blink state is supported on this LED. If set to 0, blink
		* state is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
		/*
		* If set to 1, blink_alt state is supported on this LED. If set to 0,
		* blink_alt state is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
		uint16_t led1_color_caps;
		/* The colors supported by LED #1. */
		/* reserved */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD UINT32_C(0x1)
		/*
		* If set to 1, Amber color is supported on this LED. If set to 0, Amber
		* color is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
		/*
		* If set to 1, Green color is supported on this LED. If set to 0, Green
		* color is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
		uint8_t led2_id;
		/* An identifier for the LED #2. */
		uint8_t led2_type;
		/* The type of LED #2. */
		/* Speed LED */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
		/* Activity LED */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
		/* Invalid */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
		uint8_t led2_group_id;
		/*
		* An identifier for the group of LEDs that LED #0 belongs to. If set to
		* 0, then the LED #0 cannot be grouped. For all other non-zero values
		* of this field, LED #0 is grouped together with the LEDs with the same
		* group ID value.
		*/
		uint8_t unused_3;
		uint16_t led2_state_caps;
		/* The states supported by LED #2. */
		/* If set to 1, this LED is enabled. If set to 0, this LED is disabled. */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED UINT32_C(0x1)
		/*
		* If set to 1, off state is supported on this LED. If set to 0, off
		* state is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
		/*
		* If set to 1, on state is supported on this LED. If set to 0, on state
		* is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
		/*
		* If set to 1, blink state is supported on this LED. If set to 0, blink
		* state is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
		/*
		* If set to 1, blink_alt state is supported on this LED. If set to 0,
		* blink_alt state is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
		uint16_t led2_color_caps;
		/* The colors supported by LED #2. */
		/* reserved */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD UINT32_C(0x1)
		/*
		* If set to 1, Amber color is supported on this LED. If set to 0, Amber
		* color is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
		/*
		* If set to 1, Green color is supported on this LED. If set to 0, Green
		* color is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
		uint8_t led3_id;
		/* An identifier for the LED #3. */
		uint8_t led3_type;
		/* The type of LED #3. */
		/* Speed LED */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
		/* Activity LED */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
		/* Invalid */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
		uint8_t led3_group_id;
		/*
		* An identifier for the group of LEDs that LED #3 belongs to. If set to
		* 0, then the LED #0 cannot be grouped. For all other non-zero values
		* of this field, LED #0 is grouped together with the LEDs with the same
		* group ID value.
		*/
		uint8_t unused_4;
		uint16_t led3_state_caps;
		/* The states supported by LED #3. */
		/* If set to 1, this LED is enabled. If set to 0, this LED is disabled. */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED UINT32_C(0x1)
		/*
		* If set to 1, off state is supported on this LED. If set to 0, off
		* state is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
		/*
		* If set to 1, on state is supported on this LED. If set to 0, on state
		* is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
		/*
		* If set to 1, blink state is supported on this LED. If set to 0, blink
		* state is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
		/*
		* If set to 1, blink_alt state is supported on this LED. If set to 0,
		* blink_alt state is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
		uint16_t led3_color_caps;
		/* The colors supported by LED #3. */
		/* reserved */
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD UINT32_C(0x1)
		/*
		* If set to 1, Amber color is supported on this LED. If set to 0, Amber
		* color is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
		/*
		* If set to 1, Green color is supported on this LED. If set to 0, Green
		* color is not supported on this LED.
		*/
		#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
		uint8_t unused_5;
		uint8_t unused_6;
		uint8_t unused_7;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

	/* hwrm_queue_qportcfg */	/* hwrm_queue_qportcfg */
	/*	/*
	* Description: This function is called by a driver to query queue configuration	* Description: This function is called by a driver to query queue configuration
Context not available.
	* has been completely written to memory.	* has been completely written to memory.
	*/	*/
	uint8_t max_configurable_queues;	uint8_t max_configurable_queues;
	/* The maximum number of queues that can be configured. */	/*
		* The maximum number of queues that can be configured on this port.
		* Valid values range from 1 through 8.
		*/
	uint8_t max_configurable_lossless_queues;	uint8_t max_configurable_lossless_queues;
	/* The maximum number of lossless queues that can be configured. */	/*
		* The maximum number of lossless queues that can be configured on this
		* port. Valid values range from 0 through 8.
		*/
	uint8_t queue_cfg_allowed;	uint8_t queue_cfg_allowed;
	/*	/*
	* 0 - Not allowed. Non-zero - Allowed. If this value is non-zero, then	* Bitmask indicating which queues can be configured by the
	* the HWRM shall allow the host SW driver to configure queues using	* hwrm_queue_cfg command. Each bit represents a specific queue where
	* hwrm_queue_cfg.	* bit 0 represents queue 0 and bit 7 represents queue 7. # A value of 0
		* indicates that the queue is not configurable by the hwrm_queue_cfg
		* command. # A value of 1 indicates that the queue is configurable. # A
		* hwrm_queue_cfg command shall return error when trying to configure a
		* queue not configurable.
	*/	*/
	uint8_t queue_buffers_cfg_allowed;	uint8_t queue_cfg_info;
		/* Information about queue configuration. */
	/*	/*
	* 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then	* If this flag is set to '1', then the queues are configured
	* the HWRM shall allow the host SW driver to configure queue buffers	* asymmetrically on TX and RX sides. If this flag is set to '0', then
	* using hwrm_queue_buffers_cfg.	* the queues are configured symmetrically on TX and RX sides. For
		* symmetric configuration, the queue configuration including queue ids
		* and service profiles on the TX side is the same as the corresponding
		* queue configuration on the RX side.
	*/	*/
		#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG UINT32_C(0x1)
	uint8_t queue_pfcenable_cfg_allowed;	uint8_t queue_pfcenable_cfg_allowed;
	/*	/*
	* 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then	* Bitmask indicating which queues can be configured by the
	* the HWRM shall allow the host SW driver to configure PFC using	* hwrm_queue_pfcenable_cfg command. Each bit represents a specific
	* hwrm_queue_pfcenable_cfg.	* priority where bit 0 represents priority 0 and bit 7 represents
		* priority 7. # A value of 0 indicates that the priority is not
		* configurable by the hwrm_queue_pfcenable_cfg command. # A value of 1
		* indicates that the priority is configurable. # A
		* hwrm_queue_pfcenable_cfg command shall return error when trying to
		* configure a priority that is not configurable.
	*/	*/
	uint8_t queue_pri2cos_cfg_allowed;	uint8_t queue_pri2cos_cfg_allowed;
	/*	/*
	* 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then	* Bitmask indicating which queues can be configured by the
	* the HWRM shall allow the host SW driver to configure Priority to CoS	* hwrm_queue_pri2cos_cfg command. Each bit represents a specific queue
	* mapping using hwrm_queue_pri2cos_cfg.	* where bit 0 represents queue 0 and bit 7 represents queue 7. # A
		* value of 0 indicates that the queue is not configurable by the
		* hwrm_queue_pri2cos_cfg command. # A value of 1 indicates that the
		* queue is configurable. # A hwrm_queue_pri2cos_cfg command shall
		* return error when trying to configure a queue that is not
		* configurable.
	*/	*/
	uint8_t queue_cos2bw_cfg_allowed;	uint8_t queue_cos2bw_cfg_allowed;
	/*	/*
	* 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then	* Bitmask indicating which queues can be configured by the
	* the HWRM shall allow the host SW driver to configure CoS Bandwidth	* hwrm_queue_pri2cos_cfg command. Each bit represents a specific queue
	* configuration using hwrm_queue_cos2bw_cfg.	* where bit 0 represents queue 0 and bit 7 represents queue 7. # A
		* value of 0 indicates that the queue is not configurable by the
		* hwrm_queue_pri2cos_cfg command. # A value of 1 indicates that the
		* queue is configurable. # A hwrm_queue_pri2cos_cfg command shall
		* return error when trying to configure a queue not configurable.
	*/	*/
	uint8_t queue_id0;	uint8_t queue_id0;
	/* ID of CoS Queue 0. FF - Invalid id */	/*
		* ID of CoS Queue 0. FF - Invalid id # This ID can be used on any
		* subsequent call to an hwrm command that takes a queue id. # IDs must
		* always be queried by this command before any use by the driver or
		* software. # Any driver or software should not make any assumptions
		* about queue IDs. # A value of 0xff indicates that the queue is not
		* available. # Available queues may not be in sequential order.
		*/
	uint8_t queue_id0_service_profile;	uint8_t queue_id0_service_profile;
	/* This value is applicable to CoS queues only. */	/* This value is applicable to CoS queues only. */
	/* Lossy (best-effort) */	/* Lossy (best-effort) */
Context not available.
	/* Set to 0xFF... (All Fs) if there is no service profile specified */	/* Set to 0xFF... (All Fs) if there is no service profile specified */
	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
	uint8_t queue_id1;	uint8_t queue_id1;
	/* ID of CoS Queue 1. FF - Invalid id */	/*
		* ID of CoS Queue 1. FF - Invalid id # This ID can be used on any
		* subsequent call to an hwrm command that takes a queue id. # IDs must
		* always be queried by this command before any use by the driver or
		* software. # Any driver or software should not make any assumptions
		* about queue IDs. # A value of 0xff indicates that the queue is not
		* available. # Available queues may not be in sequential order.
		*/
	uint8_t queue_id1_service_profile;	uint8_t queue_id1_service_profile;
	/* This value is applicable to CoS queues only. */	/* This value is applicable to CoS queues only. */
	/* Lossy (best-effort) */	/* Lossy (best-effort) */
Context not available.
	/* Set to 0xFF... (All Fs) if there is no service profile specified */	/* Set to 0xFF... (All Fs) if there is no service profile specified */
	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
	uint8_t queue_id2;	uint8_t queue_id2;
	/* ID of CoS Queue 2. FF - Invalid id */	/*
		* ID of CoS Queue 2. FF - Invalid id # This ID can be used on any
		* subsequent call to an hwrm command that takes a queue id. # IDs must
		* always be queried by this command before any use by the driver or
		* software. # Any driver or software should not make any assumptions
		* about queue IDs. # A value of 0xff indicates that the queue is not
		* available. # Available queues may not be in sequential order.
		*/
	uint8_t queue_id2_service_profile;	uint8_t queue_id2_service_profile;
	/* This value is applicable to CoS queues only. */	/* This value is applicable to CoS queues only. */
	/* Lossy (best-effort) */	/* Lossy (best-effort) */
Context not available.
	/* Set to 0xFF... (All Fs) if there is no service profile specified */	/* Set to 0xFF... (All Fs) if there is no service profile specified */
	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
	uint8_t queue_id3;	uint8_t queue_id3;
	/* ID of CoS Queue 3. FF - Invalid id */	/*
		* ID of CoS Queue 3. FF - Invalid id # This ID can be used on any
		* subsequent call to an hwrm command that takes a queue id. # IDs must
		* always be queried by this command before any use by the driver or
		* software. # Any driver or software should not make any assumptions
		* about queue IDs. # A value of 0xff indicates that the queue is not
		* available. # Available queues may not be in sequential order.
		*/
	uint8_t queue_id3_service_profile;	uint8_t queue_id3_service_profile;
	/* This value is applicable to CoS queues only. */	/* This value is applicable to CoS queues only. */
	/* Lossy (best-effort) */	/* Lossy (best-effort) */
Context not available.
	/* Set to 0xFF... (All Fs) if there is no service profile specified */	/* Set to 0xFF... (All Fs) if there is no service profile specified */
	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
	uint8_t queue_id4;	uint8_t queue_id4;
	/* ID of CoS Queue 4. FF - Invalid id */	/*
		* ID of CoS Queue 4. FF - Invalid id # This ID can be used on any
		* subsequent call to an hwrm command that takes a queue id. # IDs must
		* always be queried by this command before any use by the driver or
		* software. # Any driver or software should not make any assumptions
		* about queue IDs. # A value of 0xff indicates that the queue is not
		* available. # Available queues may not be in sequential order.
		*/
	uint8_t queue_id4_service_profile;	uint8_t queue_id4_service_profile;
	/* This value is applicable to CoS queues only. */	/* This value is applicable to CoS queues only. */
	/* Lossy (best-effort) */	/* Lossy (best-effort) */
Context not available.
	/* Set to 0xFF... (All Fs) if there is no service profile specified */	/* Set to 0xFF... (All Fs) if there is no service profile specified */
	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
	uint8_t queue_id5;	uint8_t queue_id5;
	/* ID of CoS Queue 5. FF - Invalid id */	/*
		* ID of CoS Queue 5. FF - Invalid id # This ID can be used on any
		* subsequent call to an hwrm command that takes a queue id. # IDs must
		* always be queried by this command before any use by the driver or
		* software. # Any driver or software should not make any assumptions
		* about queue IDs. # A value of 0xff indicates that the queue is not
		* available. # Available queues may not be in sequential order.
		*/
	uint8_t queue_id5_service_profile;	uint8_t queue_id5_service_profile;
	/* This value is applicable to CoS queues only. */	/* This value is applicable to CoS queues only. */
	/* Lossy (best-effort) */	/* Lossy (best-effort) */
Context not available.
	/* Set to 0xFF... (All Fs) if there is no service profile specified */	/* Set to 0xFF... (All Fs) if there is no service profile specified */
	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
	uint8_t queue_id6;	uint8_t queue_id6;
	/* ID of CoS Queue 6. FF - Invalid id */	/*
		* ID of CoS Queue 6. FF - Invalid id # This ID can be used on any
		* subsequent call to an hwrm command that takes a queue id. # IDs must
		* always be queried by this command before any use by the driver or
		* software. # Any driver or software should not make any assumptions
		* about queue IDs. # A value of 0xff indicates that the queue is not
		* available. # Available queues may not be in sequential order.
		*/
	uint8_t queue_id6_service_profile;	uint8_t queue_id6_service_profile;
	/* This value is applicable to CoS queues only. */	/* This value is applicable to CoS queues only. */
	/* Lossy (best-effort) */	/* Lossy (best-effort) */
Context not available.
	/* Set to 0xFF... (All Fs) if there is no service profile specified */	/* Set to 0xFF... (All Fs) if there is no service profile specified */
	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
	uint8_t queue_id7;	uint8_t queue_id7;
	/* ID of CoS Queue 7. FF - Invalid id */	/*
		* ID of CoS Queue 7. FF - Invalid id # This ID can be used on any
		* subsequent call to an hwrm command that takes a queue id. # IDs must
		* always be queried by this command before any use by the driver or
		* software. # Any driver or software should not make any assumptions
		* about queue IDs. # A value of 0xff indicates that the queue is not
		* available. # Available queues may not be in sequential order.
		*/
	uint8_t queue_id7_service_profile;	uint8_t queue_id7_service_profile;
	/* This value is applicable to CoS queues only. */	/* This value is applicable to CoS queues only. */
	/* Lossy (best-effort) */	/* Lossy (best-effort) */
Context not available.
	#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)	#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
	/* Set to 0xFF... (All Fs) if there is no service profile specified */	/* Set to 0xFF... (All Fs) if there is no service profile specified */
	#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)	#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
		uint8_t queue_cfg_info;
		/* Information about queue configuration. */
		/*
		* If this flag is set to '1', then the queue is configured
		* asymmetrically on TX and RX sides. If this flag is set to '0', then
		* this queue is configured symmetrically on TX and RX sides.
		*/
		#define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG UINT32_C(0x1)
	uint8_t unused_0;	uint8_t unused_0;
	uint8_t unused_1;
	uint8_t valid;	uint8_t valid;
	/*	/*
	* This field is used in Output records to indicate that the output is	* This field is used in Output records to indicate that the output is
Context not available.
	*/	*/
	uint32_t flags;	uint32_t flags;
	/*	/*
	* Enumeration denoting the RX, TX type of the resource. This	* Enumeration denoting the RX, TX, or both directions applicable to the
	* enumeration is used for resources that are similar for both TX and RX	* resource. This enumeration is used for resources that are similar for
	* paths of the chip.	* both TX and RX paths of the chip.
	*/	*/
	#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)	#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
		#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
	/* tx path */	/* tx path */
	#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)	#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
	/* rx path */	/* rx path */
	#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)	#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
	#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX	/* Bi-directional (Symmetrically applicable to TX and RX paths) */
		#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
		#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
	uint32_t enables;	uint32_t enables;
	/* This bit must be '1' for the dflt_len field to be configured. */	/* This bit must be '1' for the dflt_len field to be configured. */
	#define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)	#define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
Context not available.
	*/	*/
	} __attribute__((packed));	} __attribute__((packed));

	/* hwrm_queue_buffers_qcfg */
	/*
	* Description: This function is called by a driver to query configuration of
	* the buffers assigned to a queue.
	*/
	/* Input (24 bytes) */

	struct hwrm_queue_buffers_qcfg_input {
	uint16_t req_type;
	/*
	* This value indicates what type of request this is. The format for the
	* rest of the command is determined by this field.
	*/
	uint16_t cmpl_ring;
	/*
	* This value indicates the what completion ring the request will be
	* optionally completed on. If the value is -1, then no CR completion
	* will be generated. Any other value must be a valid CR ring_id value
	* for this function.
	*/
	uint16_t seq_id;
	/* This value indicates the command sequence number. */
	uint16_t target_id;
	/*
	* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
	* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
	*/
	uint64_t resp_addr;
	/*
	* This is the host address where the response will be written when the
	* request is complete. This area must be 16B aligned and must be
	* cleared to zero before the request is made.
	*/
	uint32_t flags;
	/*
	* Enumeration denoting the RX, TX type of the resource. This
	* enumeration is used for resources that are similar for both TX and RX
	* paths of the chip.
	*/
	#define HWRM_QUEUE_BUFFERS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
	/* tx path */
	#define HWRM_QUEUE_BUFFERS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
	/* rx path */
	#define HWRM_QUEUE_BUFFERS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
	#define HWRM_QUEUE_BUFFERS_QCFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_BUFFERS_QCFG_INPUT_FLAGS_PATH_RX
	uint32_t queue_id;
	/* Queue ID of queue that is to be configured by this function. */
	} __attribute__((packed));

	/* Output (40 bytes) */

	struct hwrm_queue_buffers_qcfg_output {
	uint16_t error_code;
	/*
	* Pass/Fail or error type Note: receiver to verify the in parameters,
	* and fail the call with an error when appropriate
	*/
	uint16_t req_type;
	/* This field returns the type of original request. */
	uint16_t seq_id;
	/* This field provides original sequence number of the command. */
	uint16_t resp_len;
	/*
	* This field is the length of the response in bytes. The last byte of
	* the response is a valid flag that will read as '1' when the command
	* has been completely written to memory.
	*/
	uint32_t reserved;
	/* Number of bytes allocated as reserved space for this queue. */
	uint32_t shared;
	/*
	* Number of bytes of shared buffer space for this queue. The changing
	* of shared buffer size for one CoS may create an adverse effect on
	* other CoSs sharing the same buffer. It is recommended that the driver
	* does not modify the shared mbuf size without understanding the
	* consequence of it.
	*/
	uint32_t xoff;
	/*
	* XOFF threshold of the queue. This is a high threshold value used to
	* trigger XOFF.
	*/
	uint32_t xon;
	/*
	* XON threshold of the queue. This is the low threshold value used to
	* trigger XON.
	*/
	uint32_t full;
	/*
	* FULL threshold of the queue. At this threshold, buffers allocated for
	* this queue are full. Once this condition is asserted, packets on that
	* queue are dropped.
	*/
	uint32_t notfull;
	/*
	* NOTFULL threshold of the queue. This threshold is used for the de-
	* assertion of buffers full condition.
	*/
	uint32_t max;
	/*
	* The maximum number of bytes that will be allowed to be consumed by
	* the queue. This value is the sum of both the number of bytes reserved
	* for this queue and the maximum number of bytes of shared buffers
	* allowed to be consumed by this queue.
	*/
	uint8_t unused_0;
	uint8_t unused_1;
	uint8_t unused_2;
	uint8_t valid;
	/*
	* This field is used in Output records to indicate that the output is
	* completely written to RAM. This field should be read as '1' to
	* indicate that the output has been completely written. When writing a
	* command completion or response to an internal processor, the order of
	* writes has to be such that this field is written last.
	*/
	} __attribute__((packed));

	/* hwrm_queue_buffers_cfg */
	/*
	* Description: This function is called by a driver to configure the buffering
	* for a queue.
	*/
	/* Input (56 bytes) */

	struct hwrm_queue_buffers_cfg_input {
	uint16_t req_type;
	/*
	* This value indicates what type of request this is. The format for the
	* rest of the command is determined by this field.
	*/
	uint16_t cmpl_ring;
	/*
	* This value indicates the what completion ring the request will be
	* optionally completed on. If the value is -1, then no CR completion
	* will be generated. Any other value must be a valid CR ring_id value
	* for this function.
	*/
	uint16_t seq_id;
	/* This value indicates the command sequence number. */
	uint16_t target_id;
	/*
	* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
	* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
	*/
	uint64_t resp_addr;
	/*
	* This is the host address where the response will be written when the
	* request is complete. This area must be 16B aligned and must be
	* cleared to zero before the request is made.
	*/
	uint32_t flags;
	/*
	* Enumeration denoting the RX, TX type of the resource. This
	* enumeration is used for resources that are similar for both TX and RX
	* paths of the chip.
	*/
	#define HWRM_QUEUE_BUFFERS_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
	/* tx path */
	#define HWRM_QUEUE_BUFFERS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
	/* rx path */
	#define HWRM_QUEUE_BUFFERS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
	#define HWRM_QUEUE_BUFFERS_CFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_BUFFERS_CFG_INPUT_FLAGS_PATH_RX
	uint32_t enables;
	/* This bit must be '1' for the reserved field to be configured. */
	#define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_RESERVED UINT32_C(0x1)
	/* This bit must be '1' for the shared field to be configured. */
	#define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_SHARED UINT32_C(0x2)
	/* This bit must be '1' for the xoff field to be configured. */
	#define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_XOFF UINT32_C(0x4)
	/* This bit must be '1' for the xon field to be configured. */
	#define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_XON UINT32_C(0x8)
	/* This bit must be '1' for the full field to be configured. */
	#define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_FULL UINT32_C(0x10)
	/* This bit must be '1' for the notfull field to be configured. */
	#define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_NOTFULL UINT32_C(0x20)
	/* This bit must be '1' for the max field to be configured. */
	#define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_MAX UINT32_C(0x40)
	uint32_t queue_id;
	/* Queue ID of queue that is to be configured by this function. */
	uint32_t reserved;
	/* Number of bytes to be allocated as reserved space for this queue. */
	uint32_t shared;
	/*
	* Number of bytes of shared buffer space for this queue. The changing
	* of shared buffer size for one CoS may create an adverse effect on
	* other CoSs sharing the same buffer. It is recommended that the driver
	* does not modify the shared mbuf size without understanding the
	* consequence of it.
	*/
	uint32_t xoff;
	/*
	* XOFF threshold of the queue. This is a high threshold value used to
	* trigger XOFF.
	*/
	uint32_t xon;
	/*
	* XON threshold of the queue. This is the low threshold value used to
	* trigger XON.
	*/
	uint32_t full;
	/*
	* FULL threshold of the queue. At this threshold, buffers allocated for
	* this queue are full. Once this condition is asserted, packets on that
	* queue are dropped.
	*/
	uint32_t notfull;
	/*
	* NOTFULL threshold of the queue. This threshold is used for the de-
	* assertion of buffers full condition.
	*/
	uint32_t max;
	/*
	* The maximum number of bytes that will be allowed to be consumed by
	* the queue. This value is the sum of both the number of bytes reserved
	* for this queue and the maximum number of bytes of shared buffers
	* allowed to be consumed by this queue.
	*/
	} __attribute__((packed));

	/* Output (16 bytes) */

	struct hwrm_queue_buffers_cfg_output {
	uint16_t error_code;
	/*
	* Pass/Fail or error type Note: receiver to verify the in parameters,
	* and fail the call with an error when appropriate
	*/
	uint16_t req_type;
	/* This field returns the type of original request. */
	uint16_t seq_id;
	/* This field provides original sequence number of the command. */
	uint16_t resp_len;
	/*
	* This field is the length of the response in bytes. The last byte of
	* the response is a valid flag that will read as '1' when the command
	* has been completely written to memory.
	*/
	uint32_t unused_0;
	uint8_t unused_1;
	uint8_t unused_2;
	uint8_t unused_3;
	uint8_t valid;
	/*
	* This field is used in Output records to indicate that the output is
	* completely written to RAM. This field should be read as '1' to
	* indicate that the output has been completely written. When writing a
	* command completion or response to an internal processor, the order of
	* writes has to be such that this field is written last.
	*/
	} __attribute__((packed));

	/* hwrm_queue_pfcenable_qcfg */	/* hwrm_queue_pfcenable_qcfg */
	/*	/*
	* Description: This function is called by a driver to query PFC configuration	* Description: This function is called by a driver to query PFC configuration
Context not available.
	#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0)	#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0)
	#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX	#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
	/*	/*
	* When this bit is set to '1', the mapping is requested for inner VLAN	* When this bit is set to '0', the query is for VLAN PRI field in
	* PRI.	* tunnel headers. When this bit is set to '1', the query is for VLAN
		* PRI field in inner packet headers.
	*/	*/
	#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)	#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
	uint8_t port_id;	uint8_t port_id;
Context not available.
	uint8_t pri0_cos_queue_id;	uint8_t pri0_cos_queue_id;
	/*	/*
	* CoS Queue assigned to priority 0. This value can only be changed	* CoS Queue assigned to priority 0. This value can only be changed
	* before traffic has started.	* before traffic has started. A value of 0xff indicates that no CoS
		* queue is assigned to the specified priority.
	*/	*/
	uint8_t pri1_cos_queue_id;	uint8_t pri1_cos_queue_id;
	/*	/*
	* CoS Queue assigned to priority 1. This value can only be changed	* CoS Queue assigned to priority 1. This value can only be changed
	* before traffic has started.	* before traffic has started. A value of 0xff indicates that no CoS
		* queue is assigned to the specified priority.
	*/	*/
	uint8_t pri2_cos_queue_id;	uint8_t pri2_cos_queue_id;
	/*	/*
	* CoS Queue assigned to priority 2 This value can only be changed	* CoS Queue assigned to priority 2 This value can only be changed
	* before traffic has started.	* before traffic has started. A value of 0xff indicates that no CoS
		* queue is assigned to the specified priority.
	*/	*/
	uint8_t pri3_cos_queue_id;	uint8_t pri3_cos_queue_id;
	/*	/*
	* CoS Queue assigned to priority 3. This value can only be changed	* CoS Queue assigned to priority 3. This value can only be changed
	* before traffic has started.	* before traffic has started. A value of 0xff indicates that no CoS
		* queue is assigned to the specified priority.
	*/	*/
	uint8_t pri4_cos_queue_id;	uint8_t pri4_cos_queue_id;
	/*	/*
	* CoS Queue assigned to priority 4. This value can only be changed	* CoS Queue assigned to priority 4. This value can only be changed
	* before traffic has started.	* before traffic has started. A value of 0xff indicates that no CoS
		* queue is assigned to the specified priority.
	*/	*/
	uint8_t pri5_cos_queue_id;	uint8_t pri5_cos_queue_id;
	/*	/*
	* CoS Queue assigned to priority 5. This value can only be changed	* CoS Queue assigned to priority 5. This value can only be changed
	* before traffic has started.	* before traffic has started. A value of 0xff indicates that no CoS
		* queue is assigned to the specified priority.
	*/	*/
	uint8_t pri6_cos_queue_id;	uint8_t pri6_cos_queue_id;
	/*	/*
	* CoS Queue assigned to priority 6. This value can only be changed	* CoS Queue assigned to priority 6. This value can only be changed
	* before traffic has started.	* before traffic has started. A value of 0xff indicates that no CoS
		* queue is assigned to the specified priority.
	*/	*/
	uint8_t pri7_cos_queue_id;	uint8_t pri7_cos_queue_id;
	/*	/*
	* CoS Queue assigned to priority 7. This value can only be changed	* CoS Queue assigned to priority 7. This value can only be changed
	* before traffic has started.	* before traffic has started. A value of 0xff indicates that no CoS
		* queue is assigned to the specified priority.
	*/	*/
	uint32_t unused_0;	uint8_t queue_cfg_info;
	uint8_t unused_1;	/* Information about queue configuration. */
		/*
		* If this flag is set to '1', then the PRI to CoS configuration is
		* asymmetric on TX and RX sides. If this flag is set to '0', then PRI
		* to CoS configuration is symmetric on TX and RX sides.
		*/
		#define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG UINT32_C(0x1)
		uint8_t unused_0;
		uint16_t unused_1;
	uint8_t unused_2;	uint8_t unused_2;
	uint8_t unused_3;	uint8_t unused_3;
		uint8_t unused_4;
	uint8_t valid;	uint8_t valid;
	/*	/*
	* This field is used in Output records to indicate that the output is	* This field is used in Output records to indicate that the output is
Context not available.
	*/	*/
	uint32_t flags;	uint32_t flags;
	/*	/*
	* Enumeration denoting the RX, TX type of the resource. This	* Enumeration denoting the RX, TX, or both directions applicable to the
	* enumeration is used for resources that are similar for both TX and RX	* resource. This enumeration is used for resources that are similar for
	* paths of the chip.	* both TX and RX paths of the chip.
	*/	*/
	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
	/* tx path */	/* tx path */
	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 0)	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 0)
	/* rx path */	/* rx path */
	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0)	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0)
	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX	/* Bi-directional (Symmetrically applicable to TX and RX paths) */
	/* When this bit is '1', the mapping is for inner VLAN PRI. */	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR (UINT32_C(0x2) << 0)
	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
		/*
		* When this bit is set to '0', the mapping is requested for VLAN PRI
		* field in tunnel headers. When this bit is set to '1', the mapping is
		* requested for VLAN PRI field in inner packet headers.
		*/
		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
	uint32_t enables;	uint32_t enables;
		/*
		* This bit must be '1' for the pri0_cos_queue_id field to be
		* configured.
		*/
		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID UINT32_C(0x1)
		/*
		* This bit must be '1' for the pri1_cos_queue_id field to be
		* configured.
		*/
		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID UINT32_C(0x2)
		/*
		* This bit must be '1' for the pri2_cos_queue_id field to be
		* configured.
		*/
		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID UINT32_C(0x4)
		/*
		* This bit must be '1' for the pri3_cos_queue_id field to be
		* configured.
		*/
		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID UINT32_C(0x8)
		/*
		* This bit must be '1' for the pri4_cos_queue_id field to be
		* configured.
		*/
		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID UINT32_C(0x10)
		/*
		* This bit must be '1' for the pri5_cos_queue_id field to be
		* configured.
		*/
		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID UINT32_C(0x20)
		/*
		* This bit must be '1' for the pri6_cos_queue_id field to be
		* configured.
		*/
		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID UINT32_C(0x40)
		/*
		* This bit must be '1' for the pri7_cos_queue_id field to be
		* configured.
		*/
		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID UINT32_C(0x80)
	uint8_t port_id;	uint8_t port_id;
	/*	/*
	* Port ID of port for which the table is being configured. The HWRM	* Port ID of port for which the table is being configured. The HWRM
Context not available.
	uint16_t unused_1;	uint16_t unused_1;
	uint32_t queue_id0_min_bw;	uint32_t queue_id0_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id0_max_bw;	uint32_t queue_id0_max_bw;
	/*	/*
	* Maximum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id0_tsa_assign;	uint8_t queue_id0_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 1. */	/* ID of CoS Queue 1. */
	uint32_t queue_id1_min_bw;	uint32_t queue_id1_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id1_max_bw;	uint32_t queue_id1_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id1_tsa_assign;	uint8_t queue_id1_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 2. */	/* ID of CoS Queue 2. */
	uint32_t queue_id2_min_bw;	uint32_t queue_id2_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id2_max_bw;	uint32_t queue_id2_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id2_tsa_assign;	uint8_t queue_id2_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 3. */	/* ID of CoS Queue 3. */
	uint32_t queue_id3_min_bw;	uint32_t queue_id3_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id3_max_bw;	uint32_t queue_id3_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id3_tsa_assign;	uint8_t queue_id3_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 4. */	/* ID of CoS Queue 4. */
	uint32_t queue_id4_min_bw;	uint32_t queue_id4_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id4_max_bw;	uint32_t queue_id4_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id4_tsa_assign;	uint8_t queue_id4_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 5. */	/* ID of CoS Queue 5. */
	uint32_t queue_id5_min_bw;	uint32_t queue_id5_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id5_max_bw;	uint32_t queue_id5_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id5_tsa_assign;	uint8_t queue_id5_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 6. */	/* ID of CoS Queue 6. */
	uint32_t queue_id6_min_bw;	uint32_t queue_id6_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id6_max_bw;	uint32_t queue_id6_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id6_tsa_assign;	uint8_t queue_id6_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 7. */	/* ID of CoS Queue 7. */
	uint32_t queue_id7_min_bw;	uint32_t queue_id7_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id7_max_bw;	uint32_t queue_id7_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id7_tsa_assign;	uint8_t queue_id7_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	* following: - Minimum bandwidth - Maximum bandwidth - Transmission selection	* following: - Minimum bandwidth - Maximum bandwidth - Transmission selection
	* algorithm (TSA) - Priority Level (only applies to strict priority COS) -	* algorithm (TSA) - Priority Level (only applies to strict priority COS) -
	* Bandwidth weight # A CoS can be SP or non-SP: A SP CoS always gets the strict	* Bandwidth weight # A CoS can be SP or non-SP: A SP CoS always gets the strict
	* priority. Is an COS min BW is set to 0x0 then it is considered to be non-SP;	* priority. Note: SP provides lower latency in addition to reserved bandwidth #
	* this is a valid configuration. Note: SP provides lower latency in addition to	* For non-SP CoS, min BW can be specified to reserve specific amount of the
	* reserved bandwidth # For both SP CoS and non-SP CoS, min BW can be specified	* port BW. # The min BW specified for a CoS shall not exceed max port
	* to reserve specific amount of the port BW. # The min BW specified for a CoS	* bandwidth. # The total of min BWs specified for all CoS shall not exceed max
	* shall not exceed max port bandwidth. # The total of min BWs specified for all	* port bandwidth. # For any non-SP CoS, the minimum bandwidth guarantees are
	* CoS shall not exceed max port bandwidth. # For any non-SP CoS, the minimum	* subject to round-robin scheduling. This allows BW reservation with anti-
	* bandwidth guarantees are subject to round-robin scheduling. This allows BW	* starvation; one CoS will not block another CoS using RR. Note: The bandwidth
	* reservation with anti-starvation; one CoS will not block another CoS using	* guarantees for any non-SP CoS are met after servicing all SP CoS. # An SP CoS
	* RR. Note: The bandwidth guarantees for any non-SP CoS are met after servicing	* can potentially starve other lower priority SP CoS and non-SP CoS queues.
	* all SP CoS. # An SP CoS can potentially starve other lower priority SP CoS	* This can occur to the extent the SP min exceeds the available port BW. # For
	* and non-SP CoS queues. This can occur to the extent the SP min exceeds the	* any CoS, max BW can be specified to limit the BW consumed by the CoS. # A max
	* available port BW. # For any CoS, max BW can be specified to limit the BW	* BW can be used for a SP CoS to limit the starvation of other CoS, but using
	* consumed by the CoS. # The max BW specified for a CoS shall not exceed the	* this will cause some characteristics of any ETS CoS to be violated. # The max
	* max port bandwidth. # The WFQ provides a mechanism for sharing available	* BW specified for a CoS shall not exceed the max port bandwidth. # For SP CoS,
		* it is recommended to set min and max BW to 0. This instructs the adapter to
		* use default values. # The WFQ provides a mechanism for sharing available
	* bandwidth beyond the reserved minimums configured for each CoS. The WFQ	* bandwidth beyond the reserved minimums configured for each CoS. The WFQ
	* scheduler is used to provide the percentages of remaining bandwidth after: -	* scheduler is used to provide the percentages of remaining bandwidth after: -
	* first servicing the reserved bandwidth for all SP CoS, - followed by the	* first servicing the reserved bandwidth for all SP CoS, - followed by the
Context not available.
	* this COS is not guaranteed any bandwidth. A value of 0xFF.. (all Fs) means	* this COS is not guaranteed any bandwidth. A value of 0xFF.. (all Fs) means
	* min BW is not specified. When the min BW is not specified, the HWRM can set	* min BW is not specified. When the min BW is not specified, the HWRM can set
	* it to any value it considers appropriate. Note: For a non-SP COS, the HWRM	* it to any value it considers appropriate. Note: For a non-SP COS, the HWRM
	* should set min BW to 0 when the min BW is not specified. For an SP COS, the	* should set min BW to 0 when the min BW is not specified. For an SP COS, min
	* HWRM should set min BW to some small value when the min BW is not specified.	* BW value is ignored. Maximum Bandwidth: # This is the bandwidth limit of the
	* Maximum Bandwidth: # This is the bandwidth limit of the COS. # Values 0x0 and	* COS. # Values 0x0 and 0xFF.. (all Fs) are considered unspecified and the HWRM
	* 0xFF.. (all Fs) are considered unspecified and the HWRM will set the maximum	* will set the maximum bandwidth to maximum port bandwidth. Priority Level: #
	* bandwidth to maximum port bandwidth. Priority Level: # It applies only to SP.	* It applies only to SP. # This parameter is ignored for non-SP. # 0-7 are
	* # This parameter is ignored for non-SP. # 0-7 are valid values (higher value	* valid values (higher value means higher priority) # A priority level can be
	* means higher priority) # A priority level can be assigned to at most one SP.	* assigned to at most one SP. # Invalid priority levels assignment for SPs
	* # Invalid priority levels assignment for SPs shall result in failure.	* shall result in failure. Additional notes: # The HWRM may have to use min and
	* Additional notes: # The HWRM may have to use min and (max - min) to set	* (max - min) to set appropriate counters of hardware rate limiters. # The
	* appropriate counters of hardware rate limiters. # The bandwidth percentage as	* bandwidth percentage as specified in the DCB TC BW assignment should be used
	* specified in the DCB TC BW assignment should be used by the driver to specify	* by the driver to specify minimum bandwidth and bandwidth weight for a COS.
	* maximum bandwidth and bandwidth weight for a COS. For example, the driver	* For example, the driver should set max BW to 20 Gbps and weight to 50 for two
	* should set max BW to 20 Gbps and weight to 50 for two COSs when these two	* COSs when these two COSs are assigned 50% share of 40 Gbps max port
	* COSs are assigned 50% share of 40 Gbps max port bandwidth.	* bandwidth. DCBX use cases should always use max BW of 100% for all ETS CoS
		* queues.
	*/	*/
	/* Input (128 bytes) */	/* Input (128 bytes) */

Context not available.
	uint32_t flags;	uint32_t flags;
	uint32_t enables;	uint32_t enables;
	/*	/*
	* This bit must be '1' for the cos_queue_id0_valid field to be	* If this bit is set to 1, then all queue_id0 related parameters in
	* configured.	* this command are valid.
	*/	*/
	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID UINT32_C(0x1)	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID UINT32_C(0x1)
	/*	/*
	* This bit must be '1' for the cos_queue_id1_valid field to be	* If this bit is set to 1, then all queue_id1 related parameters in
	* configured.	* this command are valid.
	*/	*/
	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID UINT32_C(0x2)	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID UINT32_C(0x2)
	/*	/*
	* This bit must be '1' for the cos_queue_id2_valid field to be	* If this bit is set to 1, then all queue_id2 related parameters in
	* configured.	* this command are valid.
	*/	*/
	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID UINT32_C(0x4)	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID UINT32_C(0x4)
	/*	/*
	* This bit must be '1' for the cos_queue_id3_valid field to be	* If this bit is set to 1, then all queue_id3 related parameters in
	* configured.	* this command are valid.
	*/	*/
	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID UINT32_C(0x8)	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID UINT32_C(0x8)
	/*	/*
	* This bit must be '1' for the cos_queue_id4_valid field to be	* If this bit is set to 1, then all queue_id4 related parameters in
	* configured.	* this command are valid.
	*/	*/
	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID UINT32_C(0x10)	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID UINT32_C(0x10)
	/*	/*
	* This bit must be '1' for the cos_queue_id5_valid field to be	* If this bit is set to 1, then all queue_id5 related parameters in
	* configured.	* this command are valid.
	*/	*/
	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID UINT32_C(0x20)	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID UINT32_C(0x20)
	/*	/*
	* This bit must be '1' for the cos_queue_id6_valid field to be	* If this bit is set to 1, then all queue_id6 related parameters in
	* configured.	* this command are valid.
	*/	*/
	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID UINT32_C(0x40)	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID UINT32_C(0x40)
	/*	/*
	* This bit must be '1' for the cos_queue_id7_valid field to be	* If this bit is set to 1, then all queue_id7 related parameters in
	* configured.	* this command are valid.
	*/	*/
	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID UINT32_C(0x80)	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID UINT32_C(0x80)
	uint16_t port_id;	uint16_t port_id;
Context not available.
	uint8_t unused_0;	uint8_t unused_0;
	uint32_t queue_id0_min_bw;	uint32_t queue_id0_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id0_max_bw;	uint32_t queue_id0_max_bw;
	/*	/*
	* Maximum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id0_tsa_assign;	uint8_t queue_id0_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 1. */	/* ID of CoS Queue 1. */
	uint32_t queue_id1_min_bw;	uint32_t queue_id1_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id1_max_bw;	uint32_t queue_id1_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id1_tsa_assign;	uint8_t queue_id1_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 2. */	/* ID of CoS Queue 2. */
	uint32_t queue_id2_min_bw;	uint32_t queue_id2_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id2_max_bw;	uint32_t queue_id2_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id2_tsa_assign;	uint8_t queue_id2_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 3. */	/* ID of CoS Queue 3. */
	uint32_t queue_id3_min_bw;	uint32_t queue_id3_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id3_max_bw;	uint32_t queue_id3_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id3_tsa_assign;	uint8_t queue_id3_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 4. */	/* ID of CoS Queue 4. */
	uint32_t queue_id4_min_bw;	uint32_t queue_id4_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id4_max_bw;	uint32_t queue_id4_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id4_tsa_assign;	uint8_t queue_id4_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 5. */	/* ID of CoS Queue 5. */
	uint32_t queue_id5_min_bw;	uint32_t queue_id5_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id5_max_bw;	uint32_t queue_id5_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id5_tsa_assign;	uint8_t queue_id5_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 6. */	/* ID of CoS Queue 6. */
	uint32_t queue_id6_min_bw;	uint32_t queue_id6_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id6_max_bw;	uint32_t queue_id6_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id6_tsa_assign;	uint8_t queue_id6_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	/* ID of CoS Queue 7. */	/* ID of CoS Queue 7. */
	uint32_t queue_id7_min_bw;	uint32_t queue_id7_min_bw;
	/*	/*
	* Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate	* Minimum BW allocated to CoS Queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
	uint32_t queue_id7_max_bw;	uint32_t queue_id7_max_bw;
	/*	/*
	* Maximum BW allocated to CoS queue in Mbps. The HWRM will translate	* Maximum BW allocated to CoS queue. The HWRM will translate this value
	* this value into byte counter and time interval used for this COS	* into byte counter and time interval used for this COS inside the
	* inside the device.	* device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t queue_id7_tsa_assign;	uint8_t queue_id7_tsa_assign;
	/* Transmission Selection Algorithm (TSA) for CoS Queue. */	/* Transmission Selection Algorithm (TSA) for CoS Queue. */
	/* Strict Priority */	/* Strict Priority */
Context not available.
	*/	*/
	} __attribute__((packed));	} __attribute__((packed));

		/* hwrm_queue_dscp_qcaps */
		/*
		* Description: This command is called by a driver to query the DSCP
		* capabilities for a port.
		*/
		/* Input (24 bytes) */

		struct hwrm_queue_dscp_qcaps_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint8_t port_id;
		/*
		* Port ID of port for which the table is being configured. The HWRM
		* needs to check whether this function is allowed to configure pri2cos
		* mapping on this port.
		*/
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_queue_dscp_qcaps_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint8_t num_dscp_bits;
		/* The number of bits provided by the hardware for the DSCP value. */
		uint8_t unused_0;
		uint16_t max_entries;
		/* Max number of DSCP-MASK-PRI entries supported. */
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_queue_dscp2pri_qcfg */
		/*
		* Description: This command is called by a driver to query configuration of the
		* DSCP to PRI mapping on the receive side. This mapping can be different on
		* different ports.
		*/
		/* Input (32 bytes) */

		struct hwrm_queue_dscp2pri_qcfg_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint64_t dest_data_addr;
		/*
		* This is the host address where the 24-bits DSCP-MASK-PRI tuple(s)
		* will be copied to.
		*/
		uint8_t port_id;
		/*
		* Port ID of port for which the table is being configured. The HWRM
		* needs to check whether this function is allowed to configure pri2cos
		* mapping on this port.
		*/
		uint8_t unused_0;
		uint16_t dest_data_buffer_size;
		/* Size of the buffer pointed to by dest_data_addr. */
		uint32_t unused_1;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_queue_dscp2pri_qcfg_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint16_t entry_cnt;
		/*
		* A count of the number of DSCP-MASK-PRI tuple(s) pointed to by the
		* dest_data_addr.
		*/
		uint8_t default_pri;
		/*
		* This is the default PRI which un-initialized DSCP values are mapped
		* to.
		*/
		uint8_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_queue_dscp2pri_cfg */
		/*
		* Description: This command is called by a driver to configure the DSCP to PRI
		* mapping on the receive side. This mapping can be different on different
		* ports.
		*/
		/* Input (40 bytes) */

		struct hwrm_queue_dscp2pri_cfg_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint64_t src_data_addr;
		/*
		* This is the host address where the 24-bits DSCP-MASK-PRI tuple will
		* be copied from.
		*/
		uint32_t flags;
		/* use_hw_default_pri is 1 b */
		#define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI UINT32_C(0x1)
		uint32_t enables;
		/* This bit must be '1' for the default_pri field to be configured. */
		#define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI UINT32_C(0x1)
		uint8_t port_id;
		/*
		* Port ID of port for which the table is being configured. The HWRM
		* needs to check whether this function is allowed to configure pri2cos
		* mapping on this port.
		*/
		uint8_t default_pri;
		/*
		* This is the default PRI which un-initialized DSCP values will be
		* mapped to.
		*/
		uint16_t entry_cnt;
		/*
		* A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
		* to by src_data_addr.
		*/
		uint32_t unused_0;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_queue_dscp2pri_cfg_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

	/* hwrm_vnic_alloc */	/* hwrm_vnic_alloc */
	/*	/*
	* Description: This VNIC is a resource in the RX side of the chip that is used	* Description: This VNIC is a resource in the RX side of the chip that is used
Context not available.
	uint8_t unused_1;	uint8_t unused_1;
	uint32_t flags;	uint32_t flags;
	/* Unused. */	/* Unused. */
		#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED UINT32_C(0x1)
	/*	/*
	* When this bit is '1', the capability of stripping VLAN in the RX path	* When this bit is '1', the capability of stripping VLAN in the RX path
	* is supported on VNIC(s). If set to '0', then VLAN stripping	* is supported on VNIC(s). If set to '0', then VLAN stripping
Context not available.
	uint32_t enables;	uint32_t enables;
	/* This bit must be '1' for the Reserved1 field to be configured. */	/* This bit must be '1' for the Reserved1 field to be configured. */
	#define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED1 UINT32_C(0x1)	#define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED1 UINT32_C(0x1)
	/* This bit must be '1' for the Reserved2 field to be configured. */	/* This bit must be '1' for the ring_arb_cfg field to be configured. */
	#define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED2 UINT32_C(0x2)	#define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG UINT32_C(0x2)
	/* This bit must be '1' for the Reserved3 field to be configured. */	/* This bit must be '1' for the Reserved3 field to be configured. */
	#define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED3 UINT32_C(0x4)	#define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED3 UINT32_C(0x4)
	/*	/*
Context not available.
	#define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID UINT32_C(0x20)	#define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID UINT32_C(0x20)
	uint8_t ring_type;	uint8_t ring_type;
	/* Ring Type. */	/* Ring Type. */
	/* Completion Ring (CR) */	/* L2 Completion Ring (CR) */
	#define HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL UINT32_C(0x0)	#define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
	/* TX Ring (TR) */	/* TX Ring (TR) */
	#define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)	#define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
	/* RX Ring (RR) */	/* RX Ring (RR) */
	#define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)	#define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
		/* RoCE Notification Completion Ring (ROCE_CR) */
		#define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
	uint8_t unused_0;	uint8_t unused_0;
	uint16_t unused_1;	uint16_t unused_1;
	uint64_t page_tbl_addr;	uint64_t page_tbl_addr;
Context not available.
	uint8_t unused_5;	uint8_t unused_5;
	uint32_t reserved1;	uint32_t reserved1;
	/* This field is reserved for the future use. It shall be set to 0. */	/* This field is reserved for the future use. It shall be set to 0. */
	uint16_t reserved2;	uint16_t ring_arb_cfg;
	/* This field is reserved for the future use. It shall be set to 0. */	/*
		* This field is used only when ring_type is a TX ring. This field is
		* used to configure arbitration related parameters for a TX ring.
		*/
		/* Arbitration policy used for the ring. */
		#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK UINT32_C(0xf)
		#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
		/*
		* Use strict priority for the TX ring. Priority value is
		* specified in arb_policy_param
		*/
		#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP (UINT32_C(0x1) << 0)
		/*
		* Use weighted fair queue arbitration for the TX ring. Weight
		* is specified in arb_policy_param
		*/
		#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ (UINT32_C(0x2) << 0)
		#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
		/* Reserved field. */
		#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK UINT32_C(0xf0)
		#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
		/*
		* Arbitration policy specific parameter. # For strict priority
		* arbitration policy, this field represents a priority value. If set to
		* 0, then the priority is not specified and the HWRM is allowed to
		* select any priority for this TX ring. # For weighted fair queue
		* arbitration policy, this field represents a weight value. If set to
		* 0, then the weight is not specified and the HWRM is allowed to select
		* any weight for this TX ring.
		*/
		#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK UINT32_C(0xff00)
		#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
	uint8_t unused_6;	uint8_t unused_6;
	uint8_t unused_7;	uint8_t unused_7;
	uint32_t reserved3;	uint32_t reserved3;
Context not available.
	/* This field is reserved for the future use. It shall be set to 0. */	/* This field is reserved for the future use. It shall be set to 0. */
	uint32_t max_bw;	uint32_t max_bw;
	/*	/*
	* This field is used only when ring_type is a TX ring. Maximum BW	* This field is used only when ring_type is a TX ring to specify
	* allocated to this TX ring in Mbps. The HWRM will translate this value	* maximum BW allocated to the TX ring. The HWRM will translate this
	* into byte counter and time interval used for this ring inside the	* value into byte counter and time interval used for this ring inside
	* device.	* the device.
	*/	*/
		/* The bandwidth value. */
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
	uint8_t int_mode;	uint8_t int_mode;
	/*	/*
	* This field is used only when ring_type is a Completion ring. This	* This field is used only when ring_type is a Completion ring. This
Context not available.
	* has been completely written to memory.	* has been completely written to memory.
	*/	*/
	uint16_t ring_id;	uint16_t ring_id;
	/* Physical number of ring allocated. */	/*
		* Physical number of ring allocated. This value shall be unique for a
		* ring type.
		*/
	uint16_t logical_ring_id;	uint16_t logical_ring_id;
	/* Logical number of ring allocated. */	/* Logical number of ring allocated. */
	uint8_t unused_0;	uint8_t unused_0;
Context not available.
	/* hwrm_ring_free */	/* hwrm_ring_free */
	/*	/*
	* Description: This command is used to free a ring and associated resources.	* Description: This command is used to free a ring and associated resources.
		* With QoS and DCBx agents, it is possible the traffic classes will be moved
		* from one CoS queue to another. When this occurs, the driver shall call
		* 'hwrm_ring_free' to free the allocated rings and then call 'hwrm_ring_alloc'
		* to re-allocate each ring and assign it to a new CoS queue. hwrm_ring_free
		* shall be called on a ring only after it has been idle for 500ms or more and
		* no frames have been posted to the ring during this time. All frames queued
		* for transmission shall be completed and at least 500ms time elapsed from the
		* last completion before calling this command.
	*/	*/
	/* Input (24 bytes) */	/* Input (24 bytes) */

Context not available.
	*/	*/
	uint8_t ring_type;	uint8_t ring_type;
	/* Ring Type. */	/* Ring Type. */
	/* Completion Ring (CR) */	/* L2 Completion Ring (CR) */
	#define HWRM_RING_FREE_INPUT_RING_TYPE_CMPL UINT32_C(0x0)	#define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
	/* TX Ring (TR) */	/* TX Ring (TR) */
	#define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)	#define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
	/* RX Ring (RR) */	/* RX Ring (RR) */
	#define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)	#define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
		/* RoCE Notification Completion Ring (ROCE_CR) */
		#define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
	uint8_t unused_0;	uint8_t unused_0;
	uint16_t ring_id;	uint16_t ring_id;
	/* Physical number of ring allocated. */	/* Physical number of ring allocated. */
Context not available.
	*/	*/
	uint8_t ring_type;	uint8_t ring_type;
	/* Ring Type. */	/* Ring Type. */
	/* Completion Ring (CR) */	/* L2 Completion Ring (CR) */
	#define HWRM_RING_RESET_INPUT_RING_TYPE_CMPL UINT32_C(0x0)	#define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
	/* TX Ring (TR) */	/* TX Ring (TR) */
	#define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)	#define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
	/* RX Ring (RR) */	/* RX Ring (RR) */
	#define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)	#define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
		/* RoCE Notification Completion Ring (ROCE_CR) */
		#define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
	uint8_t unused_0;	uint8_t unused_0;
	uint16_t ring_id;	uint16_t ring_id;
	/* Physical number of the ring. */	/* Physical number of the ring. */
Context not available.
	*/	*/
	} __attribute__((packed));	} __attribute__((packed));

		/* hwrm_cfa_vlan_antispoof_cfg */
		/* Description: Configures vlan anti-spoof filters for VF. */
		/* Input (32 bytes) */

		struct hwrm_cfa_vlan_antispoof_cfg_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t fid;
		/*
		* Function ID of the function that is being configured. Only valid for
		* a VF FID configured by the PF.
		*/
		uint8_t unused_0;
		uint8_t unused_1;
		uint32_t num_vlan_entries;
		/* Number of VLAN entries in the vlan_tag_mask_tbl. */
		uint64_t vlan_tag_mask_tbl_addr;
		/*
		* The vlan_tag_mask_tbl_addr is the DMA address of the VLAN antispoof
		* table. Each table entry contains the 16-bit TPID (0x8100 or 0x88a8
		* only), 16-bit VLAN ID, and a 16-bit mask, all in network order to
		* match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry, the mask
		* value should be 0xfff for the 12-bit VLAN ID.
		*/
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_vlan_antispoof_cfg_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_vlan_antispoof_qcfg */
		/*
		* Description: Returns the current configuration of the vlan anti-spoof filters
		* for VF.
		*/
		/* Input (32 bytes) */

		struct hwrm_cfa_vlan_antispoof_qcfg_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t fid;
		/*
		* Function ID of the function that is being queried. Only valid for a
		* VF FID queried by the PF.
		*/
		uint8_t unused_0;
		uint8_t unused_1;
		uint32_t max_vlan_entries;
		/*
		* Maximum number of VLAN entries the firmware is allowed to DMA to
		* vlan_tag_mask_tbl.
		*/
		uint64_t vlan_tag_mask_tbl_addr;
		/*
		* The vlan_tag_mask_tbl_addr is the DMA address of the VLAN antispoof
		* table to which firmware will DMA to. Each table entry will contain
		* the 16-bit TPID (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit
		* mask, all in network order to match hwrm_cfa_l2_set_rx_mask. For an
		* individual VLAN entry, the mask value should be 0xfff for the 12-bit
		* VLAN ID.
		*/
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_vlan_antispoof_qcfg_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t num_vlan_entries;
		/* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
		uint8_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

	/* hwrm_cfa_tunnel_filter_alloc */	/* hwrm_cfa_tunnel_filter_alloc */
	/*	/*
	* Description: This is a tunnel filter that uses fields from tunnel header in	* Description: This is a tunnel filter that uses fields from tunnel header in
Context not available.
	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE UINT32_C(0x8)	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE UINT32_C(0x8)
	uint8_t unused_0;	uint8_t unused_0;
	uint16_t unused_1;	uint16_t unused_1;
	uint32_t encap_data[16];	uint32_t encap_data[20];
	/* This value is encap data used for the given encap type. */	/* This value is encap data used for the given encap type. */
	} __attribute__((packed));	} __attribute__((packed));

Context not available.
	* then it should be considered accept action.	* then it should be considered accept action.
	*/	*/
	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x2)	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x2)
		/*
		* Setting of this flag indicates that a meter is expected to be
		* attached to this flow. This hint can be used when choosing the action
		* record format required for the flow.
		*/
		#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER UINT32_C(0x4)
	uint32_t enables;	uint32_t enables;
	/* This bit must be '1' for the l2_filter_id field to be configured. */	/* This bit must be '1' for the l2_filter_id field to be configured. */
	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
Context not available.
	uint8_t ip_protocol;	uint8_t ip_protocol;
	/*	/*
	* The value of protocol filed in IP header. Applies to UDP and TCP	* The value of protocol filed in IP header. Applies to UDP and TCP
	* traffic. 6 - UDP 17 - TCP	* traffic. 6 - TCP 17 - UDP
	*/	*/
	/* invalid */	/* invalid */
	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
		/* TCP */
		#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
	/* UDP */	/* UDP */
	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x6)	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
	/* TCP */
	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x11)
	uint16_t dst_id;	uint16_t dst_id;
	/*	/*
	* If set, this value shall represent the Logical VNIC ID of the	* If set, this value shall represent the Logical VNIC ID of the
Context not available.
	} __attribute__((packed));	} __attribute__((packed));

	/* hwrm_cfa_ntuple_filter_cfg */	/* hwrm_cfa_ntuple_filter_cfg */
	/* Description: Configure an ntuple filter with new destination VNIC */	/*
	/* Input (40 bytes) */	* Description: Configure an ntuple filter with a new destination VNIC and/or
		* meter.
		*/
		/* Input (48 bytes) */

	struct hwrm_cfa_ntuple_filter_cfg_input {	struct hwrm_cfa_ntuple_filter_cfg_input {
	uint16_t req_type;	uint16_t req_type;
Context not available.
	* configured.	* configured.
	*/	*/
	#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)	#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)
		/*
		* This bit must be '1' for the new_meter_instance_id field to be
		* configured.
		*/
		#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID UINT32_C(0x4)
	uint32_t unused_0;	uint32_t unused_0;
	uint64_t ntuple_filter_id;	uint64_t ntuple_filter_id;
	/* This value is an opaque id into CFA data structures. */	/* This value is an opaque id into CFA data structures. */
Context not available.
	*/	*/
	uint32_t new_mirror_vnic_id;	uint32_t new_mirror_vnic_id;
	/* New Logical VNIC ID of the VNIC where traffic is mirrored. */	/* New Logical VNIC ID of the VNIC where traffic is mirrored. */
		uint16_t new_meter_instance_id;
		/*
		* New meter to attach to the flow. Specifying the invalid instance ID
		* is used to remove any existing meter from the flow.
		*/
		/*
		* A value of 0xfff is considered invalid and implies the
		* instance is not configured.
		*/
		#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
		uint16_t unused_1[3];
	} __attribute__((packed));	} __attribute__((packed));

	/* Output (16 bytes) */	/* Output (16 bytes) */
Context not available.
	* then it should be considered accept action.	* then it should be considered accept action.
	*/	*/
	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
		/*
		* Setting of this flag indicates that a meter is expected to be
		* attached to this flow. This hint can be used when choosing the action
		* record format required for the flow.
		*/
		#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
	uint32_t enables;	uint32_t enables;
	/* This bit must be '1' for the l2_filter_id field to be configured. */	/* This bit must be '1' for the l2_filter_id field to be configured. */
	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
Context not available.
	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x8000)	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x8000)
	/* This bit must be '1' for the encap_record_id field to be configured. */	/* This bit must be '1' for the encap_record_id field to be configured. */
	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID UINT32_C(0x10000)	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID UINT32_C(0x10000)
		/*
		* This bit must be '1' for the meter_instance_id field to be
		* configured.
		*/
		#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID UINT32_C(0x20000)
	uint64_t l2_filter_id;	uint64_t l2_filter_id;
	/*	/*
	* This value identifies a set of CFA data structures used for an L2	* This value identifies a set of CFA data structures used for an L2
Context not available.
	*/	*/
	uint8_t src_macaddr[6];	uint8_t src_macaddr[6];
	/* This value indicates the source MAC address in the Ethernet header. */	/* This value indicates the source MAC address in the Ethernet header. */
	uint8_t unused_2;	uint16_t meter_instance_id;
	uint8_t unused_3;	/* The meter instance to attach to the flow. */
		/*
		* A value of 0xfff is considered invalid and implies the
		* instance is not configured.
		*/
		#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
	uint8_t dst_macaddr[6];	uint8_t dst_macaddr[6];
	/*	/*
	* This value indicates the destination MAC address in the Ethernet	* This value indicates the destination MAC address in the Ethernet
Context not available.
	uint8_t ip_protocol;	uint8_t ip_protocol;
	/*	/*
	* The value of protocol filed in IP header. Applies to UDP and TCP	* The value of protocol filed in IP header. Applies to UDP and TCP
	* traffic. 6 - UDP 17 - TCP	* traffic. 6 - TCP 17 - UDP
	*/	*/
	/* invalid */	/* invalid */
	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
		/* TCP */
		#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
	/* UDP */	/* UDP */
	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x6)	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
	/* TCP */	uint8_t unused_2;
	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x11)	uint8_t unused_3;
	uint8_t unused_4;
	uint8_t unused_5;
	uint32_t src_ipaddr[4]; /* big endian */	uint32_t src_ipaddr[4]; /* big endian */
	/*	/*
	* The value of source IP address to be used in filtering. For IPv4,	* The value of source IP address to be used in filtering. For IPv4,
Context not available.
	*/	*/
	uint32_t dst_ipaddr[4]; /* big endian */	uint32_t dst_ipaddr[4]; /* big endian */
	/*	/*
	* The value of destination IP address to be used in filtering. For	* big_endian = True The value of destination IP address to be used in
	* IPv4, first four bytes represent the IP address.	* filtering. For IPv4, first four bytes represent the IP address.
	*/	*/
	uint16_t src_port; /* big endian */	uint16_t src_port; /* big endian */
	/*	/*
Context not available.
	/* Logical VNIC ID of the VNIC where traffic is mirrored. */	/* Logical VNIC ID of the VNIC where traffic is mirrored. */
	uint32_t encap_record_id;	uint32_t encap_record_id;
	/* Logical ID of the encapsulation record. */	/* Logical ID of the encapsulation record. */
	uint32_t unused_6;	uint32_t unused_4;
	} __attribute__((packed));	} __attribute__((packed));

	/* Output (24 bytes) */	/* Output (24 bytes) */
Context not available.
	} __attribute__((packed));	} __attribute__((packed));

	/* hwrm_cfa_em_flow_cfg */	/* hwrm_cfa_em_flow_cfg */
	/* Description: Configure an EM flow with new destination VNIC */	/*
	/* Input (40 bytes) */	* Description: Configure an EM flow with a new destination VNIC and/or meter.
		*/
		/* Input (48 bytes) */

	struct hwrm_cfa_em_flow_cfg_input {	struct hwrm_cfa_em_flow_cfg_input {
	uint16_t req_type;	uint16_t req_type;
Context not available.
	* configured.	* configured.
	*/	*/
	#define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)	#define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)
		/*
		* This bit must be '1' for the new_meter_instance_id field to be
		* configured.
		*/
		#define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID UINT32_C(0x4)
	uint32_t unused_0;	uint32_t unused_0;
	uint64_t em_filter_id;	uint64_t em_filter_id;
	/* This value is an opaque id into CFA data structures. */	/* This value is an opaque id into CFA data structures. */
Context not available.
	*/	*/
	uint32_t new_mirror_vnic_id;	uint32_t new_mirror_vnic_id;
	/* New Logical VNIC ID of the VNIC where traffic is mirrored. */	/* New Logical VNIC ID of the VNIC where traffic is mirrored. */
		uint16_t new_meter_instance_id;
		/*
		* New meter to attach to the flow. Specifying the invalid instance ID
		* is used to remove any existing meter from the flow.
		*/
		/*
		* A value of 0xfff is considered invalid and implies the
		* instance is not configured.
		*/
		#define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
		uint16_t unused_1[3];
	} __attribute__((packed));	} __attribute__((packed));

	/* Output (16 bytes) */	/* Output (16 bytes) */
Context not available.
	*/	*/
	} __attribute__((packed));	} __attribute__((packed));

		/* hwrm_cfa_meter_profile_alloc */
		/*
		* Description: This is a meter profile that defines the characteristics of the
		* meter. This includes the algorithm, information rates, and burst sizes. No
		* running state is kept in a profile and instead meter instances are allocated
		* that reference a profile.
		*/
		/* Input (40 bytes) */

		struct hwrm_cfa_meter_profile_alloc_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint8_t flags;
		/*
		* Enumeration denoting the RX, TX type of the resource. This
		* enumeration is used for resources that are similar for both TX and RX
		* paths of the chip.
		*/
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
		/* tx path */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
		/* rx path */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
		uint8_t meter_type;
		/* The meter algorithm type. */
		/* RFC 2697 (srTCM) */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0)
		/* RFC 2698 (trTCM) */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1)
		/* RFC 4115 (trTCM) */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2)
		uint16_t reserved1;
		/* This field is reserved for the future use. It shall be set to 0. */
		uint32_t reserved2;
		/* This field is reserved for the future use. It shall be set to 0. */
		uint32_t commit_rate;
		/* A meter rate specified in bytes-per-second. */
		/* The bandwidth value. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
		uint32_t commit_burst;
		/* A meter burst size specified in bytes. */
		/* The bandwidth value. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
		uint32_t excess_peak_rate;
		/* A meter rate specified in bytes-per-second. */
		/* The bandwidth value. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
		uint32_t excess_peak_burst;
		/* A meter burst size specified in bytes. */
		/* The bandwidth value. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_meter_profile_alloc_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint16_t meter_profile_id;
		/* This value identifies a meter profile in CFA. */
		/*
		* A value of 0xfff is considered invalid and implies the
		* profile is not configured.
		*/
		#define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
		uint8_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t unused_4;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_meter_profile_free */
		/* Description: Free a meter profile. */
		/* Input (24 bytes) */

		struct hwrm_cfa_meter_profile_free_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint8_t flags;
		/*
		* Enumeration denoting the RX, TX type of the resource. This
		* enumeration is used for resources that are similar for both TX and RX
		* paths of the chip.
		*/
		#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
		/* tx path */
		#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
		/* rx path */
		#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
		#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
		uint8_t unused_0;
		uint16_t meter_profile_id;
		/* This value identifies a meter profile in CFA. */
		/*
		* A value of 0xfff is considered invalid and implies the
		* profile is not configured.
		*/
		#define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
		uint32_t unused_1;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_meter_profile_free_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_meter_profile_cfg */
		/* Description: Reconfigure a meter profile. */
		/* Input (40 bytes) */

		struct hwrm_cfa_meter_profile_cfg_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint8_t flags;
		/*
		* Enumeration denoting the RX, TX type of the resource. This
		* enumeration is used for resources that are similar for both TX and RX
		* paths of the chip.
		*/
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
		/* tx path */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
		/* rx path */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
		uint8_t meter_type;
		/* The meter algorithm type. */
		/* RFC 2697 (srTCM) */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0)
		/* RFC 2698 (trTCM) */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1)
		/* RFC 4115 (trTCM) */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2)
		uint16_t meter_profile_id;
		/* This value identifies a meter profile in CFA. */
		/*
		* A value of 0xfff is considered invalid and implies the
		* profile is not configured.
		*/
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
		uint32_t reserved;
		/* This field is reserved for the future use. It shall be set to 0. */
		uint32_t commit_rate;
		/* A meter rate specified in bytes-per-second. */
		/* The bandwidth value. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
		uint32_t commit_burst;
		/* A meter burst size specified in bytes. */
		/* The bandwidth value. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
		uint32_t excess_peak_rate;
		/* A meter rate specified in bytes-per-second. */
		/* The bandwidth value. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
		uint32_t excess_peak_burst;
		/* A meter burst size specified in bytes. */
		/* The bandwidth value. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT 0
		/* The granularity of the value (bits or bytes). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE UINT32_C(0x10000000)
		/* Value is in bits. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
		/* Value is in bytes. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
		/* bw_value_unit is 3 b */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT 29
		/* Value is in Mb or MB (base 10). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
		/* Value is in Kb or KB (base 10). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
		/* Value is in bits or bytes. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
		/* Value is in Gb or GB (base 10). */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
		/* Value is in 1/100th of a percentage of total bandwidth. */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
		/* Invalid unit */
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_meter_profile_cfg_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_meter_instance_alloc */
		/*
		* Description: This is a meter instance which is used to track a meter's bucket
		* fill values for a flow. Each meter instance references a meter profile that
		* defines the meter algorithm in use.
		*/
		/* Input (24 bytes) */

		struct hwrm_cfa_meter_instance_alloc_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint8_t flags;
		/*
		* Enumeration denoting the RX, TX type of the resource. This
		* enumeration is used for resources that are similar for both TX and RX
		* paths of the chip.
		*/
		#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
		/* tx path */
		#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
		/* rx path */
		#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
		#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
		uint8_t unused_0;
		uint16_t meter_profile_id;
		/* This value identifies a meter profile in CFA. */
		/*
		* A value of 0xfff is considered invalid and implies the
		* profile is not configured.
		*/
		#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
		uint32_t unused_1;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_meter_instance_alloc_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint16_t meter_instance_id;
		/* This value identifies a meter instance in CFA. */
		/*
		* A value of 0xfff is considered invalid and implies the
		* instance is not configured.
		*/
		#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
		uint8_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t unused_4;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_meter_instance_free */
		/* Description: Free a meter instance. */
		/* Input (24 bytes) */

		struct hwrm_cfa_meter_instance_free_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint8_t flags;
		/*
		* Enumeration denoting the RX, TX type of the resource. This
		* enumeration is used for resources that are similar for both TX and RX
		* paths of the chip.
		*/
		#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
		/* tx path */
		#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
		/* rx path */
		#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
		#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
		uint8_t unused_0;
		uint16_t meter_instance_id;
		/* This value identifies a meter instance in CFA. */
		/*
		* A value of 0xfff is considered invalid and implies the
		* instance is not configured.
		*/
		#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
		uint32_t unused_1;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_meter_instance_free_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_decap_filter_alloc */
		/*
		* Description: This command uses fields from L4/L3/L2 headers. All L2/L3/L4
		* header fields are specified in network byte order.
		*/
		/* Input (104 bytes) */

		struct hwrm_cfa_decap_filter_alloc_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint32_t flags;
		/* ovs_tunnel is 1 b */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL UINT32_C(0x1)
		uint32_t enables;
		/* This bit must be '1' for the tunnel_type field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x1)
		/* This bit must be '1' for the tunnel_id field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID UINT32_C(0x2)
		/* This bit must be '1' for the src_macaddr field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x4)
		/* This bit must be '1' for the dst_macaddr field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x8)
		/* This bit must be '1' for the ovlan_vid field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID UINT32_C(0x10)
		/* This bit must be '1' for the ivlan_vid field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID UINT32_C(0x20)
		/* This bit must be '1' for the t_ovlan_vid field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID UINT32_C(0x40)
		/* This bit must be '1' for the t_ivlan_vid field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID UINT32_C(0x80)
		/* This bit must be '1' for the ethertype field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x100)
		/* This bit must be '1' for the src_ipaddr field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x200)
		/* This bit must be '1' for the dst_ipaddr field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x400)
		/* This bit must be '1' for the ipaddr_type field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x800)
		/* This bit must be '1' for the ip_protocol field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x1000)
		/* This bit must be '1' for the src_port field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x2000)
		/* This bit must be '1' for the dst_port field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x4000)
		/* This bit must be '1' for the dst_id field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x8000)
		/* This bit must be '1' for the mirror_vnic_id field to be configured. */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x10000)
		uint32_t tunnel_id;
		/*
		* Tunnel identifier. Virtual Network Identifier (VNI). Only valid with
		* tunnel_types VXLAN, NVGRE, and Geneve. Only lower 24-bits of VNI
		* field are used in setting up the filter.
		*/
		uint8_t tunnel_type;
		/* Tunnel Type. */
		/* Non-tunnel */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
		/* Virtual eXtensible Local Area Network (VXLAN) */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
		/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
		/* Generic Routing Encapsulation (GRE) inside Ethernet payload */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
		/* IP in IP */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
		/* Generic Network Virtualization Encapsulation (Geneve) */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
		/* Multi-Protocol Lable Switching (MPLS) */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
		/* Stateless Transport Tunnel (STT) */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
		/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
		/* Any tunneled traffic */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
		uint8_t unused_0;
		uint16_t unused_1;
		uint8_t src_macaddr[6];
		/* This value indicates the source MAC address in the Ethernet header. */
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t dst_macaddr[6];
		/*
		* This value indicates the destination MAC address in the Ethernet
		* header.
		*/
		uint16_t ovlan_vid;
		/*
		* This value indicates the VLAN ID of the outer VLAN tag in the
		* Ethernet header.
		*/
		uint16_t ivlan_vid;
		/*
		* This value indicates the VLAN ID of the inner VLAN tag in the
		* Ethernet header.
		*/
		uint16_t t_ovlan_vid;
		/*
		* This value indicates the VLAN ID of the outer VLAN tag in the tunnel
		* Ethernet header.
		*/
		uint16_t t_ivlan_vid;
		/*
		* This value indicates the VLAN ID of the inner VLAN tag in the tunnel
		* Ethernet header.
		*/
		uint16_t ethertype; /* big endian */
		/* This value indicates the ethertype in the Ethernet header. */
		uint8_t ip_addr_type;
		/*
		* This value indicates the type of IP address. 4 - IPv4 6 - IPv6 All
		* others are invalid.
		*/
		/* invalid */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
		/* IPv4 */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
		/* IPv6 */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
		uint8_t ip_protocol;
		/*
		* The value of protocol filed in IP header. Applies to UDP and TCP
		* traffic. 6 - TCP 17 - UDP
		*/
		/* invalid */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
		/* TCP */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
		/* UDP */
		#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
		uint8_t unused_4;
		uint8_t unused_5;
		uint8_t unused_6[3];
		uint8_t unused_7;
		uint32_t src_ipaddr[4]; /* big endian */
		/*
		* The value of source IP address to be used in filtering. For IPv4,
		* first four bytes represent the IP address.
		*/
		uint32_t dst_ipaddr[4]; /* big endian */
		/*
		* The value of destination IP address to be used in filtering. For
		* IPv4, first four bytes represent the IP address.
		*/
		uint16_t src_port; /* big endian */
		/*
		* The value of source port to be used in filtering. Applies to UDP and
		* TCP traffic.
		*/
		uint16_t dst_port; /* big endian */
		/*
		* The value of destination port to be used in filtering. Applies to UDP
		* and TCP traffic.
		*/
		uint16_t dst_id;
		/*
		* If set, this value shall represent the Logical VNIC ID of the
		* destination VNIC for the RX path.
		*/
		uint16_t l2_ctxt_ref_id;
		/*
		* If set, this value shall represent the L2 context that matches the L2
		* information of the decap filter.
		*/
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_decap_filter_alloc_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t decap_filter_id;
		/* This value is an opaque id into CFA data structures. */
		uint8_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_decap_filter_free */
		/* Description: Free an decap filter table entry */
		/* Input (24 bytes) */

		struct hwrm_cfa_decap_filter_free_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint32_t decap_filter_id;
		/* This value is an opaque id into CFA data structures. */
		uint32_t unused_0;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_decap_filter_free_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_flow_alloc */
		/* Description: Flow is added to table and resources are allocated. */
		/* Input (128 bytes) */

		struct hwrm_cfa_flow_alloc_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t flags;
		/* tunnel is 1 b */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL UINT32_C(0x1)
		/* num_vlan is 2 b */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK UINT32_C(0x6)
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
		/* no tags */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE (UINT32_C(0x0) << 1)
		/* 1 tag */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE (UINT32_C(0x1) << 1)
		/* 2 tags */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO (UINT32_C(0x2) << 1)
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
		/* Enumeration denoting the Flow Type. */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK UINT32_C(0x38)
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
		/* L2 flow */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 (UINT32_C(0x0) << 3)
		/* IPV4 flow */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 (UINT32_C(0x1) << 3)
		/* IPV6 flow */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 (UINT32_C(0x2) << 3)
		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
		uint16_t src_fid;
		/* Tx Flow: vf fid. Rx Flow: pf fid. */
		uint32_t tunnel_handle;
		/* Tunnel handle valid when tunnel flag is set. */
		uint16_t action_flags;
		/*
		* Setting of this flag indicates drop action. If this flag is not set,
		* then it should be considered accept action.
		*/
		#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD UINT32_C(0x1)
		/* recycle is 1 b */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE UINT32_C(0x2)
		/*
		* Setting of this flag indicates drop action. If this flag is not set,
		* then it should be considered accept action.
		*/
		#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP UINT32_C(0x4)
		/* meter is 1 b */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER UINT32_C(0x8)
		/* tunnel is 1 b */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL UINT32_C(0x10)
		/* nat_src is 1 b */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC UINT32_C(0x20)
		/* nat_dest is 1 b */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST UINT32_C(0x40)
		/* nat_ipv4_address is 1 b */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS UINT32_C(0x80)
		/* l2_header_rewrite is 1 b */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE UINT32_C(0x100)
		/* ttl_decrement is 1 b */
		#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT UINT32_C(0x200)
		uint16_t dst_fid;
		/* Tx Flow: pf or vf fid. Rx Flow: vf fid. */
		uint16_t l2_rewrite_vlan_tpid; /* big endian */
		/* VLAN tpid, valid when push_vlan flag is set. */
		uint16_t l2_rewrite_vlan_tci; /* big endian */
		/* VLAN tci, valid when push_vlan flag is set. */
		uint16_t act_meter_id;
		/* Meter id, valid when meter flag is set. */
		uint16_t ref_flow_handle;
		/* Flow with the same l2 context tcam key. */
		uint16_t ethertype; /* big endian */
		/* This value sets the match value for the ethertype. */
		uint16_t outer_vlan_tci; /* big endian */
		/* valid when num tags is 1 or 2. */
		uint16_t dmac[3]; /* big endian */
		/* This value sets the match value for the Destination MAC address. */
		uint16_t inner_vlan_tci; /* big endian */
		/* valid when num tags is 2. */
		uint16_t smac[3]; /* big endian */
		/* This value sets the match value for the Source MAC address. */
		uint8_t ip_dst_mask_len;
		/* The bit length of destination IP address mask. */
		uint8_t ip_src_mask_len;
		/* The bit length of source IP address mask. */
		uint32_t ip_dst[4]; /* big endian */
		/* The value of destination IPv4/IPv6 address. */
		uint32_t ip_src[4]; /* big endian */
		/* The source IPv4/IPv6 address. */
		uint16_t l4_src_port; /* big endian */
		/* The value of source port. Applies to UDP and TCP traffic. */
		uint16_t l4_src_port_mask; /* big endian */
		/* The value of source port mask. Applies to UDP and TCP traffic. */
		uint16_t l4_dst_port; /* big endian */
		/* The value of destination port. Applies to UDP and TCP traffic. */
		uint16_t l4_dst_port_mask; /* big endian */
		/* The value of destination port mask. Applies to UDP and TCP traffic. */
		uint32_t nat_ip_address[4]; /* big endian */
		/* NAT IPv4/6 address based on address type flag. 0 values are ignored. */
		uint16_t l2_rewrite_dmac[3]; /* big endian */
		/* L2 header re-write Destination MAC address. */
		uint16_t nat_port; /* big endian */
		/*
		* The NAT source/destination port based on direction flag. Applies to
		* UDP and TCP traffic. 0 values are ignored.
		*/
		uint16_t l2_rewrite_smac[3]; /* big endian */
		/* L2 header re-write Source MAC address. */
		uint8_t ip_proto;
		/* The value of ip protocol. */
		uint8_t unused_0;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_flow_alloc_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint16_t flow_handle;
		/* Flow record index. */
		uint8_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t unused_4;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_flow_free */
		/* Description: Flow is removed from table and resources are released. */
		/* Input (24 bytes) */

		struct hwrm_cfa_flow_free_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t flow_handle;
		/* Flow record index. */
		uint16_t unused_0[3];
		} __attribute__((packed));

		/* Output (32 bytes) */

		struct hwrm_cfa_flow_free_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint64_t packet;
		/* packet is 64 b */
		uint64_t byte;
		/* byte is 64 b */
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_flow_info */
		/* Description: Flow record content for specified flow is returned. */
		/* Input (24 bytes) */

		struct hwrm_cfa_flow_info_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t flow_handle;
		/* Flow record index. */
		/* Max flow handle */
		#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK UINT32_C(0xfff)
		#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
		/* CNP flow handle */
		#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT UINT32_C(0x1000)
		/* Reserved */
		#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_RESERVED_MASK UINT32_C(0x6000)
		#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_RESERVED_SFT 13
		/* Direction rx = 1 */
		#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX UINT32_C(0x8000)
		uint16_t unused_0[3];
		} __attribute__((packed));

		/* Output (56 bytes) */

		struct hwrm_cfa_flow_info_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint8_t flags;
		/* flags is 8 b */
		uint8_t profile;
		/* profile is 8 b */
		uint16_t src_fid;
		/* src_fid is 16 b */
		uint16_t dst_fid;
		/* dst_fid is 16 b */
		uint16_t l2_ctxt_id;
		/* l2_ctxt_id is 16 b */
		uint64_t em_info;
		/* em_info is 64 b */
		uint64_t tcam_info;
		/* tcam_info is 64 b */
		uint64_t vfp_tcam_info;
		/* vfp_tcam_info is 64 b */
		uint16_t ar_id;
		/* ar_id is 16 b */
		uint16_t flow_handle;
		/* flow_handle is 16 b */
		uint32_t tunnel_handle;
		/* tunnel_handle is 32 b */
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_flow_flush */
		/* Description: All flows are removed from table and resources are released. */
		/* Input (24 bytes) */

		struct hwrm_cfa_flow_flush_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint32_t flags;
		uint32_t unused_0;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_flow_flush_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_flow_stats */
		/* Description: Flow is removed from table and resources are released. */
		/* Input (40 bytes) */

		struct hwrm_cfa_flow_stats_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t num_flows;
		/* Flow handle. */
		uint16_t flow_handle_0;
		/* Flow handle. */
		uint16_t flow_handle_1;
		/* Flow handle. */
		uint16_t flow_handle_2;
		/* Flow handle. */
		uint16_t flow_handle_3;
		/* Flow handle. */
		uint16_t flow_handle_4;
		/* Flow handle. */
		uint16_t flow_handle_5;
		/* Flow handle. */
		uint16_t flow_handle_6;
		/* Flow handle. */
		uint16_t flow_handle_7;
		/* Flow handle. */
		uint16_t flow_handle_8;
		/* Flow handle. */
		uint16_t flow_handle_9;
		/* Flow handle. */
		uint16_t unused_0;
		} __attribute__((packed));

		/* Output (176 bytes) */

		struct hwrm_cfa_flow_stats_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint64_t packet_0;
		/* packet_0 is 64 b */
		uint64_t packet_1;
		/* packet_1 is 64 b */
		uint64_t packet_2;
		/* packet_2 is 64 b */
		uint64_t packet_3;
		/* packet_3 is 64 b */
		uint64_t packet_4;
		/* packet_4 is 64 b */
		uint64_t packet_5;
		/* packet_5 is 64 b */
		uint64_t packet_6;
		/* packet_6 is 64 b */
		uint64_t packet_7;
		/* packet_7 is 64 b */
		uint64_t packet_8;
		/* packet_8 is 64 b */
		uint64_t packet_9;
		/* packet_9 is 64 b */
		uint64_t byte_0;
		/* byte_0 is 64 b */
		uint64_t byte_1;
		/* byte_1 is 64 b */
		uint64_t byte_2;
		/* byte_2 is 64 b */
		uint64_t byte_3;
		/* byte_3 is 64 b */
		uint64_t byte_4;
		/* byte_4 is 64 b */
		uint64_t byte_5;
		/* byte_5 is 64 b */
		uint64_t byte_6;
		/* byte_6 is 64 b */
		uint64_t byte_7;
		/* byte_7 is 64 b */
		uint64_t byte_8;
		/* byte_8 is 64 b */
		uint64_t byte_9;
		/* byte_9 is 64 b */
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_vf_pair_alloc */
		/* Description: VF pair is added to table and resources are allocated. */
		/* Input (32 bytes) */

		struct hwrm_cfa_vf_pair_alloc_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t vf_a_id;
		/* Logical VF number (range: 0 -> MAX_VFS -1). */
		uint16_t vf_b_id;
		/* Logical VF number (range: 0 -> MAX_VFS -1). */
		uint32_t unused_0;
		char pair_name[32];
		/* VF Pair name (32 byte string). */
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_vf_pair_alloc_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_vf_pair_free */
		/* Description: VF Pair is removed from table and resources are released. */
		/* Input (24 bytes) */

		struct hwrm_cfa_vf_pair_free_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		char pair_name[32];
		/* VF Pair name (32 byte string). */
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_vf_pair_free_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_vf_pair_info */
		/* Description: VF pair information is returned. */
		/* Input (32 bytes) */

		struct hwrm_cfa_vf_pair_info_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint32_t flags;
		/* If this flag is set, lookup by name else lookup by index. */
		#define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
		uint16_t vf_pair_index;
		/* vf pair table index. */
		uint8_t unused_0;
		uint8_t unused_1;
		char vf_pair_name[32];
		/* VF Pair name (32 byte string). */
		} __attribute__((packed));

		/* Output (64 bytes) */

		struct hwrm_cfa_vf_pair_info_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint16_t next_vf_pair_index;
		/* vf pair table index. */
		uint16_t vf_a_fid;
		/* vf pair member a's vf_fid. */
		uint16_t vf_a_index;
		/* vf pair member a's Linux logical VF number. */
		uint16_t vf_b_fid;
		/* vf pair member b's vf_fid. */
		uint16_t vf_b_index;
		/* vf pair member a's Linux logical VF number. */
		uint8_t pair_state;
		/* vf pair state. */
		/* Pair has been allocated */
		#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
		/* Both pair members are active */
		#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
		uint8_t unused_0;
		uint32_t unused_1;
		char pair_name[32];
		/* VF Pair name (32 byte string). */
		uint32_t unused_2;
		uint8_t unused_3;
		uint8_t unused_4;
		uint8_t unused_5;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_vfr_alloc */
		/* Description: VF-R is added to table and resources are allocated. */
		/* Input (32 bytes) */

		struct hwrm_cfa_vfr_alloc_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t vf_id;
		/* Logical VF number (range: 0 -> MAX_VFS -1). */
		uint16_t reserved;
		/* This field is reserved for the future use. It shall be set to 0. */
		uint32_t unused_0;
		char vfr_name[32];
		/* VF Representor name (32 byte string). */
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_vfr_alloc_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint16_t rx_cfa_code;
		/* Rx CFA code. */
		uint16_t tx_cfa_action;
		/* Tx CFA action. */
		uint8_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_cfa_vfr_free */
		/* Description: VF-R is removed from table and resources are released. */
		/* Input (24 bytes) */

		struct hwrm_cfa_vfr_free_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		char vfr_name[32];
		/* VF Representor name (32 byte string). */
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_cfa_vfr_free_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

	/* hwrm_tunnel_dst_port_query */	/* hwrm_tunnel_dst_port_query */
	/*	/*
	* Description: This function is called by a driver to query tunnel type	* Description: This function is called by a driver to query tunnel type
Context not available.
	uint32_t update_period_ms;	uint32_t update_period_ms;
	/*	/*
	* The statistic block update period in ms. e.g. 250ms, 500ms, 750ms,	* The statistic block update period in ms. e.g. 250ms, 500ms, 750ms,
	* 1000ms.	* 1000ms. If update_period_ms is 0, then the stats update shall be
		* never done and the DMA address shall not be used. In this case, the
		* stat block can only be read by hwrm_stat_ctx_query command.
	*/	*/
	uint32_t unused_0;	uint8_t stat_ctx_flags;
		/*
		* This field is used to specify statistics context specific
		* configuration flags.
		*/
		/*
		* When this bit is set to '1', the statistics context shall be
		* allocated for RoCE traffic only. In this case, traffic other than
		* offloaded RoCE traffic shall not be included in this statistic
		* context. When this bit is set to '0', the statistics context shall be
		* used for the network traffic other than offloaded RoCE traffic.
		*/
		#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
		uint8_t unused_0[3];
	} __attribute__((packed));	} __attribute__((packed));

	/* Output (16 bytes) */	/* Output (16 bytes) */
Context not available.
	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2)	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2)
	/* RoCE control processor */	/* RoCE control processor */
	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3)	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3)
	/* Reserved */	/*
	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_RSVD UINT32_C(0x4)	* Host (in multi-host environment): This is only valid if
		* requester is IPC
		*/
		#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4)
	uint8_t selfrst_status;	uint8_t selfrst_status;
	/* Type of self reset. */	/* Type of self reset. */
	/* No Self Reset */	/* No Self Reset */
Context not available.
	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1)	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1)
	/* Self Reset on PCIe Reset */	/* Self Reset on PCIe Reset */
	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2)	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2)
	uint16_t unused_0[3];	uint8_t host_idx;
		/*
		* Indicate which host is being reset. 0 means first host. Only valid
		* when embedded_proc_type is host in multihost environment
		*/
		uint8_t unused_0[5];
	} __attribute__((packed));	} __attribute__((packed));

	/* Output (16 bytes) */	/* Output (16 bytes) */
Context not available.
	#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2)	#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2)
	/* RoCE control processor */	/* RoCE control processor */
	#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3)	#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3)
	/* Reserved */	/*
	#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_RSVD UINT32_C(0x4)	* Host (in multi-host environment): This is only valid if
		* requester is IPC
		*/
		#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4)
	uint8_t unused_0[7];	uint8_t unused_0[7];
	} __attribute__((packed));	} __attribute__((packed));

Context not available.
	*/	*/
	} __attribute__((packed));	} __attribute__((packed));

		/* hwrm_fw_set_structured_data */
		/*
		* Description: There can be a variable number of Structure Data Headers (SDH)
		* between offset 0x0 and the 'valid' field to handle customizable return
		* values. Each Structure Data Header will include one defined structure. The
		* number of returned structures can be 0, in which case the 'valid' field
		* starts at offset 0x8. The 'valid' field offset is adjusted based on the
		* Structure Data Header length and the length of the structured data it
		* contains.
		*/
		/* Input (32 bytes) */

		struct hwrm_fw_set_structured_data_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint64_t src_data_addr;
		/* This is the host address where structured data will be copied from */
		uint16_t data_len;
		/* size of data in bytes */
		uint8_t hdr_cnt;
		/*
		* a count of the number of Structured Data Headers in the data pointed
		* by src_data_addr.
		*/
		uint8_t unused_0[5];
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_fw_set_structured_data_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* Command specific Error Codes (8 bytes) */

		struct hwrm_fw_set_structured_data_cmd_err {
		uint8_t code;
		/*
		* command specific error codes that goes to the cmd_err field in Common
		* HWRM Error Response.
		*/
		/* Unknown error */
		#define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
		/* count_of_headers is incorrect */
		#define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT UINT32_C(0x1)
		/* data improperly formatted */
		#define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT UINT32_C(0x2)
		/* unknown structure ID(s) */
		#define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID UINT32_C(0x3)
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* hwrm_fw_get_structured_data */
		/* Input (32 bytes) */

		struct hwrm_fw_get_structured_data_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint64_t dest_data_addr;
		/* This is the host address where structured data will be copied to */
		uint16_t data_len;
		/* size of data in bytes */
		uint16_t structure_id;
		/*
		* Structure_id is the id of the structure data requesting and count is
		* a requested number of instances of this data requested. The actual
		* number will be returned in count_of_headers
		*/
		uint16_t subtype;
		/*
		* Subtype is an optional field used to specify additional information
		* of the data being retrieved. For example, if data can be categorized
		* as "live" vs "saved" then this field can be used to provide an
		* indication of "saved" vs "live" data. Not all structured data
		* supports subtypes and if they are supported then the structured data
		* will specify the valid values. If structured data is requested that
		* supports subtypes but no subtype is given then it is implementation
		* specific what will be returned. Some structure data can support a
		* subtype of "All" which would cause a list of structures to be
		* returned for all supported subtypes. "All" is only used on the
		* hwrm_get_structured_data command.
		*/
		#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_ALL UINT32_C(0xffff)
		#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_ADMIN UINT32_C(0x100)
		#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_PEER UINT32_C(0x101)
		#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_OPERATIONAL UINT32_C(0x102)
		#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_ADMIN UINT32_C(0x200)
		#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_PEER UINT32_C(0x201)
		#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_OPERATIONAL UINT32_C(0x202)
		#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_HOST_OPERATIONAL UINT32_C(0x300)
		uint8_t count;
		/* Number of elements. This allows support of arrayed data */
		uint8_t unused_0;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_fw_get_structured_data_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint8_t hdr_cnt;
		/*
		* a count of the number of Structured Data Headers in the data pointed
		* by dest_data_addr.
		*/
		uint8_t unused_0;
		uint16_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t unused_4;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* Command specific Error Codes (8 bytes) */

		struct hwrm_fw_get_structured_data_cmd_err {
		uint8_t code;
		/*
		* command specific error codes that goes to the cmd_err field in Common
		* HWRM Error Response.
		*/
		/* Unknown error */
		#define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
		/* unknown structure ID(s) */
		#define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID UINT32_C(0x3)
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* hwrm_fw_ipc_mailbox */
		/* Input (32 bytes) */

		struct hwrm_fw_ipc_mailbox_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint8_t flags;
		uint8_t unused_0;
		/* unused is 8 b */
		uint8_t event_id;
		/* asynchronous event to hosts. */
		uint8_t port_id;
		/* PORT ID */
		uint32_t event_data1;
		/* event data1 of asynchronous event */
		uint32_t event_data2;
		/* event data2 of asynchronous event */
		uint32_t unused_1;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_fw_ipc_mailbox_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* Command specific Error Codes (8 bytes) */

		struct hwrm_fw_ipc_mailbox_cmd_err {
		uint8_t code;
		/*
		* command specific error codes that goes to the cmd_err field in Common
		* HWRM Error Response.
		*/
		/* Unknown error */
		#define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
		/* invalid event */
		#define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID UINT32_C(0x3)
		uint8_t unused_0[7];
		} __attribute__((packed));

	/* hwrm_exec_fwd_resp */	/* hwrm_exec_fwd_resp */
	/*	/*
	* Description: This command is used to send an encapsulated request to the	* Description: This command is used to send an encapsulated request to the
Context not available.
	* HWRM is not required to provide pattern when the response contains a	* HWRM is not required to provide pattern when the response contains a
	* bitmap WoL filter.	* bitmap WoL filter.
	*/	*/
	uint64_t pattern_buf_size;	uint16_t pattern_buf_size;
	/* The sixe of the pattern buffer. Applies to bitmap WoL filter only. */	/* The size of the pattern buffer. Applies to bitmap WoL filter only. */
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3[3];
		uint8_t unused_4;
	uint64_t pattern_mask_addr;	uint64_t pattern_mask_addr;
	/*	/*
	* Physical address of the pattern mask. Applies to bitmap WoL filter	* Physical address of the pattern mask. Applies to bitmap WoL filter
Context not available.
	* the HWRM is not required to provide mask when the response contains a	* the HWRM is not required to provide mask when the response contains a
	* bitmap WoL filter.	* bitmap WoL filter.
	*/	*/
	uint64_t pattern_mask_size;	uint16_t pattern_mask_size;
	/*	/*
	* The size of the buffer for pattern mask. Applies to bitmap WoL filter	* The size of the buffer for pattern mask. Applies to bitmap WoL filter
	* only.	* only.
	*/	*/
		uint16_t unused_5[3];
	} __attribute__((packed));	} __attribute__((packed));

	/* Output (32 bytes) */	/* Output (32 bytes) */
Context not available.
	uint8_t unused_3;	uint8_t unused_3;
	uint64_t wol_pkt_buf_addr;	uint64_t wol_pkt_buf_addr;
	/* Physical address of the packet buffer for querying WoL packet. */	/* Physical address of the packet buffer for querying WoL packet. */
	uint64_t wol_pkt_buf_size;	uint16_t wol_pkt_buf_size;
	/* The size of the buffer for the WoL packet. */	/* The size of the buffer for the WoL packet. */
		uint16_t unused_4[3];
	} __attribute__((packed));	} __attribute__((packed));

	/* Output (16 bytes) */	/* Output (16 bytes) */
Context not available.
	#define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_BMP UINT32_C(0x1)	#define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_BMP UINT32_C(0x1)
	/* Invalid */	/* Invalid */
	#define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_INVALID UINT32_C(0xff)	#define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_INVALID UINT32_C(0xff)
		uint8_t wol_pkt_len;
		/* The value identifies the length of the WoL packet in bytes. */
	uint8_t unused_0;	uint8_t unused_0;
	uint8_t unused_1;	uint8_t unused_1;
	uint8_t unused_2;	uint8_t unused_2;
	uint8_t unused_3;	uint8_t unused_3;
	uint8_t unused_4;
	uint8_t valid;	uint8_t valid;
	/*	/*
	* This field is used in Output records to indicate that the output is	* This field is used in Output records to indicate that the output is
Context not available.
	*/	*/
	} __attribute__((packed));	} __attribute__((packed));

		/* hwrm_dbg_read_direct */
		/*
		* Description: ChiMP HWRM will read data from specified ChiMP view address, and
		* DMA content to specified host buffer.
		*/
		/* Input (32 bytes) */

		struct hwrm_dbg_read_direct_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint64_t host_dest_addr;
		/*
		* host address where the data content will be written when the request
		* is complete. This area must be 16B aligned.
		*/
		uint32_t read_addr;
		/* address(in ChiMP view) to start reading */
		uint32_t read_len32;
		/* number of dwords to read */
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_dbg_read_direct_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_dbg_write_direct */
		/*
		* Description: ChiMP HWRM will write data to specified ChiMP view address, up
		* to 8 dwords can be specified.
		*/
		/* Input (32 bytes) */

		struct hwrm_dbg_write_direct_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint32_t write_addr;
		/* address(in ChiMP view) to start writing */
		uint32_t write_len32;
		/* number of dwords to write (up to 8 dwords) */
		uint32_t write_data[8];
		/* write data (up to 8 dwords) */
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_dbg_write_direct_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_dbg_read_indirect */
		/*
		* Description: ChiMP HWRM will perform multiple entries read, given indirect
		* address type, index address and number of entries. This command is used to
		* read from on-chip data structures like tables, filters, contexts, etc.
		*/
		/* Input (40 bytes) */

		struct hwrm_dbg_read_indirect_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint64_t host_dest_addr;
		/*
		* host address where the data content will be written when the request
		* is complete. This area must be 16B aligned.
		*/
		uint32_t host_dest_addr_len;
		/* Length of host buffer used for transferring debug data. */
		uint8_t indirect_access_type;
		/* Indirect access type to on-chip data structures. */
		/* L2 Mgmt filters in Transmit Engine (TE) */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2 UINT32_C(0x0)
		/* L3/L4 Mgmt filters in Transmit Engine (TE) */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4 UINT32_C(0x1)
		/* L2 Mgmt filters in Receive Engine (RE) */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2 UINT32_C(0x2)
		/* L3/L4 Mgmt filters in Receive Engine (RE) */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4 UINT32_C(0x3)
		/* Statistics contexts */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STAT_CTXS UINT32_C(0x4)
		/* TX L2 TCAM */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM UINT32_C(0x5)
		/* RX L2 TCAM */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM UINT32_C(0x6)
		/* TX IPv6 subnet TCAM */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM UINT32_C(0x7)
		/* RX IPv6 subnet TCAM */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM UINT32_C(0x8)
		/* TX source properties TCAM */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM UINT32_C(0x9)
		/* RX source properties TCAM */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM UINT32_C(0xa)
		/* VEB Lookup TCAM */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM UINT32_C(0xb)
		/* TX Profile Lookup TCAM */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM UINT32_C(0xc)
		/* RX Profile Lookup TCAM */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM UINT32_C(0xd)
		/* TX Lookup TCAM */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM UINT32_C(0xe)
		/* RX Lookup TCAM */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM UINT32_C(0xf)
		/* MHB registers (valid for multi-host environment) */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MHB UINT32_C(0x10)
		/* PCIE global registers (valid for multi-host environment) */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_GBL UINT32_C(0x11)
		/* SOC registers (valid for multi-host environment) */
		#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC UINT32_C(0x12)
		uint8_t unused_0;
		uint16_t unused_1;
		uint32_t start_index;
		/* Entry number to start reading */
		uint32_t num_of_entries;
		/* Total number of entries to read */
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_dbg_read_indirect_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_dbg_write_indirect */
		/*
		* Description: ChiMP HWRM will perform write of multiple entries, given
		* indirect address type, index address and number of entries. This command is
		* used to write to on-chip data structures like tables, filters, contexts, etc.
		*/
		/* Input (40 bytes) */

		struct hwrm_dbg_write_indirect_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint8_t indirect_access_type;
		/* Indirect access type to on-chip data structures. */
		/* L2 Mgmt filters in Transmit Engine (TE) */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2 UINT32_C(0x0)
		/* L3/L4 Mgmt filters in Transmit Engine (TE) */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4 UINT32_C(0x1)
		/* L2 Mgmt filters in Receive Engine (RE) */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2 UINT32_C(0x2)
		/* L3/L4 Mgmt filters in Receive Engine (RE) */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4 UINT32_C(0x3)
		/* Statistics contexts */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STAT_CTXS UINT32_C(0x4)
		/* TX L2 TCAM */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM UINT32_C(0x5)
		/* RX L2 TCAM */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM UINT32_C(0x6)
		/* TX IPv6 subnet TCAM */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM UINT32_C(0x7)
		/* RX IPv6 subnet TCAM */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM UINT32_C(0x8)
		/* TX source properties TCAM */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM UINT32_C(0x9)
		/* RX source properties TCAM */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM UINT32_C(0xa)
		/* VEB Lookup TCAM */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM UINT32_C(0xb)
		/* TX Profile Lookup TCAM */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM UINT32_C(0xc)
		/* RX Profile Lookup TCAM */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM UINT32_C(0xd)
		/* TX Lookup TCAM */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM UINT32_C(0xe)
		/* RX Lookup TCAM */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM UINT32_C(0xf)
		/* MHB registers (valid for multi-host environment) */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MHB UINT32_C(0x10)
		/* PCIE global registers (valid for multi-host environment) */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_GBL UINT32_C(0x11)
		/* SOC registers (valid for multi-host environment) */
		#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC UINT32_C(0x12)
		uint8_t unused_0;
		uint16_t unused_1;
		uint32_t start_index;
		/* Entry number to start reading */
		uint32_t num_of_entries;
		/* Total number of entries to read */
		uint32_t unused_2;
		uint32_t write_data[8];
		/* write data (up to 8 dwords) */
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_dbg_write_indirect_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

	/* hwrm_dbg_dump */	/* hwrm_dbg_dump */
	/*	/*
	* Description: This command is used by to initiate the dump of debug	* Description: This command is used by to initiate the dump of debug
Context not available.
	*/	*/
	} __attribute__((packed));	} __attribute__((packed));

		/* hwrm_dbg_erase_nvm */
		/* Input (24 bytes) */

		struct hwrm_dbg_erase_nvm_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint16_t flags;
		/* If set to 1, then erase all locations in persistent storage. */
		#define HWRM_DBG_ERASE_NVM_INPUT_FLAGS_ERASE_ALL UINT32_C(0x1)
		uint16_t unused_0[3];
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_dbg_erase_nvm_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* hwrm_dbg_cfg */
		/* Description: This command is used by to configure debug settings. */
		/* Input (24 bytes) */

		struct hwrm_dbg_cfg_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint32_t flags;
		/* If set to 1, then UART logging will be enabled. Disabled otherwise. */
		#define HWRM_DBG_CFG_INPUT_FLAGS_UART_LOG UINT32_C(0x1)
		uint32_t unused_0;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_dbg_cfg_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

	/* hwrm_nvm_raw_write_blk */	/* hwrm_nvm_raw_write_blk */
	/*	/*
	* Note: Write an unmanaged block of data at any physical offset within the	* Note: Write an unmanaged block of data at any physical offset within the
Context not available.
	* allocated item length, which may be greater than the requested item	* allocated item length, which may be greater than the requested item
	* length. The purpose for allocating more than the required number of	* length. The purpose for allocating more than the required number of
	* bytes for an item's data is to pre-allocate extra storage (padding)	* bytes for an item's data is to pre-allocate extra storage (padding)
	* to accommodate the potential future growth of an item (e.g. upgraded	* to accomodate the potential future growth of an item (e.g. upgraded
	* firmware with a size increase, log growth, expanded configuration	* firmware with a size increase, log growth, expanded configuration
	* data).	* data).
	*/	*/
Context not available.
	*/	*/
	} __attribute__((packed));	} __attribute__((packed));

		/* Command specific Error Codes (8 bytes) */

		struct hwrm_nvm_write_cmd_err {
		uint8_t code;
		/*
		* command specific error codes that goes to the cmd_err field in Common
		* HWRM Error Response.
		*/
		/* Unknown error */
		#define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
		/* Unable to complete operation due to fragmentation */
		#define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
		/* nvm is completely full. */
		#define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
		uint8_t unused_0[7];
		} __attribute__((packed));

	/* hwrm_nvm_modify */	/* hwrm_nvm_modify */
	/*	/*
	* Note: Modify the contents of an NVRAM item as referenced (indexed) by an	* Note: Modify the contents of an NVRAM item as referenced (indexed) by an
Context not available.
	* an installation directive of 'install').	* an installation directive of 'install').
	*/	*/
	#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL UINT32_C(0xffffffff)	#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL UINT32_C(0xffffffff)
	uint32_t unused_0;	uint16_t flags;
		/*
		* If set to 1, then securely erase all unused locations in persistent
		* storage.
		*/
		#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE UINT32_C(0x1)
		/*
		* If set to 1, then unspecifed images, images not in the package file,
		* will be safely deleted. When combined with erase_unused_space then
		* unspecified images will be securely erased.
		*/
		#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG UINT32_C(0x2)
		/*
		* If set to 1, FW will defragment the NVM if defragmentation is
		* required for the update. Allow additional time for this command to
		* complete if this bit is set to 1.
		*/
		#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG UINT32_C(0x4)
		uint16_t unused_0;
	} __attribute__((packed));	} __attribute__((packed));

	/* Output (24 bytes) */	/* Output (24 bytes) */
Context not available.
	*/	*/
	} __attribute__((packed));	} __attribute__((packed));

		/* Command specific Error Codes (8 bytes) */

		struct hwrm_nvm_install_update_cmd_err {
		uint8_t code;
		/*
		* command specific error codes that goes to the cmd_err field in Common
		* HWRM Error Response.
		*/
		/* Unknown error */
		#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
		/* Unable to complete operation due to fragmentation */
		#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
		/* nvm is completely full. */
		#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* hwrm_nvm_flush */
		/* Input (16 bytes) */

		struct hwrm_nvm_flush_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_nvm_flush_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* Command specific Error Codes (8 bytes) */

		struct hwrm_nvm_flush_cmd_err {
		uint8_t code;
		/*
		* command specific error codes that goes to the cmd_err field in Common
		* HWRM Error Response.
		*/
		/* Unknown error */
		#define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
		/* flush could not be performed */
		#define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* hwrm_nvm_get_variable */
		/* Input (40 bytes) */

		struct hwrm_nvm_get_variable_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint64_t dest_data_addr;
		/* This is the host address where nvm variable will be stored */
		uint16_t data_len;
		/* size of data in bits */
		uint16_t option_num;
		/* nvm cfg option number */
		/* reserved. */
		#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
		/* reserved. */
		#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
		uint16_t dimensions;
		/*
		* Number of dimensions for this nvm configuration variable. This value
		* indicates how many of the indexN values to use. A value of 0 means
		* that none of the indexN values are valid. A value of 1 requires at
		* index0 is valued, a value of 2 requires that index0 and index1 are
		* valid, and so forth
		*/
		uint16_t index_0;
		/* index for the 1st dimensions */
		uint16_t index_1;
		/* index for the 2nd dimensions */
		uint16_t index_2;
		/* index for the 3rd dimensions */
		uint16_t index_3;
		/* index for the 4th dimensions */
		uint8_t flags;
		/*
		* When this bit is set to 1, the factory default value will be
		* returned, 0 returns the operational value.
		*/
		#define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT UINT32_C(0x1)
		uint8_t unused_0;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_nvm_get_variable_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint16_t data_len;
		/* size of data of the actual variable retrieved in bits */
		uint16_t option_num;
		/*
		* option_num is the option number for the data retrieved. It is
		* possible in the future that the option number returned would be
		* different than requested. This condition could occur if an option is
		* deprecated and a new option id is defined with similar
		* characteristics, but has a slightly different definition. This also
		* makes it convenient for the caller to identify the variable result
		* with the option id from the response.
		*/
		/* reserved. */
		#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
		/* reserved. */
		#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
		uint8_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* Command specific Error Codes (8 bytes) */

		struct hwrm_nvm_get_variable_cmd_err {
		uint8_t code;
		/*
		* command specific error codes that goes to the cmd_err field in Common
		* HWRM Error Response.
		*/
		/* Unknown error */
		#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
		/* variable does not exist */
		#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
		/* configuration is corrupted and the variable cannot be saved */
		#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
		/* length specified is too small */
		#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* hwrm_nvm_set_variable */
		/* Input (40 bytes) */

		struct hwrm_nvm_set_variable_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint64_t src_data_addr;
		/* This is the host address where nvm variable will be copied from */
		uint16_t data_len;
		/* size of data in bits */
		uint16_t option_num;
		/* nvm cfg option number */
		/* reserved. */
		#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
		/* reserved. */
		#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
		uint16_t dimensions;
		/*
		* Number of dimensions for this nvm configuration variable. This value
		* indicates how many of the indexN values to use. A value of 0 means
		* that none of the indexN values are valid. A value of 1 requires at
		* index0 is valued, a value of 2 requires that index0 and index1 are
		* valid, and so forth
		*/
		uint16_t index_0;
		/* index for the 1st dimensions */
		uint16_t index_1;
		/* index for the 2nd dimensions */
		uint16_t index_2;
		/* index for the 3rd dimensions */
		uint16_t index_3;
		/* index for the 4th dimensions */
		uint8_t flags;
		/*
		* When this bit is 1, flush internal cache after this write operation
		* (see hwrm_nvm_flush command.)
		*/
		#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH UINT32_C(0x1)
		/* encryption method */
		#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK UINT32_C(0xe)
		#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
		/* No encryption. */
		#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE (UINT32_C(0x0) << 1)
		/* one-way encryption. */
		#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (UINT32_C(0x1) << 1)
		#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1
		uint8_t unused_0;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_nvm_set_variable_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t unused_0;
		uint8_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* Command specific Error Codes (8 bytes) */

		struct hwrm_nvm_set_variable_cmd_err {
		uint8_t code;
		/*
		* command specific error codes that goes to the cmd_err field in Common
		* HWRM Error Response.
		*/
		/* Unknown error */
		#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
		/* variable does not exist */
		#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
		/* configuration is corrupted and the variable cannot be saved */
		#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* hwrm_nvm_validate_option */
		/* Input (40 bytes) */

		struct hwrm_nvm_validate_option_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint64_t src_data_addr;
		/* This is the host address where nvm variable will be copied from */
		uint16_t data_len;
		/* size of data in bits */
		uint16_t option_num;
		/* nvm cfg option number */
		/* reserved. */
		#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
		/* reserved. */
		#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
		uint16_t dimensions;
		/*
		* Number of dimensions for this nvm configuration variable. This value
		* indicates how many of the indexN values to use. A value of 0 means
		* that none of the indexN values are valid. A value of 1 requires at
		* index0 is valued, a value of 2 requires that index0 and index1 are
		* valid, and so forth
		*/
		uint16_t index_0;
		/* index for the 1st dimensions */
		uint16_t index_1;
		/* index for the 2nd dimensions */
		uint16_t index_2;
		/* index for the 3rd dimensions */
		uint16_t index_3;
		/* index for the 4th dimensions */
		uint16_t unused_0;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_nvm_validate_option_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint8_t result;
		/*
		* indicates that the value provided for the option is not
		* matching with the saved data.
		*/
		#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
		/*
		* indicates that the value provided for the option is matching
		* the saved data.
		*/
		#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
		uint8_t unused_0;
		uint16_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t unused_4;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* Command specific Error Codes (8 bytes) */

		struct hwrm_nvm_validate_option_cmd_err {
		uint8_t code;
		/*
		* command specific error codes that goes to the cmd_err field in Common
		* HWRM Error Response.
		*/
		/* Unknown error */
		#define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* hwrm_nvm_factory_defaults */
		/* Input (24 bytes) */

		struct hwrm_nvm_factory_defaults_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint8_t mode;
		/* mode is 8 b */
		/*
		* If set to 1, it will trigger restoration of factory default
		* settings
		*/
		#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_RESTORE UINT32_C(0x0)
		/* If set to 1, it will trigger creation of factory default settings */
		#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE UINT32_C(0x1)
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_nvm_factory_defaults_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint8_t result;
		/* factory defaults created successfully. */
		#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_OK UINT32_C(0x0)
		/* factory defaults restored successfully. */
		#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_RESTORE_OK UINT32_C(0x1)
		/* factory defaults already created. */
		#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY UINT32_C(0x2)
		uint8_t unused_0;
		uint16_t unused_1;
		uint8_t unused_2;
		uint8_t unused_3;
		uint8_t unused_4;
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* Command specific Error Codes (8 bytes) */

		struct hwrm_nvm_factory_defaults_cmd_err {
		uint8_t code;
		/*
		* command specific error codes that goes to the cmd_err field in Common
		* HWRM Error Response.
		*/
		/* Unknown error */
		#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
		/* valid configuration not present to create defaults */
		#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG UINT32_C(0x1)
		/* No saved configuration present to restore, restore failed */
		#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG UINT32_C(0x2)
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* Command Queue (CMDQ) Interface */
		/* Description: This command queries congestion control settings. */
		/* Init CMDQ (16 bytes) */

		struct cmdq_init {
		uint64_t cmdq_pbl;
		/* CMDQ PBL physical address. */
		uint16_t cmdq_size_cmdq_lvl;
		/* CMDQ size. */
		/* CMDQ PBL indirection levels. */
		#define CMDQ_INIT_CMDQ_LVL_MASK UINT32_C(0x3)
		#define CMDQ_INIT_CMDQ_LVL_SFT 0
		/* CMDQ size. */
		#define CMDQ_INIT_CMDQ_SIZE_MASK UINT32_C(0xfffc)
		#define CMDQ_INIT_CMDQ_SIZE_SFT 2
		uint16_t creq_ring_id;
		/* CREQ completion ring id. */
		uint32_t prod_idx;
		/* Mailbox producer index. MSB must also be set. */
		} __attribute__((packed));

		/* Update CMDQ producer index (16 bytes) */

		struct cmdq_update {
		uint64_t reserved64;
		/* reserved64 is 64 b */
		uint32_t reserved32;
		/* reserved32 is 32 b */
		uint32_t prod_idx;
		/* Mailbox producer index. */
		} __attribute__((packed));

		/* CMDQ common header structure (16 bytes) */

		struct cmdq_base {
		uint8_t opcode;
		/* Command opcode. */
		/*
		* Create QP command allocates QP context with the specified SQ,
		* RQ/SRQ, CQ and other parameters.
		*/
		#define CMDQ_BASE_OPCODE_CREATE_QP UINT32_C(0x1)
		/*
		* Destroy QP command deletes the QP context and ceases any
		* further reference.
		*/
		#define CMDQ_BASE_OPCODE_DESTROY_QP UINT32_C(0x2)
		/*
		* Modify QP command changes QP states and other QP specific
		* parameters.
		*/
		#define CMDQ_BASE_OPCODE_MODIFY_QP UINT32_C(0x3)
		/* Query QP command retrieves info about the specified QP. */
		#define CMDQ_BASE_OPCODE_QUERY_QP UINT32_C(0x4)
		/* Create SRQ command allocates a SRQ with the specified parameters. */
		#define CMDQ_BASE_OPCODE_CREATE_SRQ UINT32_C(0x5)
		/* Destroy SRQ command deletes and flushes the specified SRQ. */
		#define CMDQ_BASE_OPCODE_DESTROY_SRQ UINT32_C(0x6)
		/* Query SRP command retrieves info about the specified SRQ. */
		#define CMDQ_BASE_OPCODE_QUERY_SRQ UINT32_C(0x8)
		/* Create CQ command allocates a CQ with the specified parameters. */
		#define CMDQ_BASE_OPCODE_CREATE_CQ UINT32_C(0x9)
		/* Destroy CQ command deletes and flushes the specified CQ. */
		#define CMDQ_BASE_OPCODE_DESTROY_CQ UINT32_C(0xa)
		/* Resize CQ command resizes the specified CQ. */
		#define CMDQ_BASE_OPCODE_RESIZE_CQ UINT32_C(0xc)
		/*
		* Allocate MRW command allocates a MR/MW with the specified
		* parameters and returns the region's L_KEY/R_KEY
		*/
		#define CMDQ_BASE_OPCODE_ALLOCATE_MRW UINT32_C(0xd)
		/*
		* De-allocate key command frees a MR/MW entry associated with
		* the specified key.
		*/
		#define CMDQ_BASE_OPCODE_DEALLOCATE_KEY UINT32_C(0xe)
		/* Register MR command registers memory to the specified MR. */
		#define CMDQ_BASE_OPCODE_REGISTER_MR UINT32_C(0xf)
		/* Deregister MR command de-registers memory from the specified MR. */
		#define CMDQ_BASE_OPCODE_DEREGISTER_MR UINT32_C(0x10)
		/* Add GID command adds a GID to the local address table. */
		#define CMDQ_BASE_OPCODE_ADD_GID UINT32_C(0x11)
		/* Delete GID command deletes a GID from the local address table. */
		#define CMDQ_BASE_OPCODE_DELETE_GID UINT32_C(0x12)
		/* Modify GID command modifies a GID in the local address table. */
		#define CMDQ_BASE_OPCODE_MODIFY_GID UINT32_C(0x17)
		/* Query GID command queries a GID in the local address table. */
		#define CMDQ_BASE_OPCODE_QUERY_GID UINT32_C(0x18)
		/* Create QP1 command allocates a QP1 only. */
		#define CMDQ_BASE_OPCODE_CREATE_QP1 UINT32_C(0x13)
		/* Destroy QP1 command deletes and flushes the specified QP1. */
		#define CMDQ_BASE_OPCODE_DESTROY_QP1 UINT32_C(0x14)
		/* Create AH command allocates an AH with the specified parameters. */
		#define CMDQ_BASE_OPCODE_CREATE_AH UINT32_C(0x15)
		/* Destroy AH command deletes the specified AH. */
		#define CMDQ_BASE_OPCODE_DESTROY_AH UINT32_C(0x16)
		/*
		* Initialize firmware command initializes the firmware with the
		* specified parameters.
		*/
		#define CMDQ_BASE_OPCODE_INITIALIZE_FW UINT32_C(0x80)
		/* De-initialize firmware command deinitializes the firmware. */
		#define CMDQ_BASE_OPCODE_DEINITIALIZE_FW UINT32_C(0x81)
		/* Stop the function */
		#define CMDQ_BASE_OPCODE_STOP_FUNC UINT32_C(0x82)
		/* Query the HW capabilities for the function. */
		#define CMDQ_BASE_OPCODE_QUERY_FUNC UINT32_C(0x83)
		/*
		* Set the following resources for the function: - Max QP, CQ,
		* MR+MW, SRQ per PF - Max QP, CQ, MR+MW, SRQ per VF
		*/
		#define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84)
		/*
		* Read the current state of any internal resource context. Can
		* only be issued from a PF.
		*/
		#define CMDQ_BASE_OPCODE_READ_CONTEXT UINT32_C(0x85)
		/*
		* Send a request from VF to pass a command to the PF. VF HSI is
		* suspended until the PF returns the response
		*/
		#define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86)
		/*
		* Read VF memory (primarily to get the backchannel request
		* blob). Can only be issued from a PF.
		*/
		#define CMDQ_BASE_OPCODE_READ_VF_MEMORY UINT32_C(0x87)
		/*
		* Write VF memory (primarily to put the backchannel response
		* blob), and reenable VF HSI (post a CAG completion to it). Can
		* only be issued from a PF.
		*/
		#define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88)
		/*
		* Extend resource (QPC, MRW, CQ, SRQ) array, after the host
		* allocates more. Can only be issued from a PF.
		*/
		#define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY UINT32_C(0x89)
		/* Map TC to COS. Can only be issued from a PF. */
		#define CMDQ_BASE_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a)
		/* Query version. */
		#define CMDQ_BASE_OPCODE_QUERY_VERSION UINT32_C(0x8b)
		/* Modify congestion control. Can only be issued from a PF. */
		#define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c)
		/* Query congestion control. */
		#define CMDQ_BASE_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		} __attribute__((packed));

		/* Create QP command (96 bytes) */

		struct cmdq_create_qp {
		uint8_t opcode;
		/* Command opcode. */
		/*
		* Create QP command allocates QP context with the specified SQ,
		* RQ/SRQ, CQ and other parameters.
		*/
		#define CMDQ_CREATE_QP_OPCODE_CREATE_QP UINT32_C(0x1)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint64_t qp_handle;
		/* QP handle. */
		uint32_t qp_flags;
		/* Create QP flags. */
		/* SRQ is used. */
		#define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED UINT32_C(0x1)
		/* post CQE for all SQ WQEs. */
		#define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2)
		/* This QP can use reserved L_Key */
		#define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4)
		/* This QP can fast register physical memory */
		#define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED UINT32_C(0x8)
		uint8_t type;
		/* Supported QP types. */
		/* Reliable Connection. */
		#define CMDQ_CREATE_QP_TYPE_RC UINT32_C(0x2)
		/* Unreliable Datagram. */
		#define CMDQ_CREATE_QP_TYPE_UD UINT32_C(0x4)
		/* Raw Ethertype. */
		#define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE UINT32_C(0x6)
		uint8_t sq_pg_size_sq_lvl;
		/* SQ page size. */
		/* SQ PBL indirect levels. */
		#define CMDQ_CREATE_QP_SQ_LVL_MASK UINT32_C(0xf)
		#define CMDQ_CREATE_QP_SQ_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_CREATE_QP_SQ_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_CREATE_QP_SQ_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_CREATE_QP_SQ_LVL_LVL_2 UINT32_C(0x2)
		/* SQ page size. */
		#define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK UINT32_C(0xf0)
		#define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4
		/* 4KB. */
		#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
		/* 8KB. */
		#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
		/* 64KB. */
		#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
		/* 2MB. */
		#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
		/* 8MB. */
		#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
		/* 1GB. */
		#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
		uint8_t rq_pg_size_rq_lvl;
		/* RQ page size. */
		/* RQ PBL indirect levels. */
		#define CMDQ_CREATE_QP_RQ_LVL_MASK UINT32_C(0xf)
		#define CMDQ_CREATE_QP_RQ_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_CREATE_QP_RQ_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_CREATE_QP_RQ_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_CREATE_QP_RQ_LVL_LVL_2 UINT32_C(0x2)
		/* RQ page size. */
		#define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK UINT32_C(0xf0)
		#define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4
		/* 4KB. */
		#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
		/* 8KB. */
		#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
		/* 64KB. */
		#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
		/* 2MB. */
		#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
		/* 8MB. */
		#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
		/* 1GB. */
		#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
		uint8_t unused_0;
		uint32_t dpi;
		/* Doorbell page index. */
		uint32_t sq_size;
		/* Max number of SQ wqes. */
		uint32_t rq_size;
		/* Max number of RQ wqes. */
		uint16_t sq_fwo_sq_sge;
		/* Offset of First WQE in the first SQ page, in 128 byte units */
		/* Max send SGEs per SWQE. */
		#define CMDQ_CREATE_QP_SQ_SGE_MASK UINT32_C(0xf)
		#define CMDQ_CREATE_QP_SQ_SGE_SFT 0
		/* Offset of First WQE in the first SQ page, in 128 byte units */
		#define CMDQ_CREATE_QP_SQ_FWO_MASK UINT32_C(0xfff0)
		#define CMDQ_CREATE_QP_SQ_FWO_SFT 4
		uint16_t rq_fwo_rq_sge;
		/* Offset of First WQE in the first RQ page, in 128 byte units */
		/* Max recv SGEs per RWQE (NOT SUPPORTED BY HARDWARE). */
		#define CMDQ_CREATE_QP_RQ_SGE_MASK UINT32_C(0xf)
		#define CMDQ_CREATE_QP_RQ_SGE_SFT 0
		/* Offset of First WQE in the first RQ page, in 128 byte units */
		#define CMDQ_CREATE_QP_RQ_FWO_MASK UINT32_C(0xfff0)
		#define CMDQ_CREATE_QP_RQ_FWO_SFT 4
		uint32_t scq_cid;
		/* Send CQ context id. */
		uint32_t rcq_cid;
		/* Receive CQ context id. */
		uint32_t srq_cid;
		/* SRQ CQ context id. */
		uint32_t pd_id;
		/* Protection domain id. */
		uint64_t sq_pbl;
		/* SQ PBL physical address. */
		uint64_t rq_pbl;
		/* RQ PBL physical address. */
		uint64_t irrq_addr;
		/* IRRQ address. */
		uint64_t orrq_addr;
		/* ORRQ address. */
		} __attribute__((packed));

		/* Destroy QP command (24 bytes) */

		struct cmdq_destroy_qp {
		uint8_t opcode;
		/* Command opcode. */
		/*
		* Destroy QP command deletes the QP context and ceases any
		* further reference.
		*/
		#define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP UINT32_C(0x2)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t qp_cid;
		/* QP context id */
		uint32_t unused_0;
		} __attribute__((packed));

		/* Modify QP command (112 bytes) */

		struct cmdq_modify_qp {
		uint8_t opcode;
		/* Command opcode. */
		/*
		* Modify QP command changes QP states and other QP specific
		* parameters.
		*/
		#define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP UINT32_C(0x3)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t modify_mask;
		/* Modify mask signifies the field that is requesting the change. */
		/* QP state change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_STATE UINT32_C(0x1)
		/* Enable SQ drain asynchronous notification change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY UINT32_C(0x2)
		/* Access change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS UINT32_C(0x4)
		/* P_KEY change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY UINT32_C(0x8)
		/* Q_KEY index change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY UINT32_C(0x10)
		/* Destination GID change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_DGID UINT32_C(0x20)
		/* Flow label change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL UINT32_C(0x40)
		/* SGID change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX UINT32_C(0x80)
		/* Hop limit change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT UINT32_C(0x100)
		/* Traffic class change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS UINT32_C(0x200)
		/* destination MAC change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC UINT32_C(0x400)
		/* unused is 1 b */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_UNUSED UINT32_C(0x800)
		/* Path MTU change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU UINT32_C(0x1000)
		/* Timeout change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT UINT32_C(0x2000)
		/* Retry count change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT UINT32_C(0x4000)
		/* RNR Retry change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY UINT32_C(0x8000)
		/* RQ start packet sequence number change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN UINT32_C(0x10000)
		/* Max outstanding RDMA read atomic change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC UINT32_C(0x20000)
		/* RNR minimum timer change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER UINT32_C(0x40000)
		/* SQ start packet sequence number change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN UINT32_C(0x80000)
		/* Max destination outstanding RDMA read atomic change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC UINT32_C(0x100000)
		/* Max send WQE change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE UINT32_C(0x200000)
		/* Max recv WQE change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE UINT32_C(0x400000)
		/* Max recv SGEs per SWQE change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE UINT32_C(0x800000)
		/* Max send SGEs per RWQE change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE UINT32_C(0x1000000)
		/* Max inline data length change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA UINT32_C(0x2000000)
		/* Destination QP id change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID UINT32_C(0x4000000)
		/* Source MAC change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC UINT32_C(0x8000000)
		/* Source VLAN id change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID UINT32_C(0x10000000)
		/* Congestion control RoCE v2 change. */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC UINT32_C(0x20000000)
		/* IP TOS ECN change */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN UINT32_C(0x40000000)
		/* IP TOS DSCP change */
		#define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP UINT32_C(0x80000000)
		uint32_t qp_cid;
		/* QP context id. */
		uint8_t network_type_en_sqd_async_notify_new_state;
		/* network type. */
		/* New QP state. */
		#define CMDQ_MODIFY_QP_NEW_STATE_MASK UINT32_C(0xf)
		#define CMDQ_MODIFY_QP_NEW_STATE_SFT 0
		/* Reset. */
		#define CMDQ_MODIFY_QP_NEW_STATE_RESET UINT32_C(0x0)
		/* Init. */
		#define CMDQ_MODIFY_QP_NEW_STATE_INIT UINT32_C(0x1)
		/* Ready To Receive. */
		#define CMDQ_MODIFY_QP_NEW_STATE_RTR UINT32_C(0x2)
		/* Ready To Send. */
		#define CMDQ_MODIFY_QP_NEW_STATE_RTS UINT32_C(0x3)
		/* SQ Drain. */
		#define CMDQ_MODIFY_QP_NEW_STATE_SQD UINT32_C(0x4)
		/* SQ Error. */
		#define CMDQ_MODIFY_QP_NEW_STATE_SQE UINT32_C(0x5)
		/* Error. */
		#define CMDQ_MODIFY_QP_NEW_STATE_ERR UINT32_C(0x6)
		/* Enable SQ drain asynchronous notification. */
		#define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY UINT32_C(0x10)
		/* unused1 is 1 b */
		/* network type. */
		#define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK UINT32_C(0xc0)
		#define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6
		/* RoCEv1. */
		#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (UINT32_C(0x0) << 6)
		/* RoCEv2 IPv4. */
		#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (UINT32_C(0x2) << 6)
		/* RoCEv2 IPv6. */
		#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (UINT32_C(0x3) << 6)
		uint8_t access;
		/* Access flags. */
		/* Local write access. */
		#define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE UINT32_C(0x1)
		/* Remote write access. */
		#define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE UINT32_C(0x2)
		/* Remote read access. */
		#define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ UINT32_C(0x4)
		/* Remote atomic access. */
		#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC UINT32_C(0x8)
		uint16_t pkey;
		/* P_KEY. */
		uint32_t qkey;
		/* Q_KEY. */
		uint32_t dgid[4];
		/* Destination GID. */
		uint32_t flow_label;
		/* Flow label. */
		uint16_t sgid_index;
		/* Source GID index. */
		uint8_t hop_limit;
		/* Hop limit. */
		uint8_t traffic_class;
		/* Traffic class. */
		uint16_t dest_mac[3];
		/* Destination MAC address. */
		uint8_t tos_dscp_tos_ecn;
		/* IP TOS DSCP. */
		/* IP TOS ECN. Valid values are 1 or 2 when ECN is enabled. */
		#define CMDQ_MODIFY_QP_TOS_ECN_MASK UINT32_C(0x3)
		#define CMDQ_MODIFY_QP_TOS_ECN_SFT 0
		/* IP TOS DSCP. */
		#define CMDQ_MODIFY_QP_TOS_DSCP_MASK UINT32_C(0xfc)
		#define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2
		uint8_t path_mtu;
		/* Path MTU. */
		/* unused4 is 4 b */
		/* Path MTU. */
		#define CMDQ_MODIFY_QP_PATH_MTU_MASK UINT32_C(0xf0)
		#define CMDQ_MODIFY_QP_PATH_MTU_SFT 4
		/* 256. */
		#define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (UINT32_C(0x0) << 4)
		/* 512. */
		#define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (UINT32_C(0x1) << 4)
		/* 1024. */
		#define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (UINT32_C(0x2) << 4)
		/* 2048. */
		#define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (UINT32_C(0x3) << 4)
		/* 4096. */
		#define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (UINT32_C(0x4) << 4)
		/* 8192. */
		#define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (UINT32_C(0x5) << 4)
		uint8_t timeout;
		/* Timeout value for SWQEs. */
		uint8_t retry_cnt;
		/* Max retry count for WQEs. */
		uint8_t rnr_retry;
		/* Max RNR retry count for WQEs. */
		uint8_t min_rnr_timer;
		/* Min RNR timer that the QP will report to the remote. */
		uint32_t rq_psn;
		/* RQ start packet sequence number. */
		uint32_t sq_psn;
		/* SQ start packet sequence number. */
		uint8_t max_rd_atomic;
		/* Max outstanding RDMA read atomic. */
		uint8_t max_dest_rd_atomic;
		/* Max destination outstanding RDMA read atomic. */
		uint16_t enable_cc;
		/* unused15 is 15 b */
		/* Enable congestion control. */
		#define CMDQ_MODIFY_QP_ENABLE_CC UINT32_C(0x1)
		/* unused15 is 15 b */
		uint32_t sq_size;
		/* Max send WQE. */
		uint32_t rq_size;
		/* Max recv WQE. */
		uint16_t sq_sge;
		/* Max send SGEs per SWQE. */
		uint16_t rq_sge;
		/* Max recv SGEs per RWQE. */
		uint32_t max_inline_data;
		/* Max inline data length (upto 120 bytes). */
		uint32_t dest_qp_id;
		/* Destination QP id. */
		uint32_t unused_3;
		uint16_t src_mac[3];
		/* Source MAC. (Unused. Comes from Source GID index) */
		uint16_t vlan_pcp_vlan_dei_vlan_id;
		/* VLAN PCP field - Priority Code Point. */
		/* VLAN id. (Unused. Comes from Source GID index) */
		#define CMDQ_MODIFY_QP_VLAN_ID_MASK UINT32_C(0xfff)
		#define CMDQ_MODIFY_QP_VLAN_ID_SFT 0
		/* VLAN DEI field - Drop Eligibility Indicator. */
		#define CMDQ_MODIFY_QP_VLAN_DEI UINT32_C(0x1000)
		/* VLAN PCP field - Priority Code Point. */
		#define CMDQ_MODIFY_QP_VLAN_PCP_MASK UINT32_C(0xe000)
		#define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13
		} __attribute__((packed));

		/* Query QP command (24 bytes) */

		struct cmdq_query_qp {
		uint8_t opcode;
		/* Command opcode. */
		/* Query QP command retrieves info about the specified QP. */
		#define CMDQ_QUERY_QP_OPCODE_QUERY_QP UINT32_C(0x4)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t qp_cid;
		/* QP context id */
		uint32_t unused_0;
		} __attribute__((packed));

		/* Create SRQ command (48 bytes) */

		struct cmdq_create_srq {
		uint8_t opcode;
		/* Command opcode. */
		/* Create SRQ command allocates a SRQ with the specified parameters. */
		#define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ UINT32_C(0x5)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint64_t srq_handle;
		/* SRQ handle. */
		uint16_t pg_size_lvl;
		/* unused11 is 11 b */
		/* SRQ PBL indirect levels. */
		#define CMDQ_CREATE_SRQ_LVL_MASK UINT32_C(0x3)
		#define CMDQ_CREATE_SRQ_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_CREATE_SRQ_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_CREATE_SRQ_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_CREATE_SRQ_LVL_LVL_2 UINT32_C(0x2)
		/* page size. */
		#define CMDQ_CREATE_SRQ_PG_SIZE_MASK UINT32_C(0x1c)
		#define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2
		/* 4KB. */
		#define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
		/* 8KB. */
		#define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
		/* 64KB. */
		#define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
		/* 2MB. */
		#define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
		/* 8MB. */
		#define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
		/* 1GB. */
		#define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
		/* unused11 is 11 b */
		uint16_t eventq_id;
		/* unused4 is 4 b */
		/* eventq_id is 12 b */
		#define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK UINT32_C(0xfff)
		#define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0
		/* unused4 is 4 b */
		uint16_t srq_size;
		/* Max number of SRQ wqes. */
		uint16_t srq_fwo;
		/* Offsetof first WQE in the first page of SRQ, in 128 byte units */
		uint32_t dpi;
		/* Doorbell page index. */
		uint32_t pd_id;
		/* Protection domain id. */
		uint64_t pbl;
		/* RQ PBL physical address. */
		} __attribute__((packed));

		/* Destroy SRQ command (24 bytes) */

		struct cmdq_destroy_srq {
		uint8_t opcode;
		/* Command opcode. */
		/* Destroy SRQ command deletes and flushes the specified SRQ. */
		#define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ UINT32_C(0x6)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t srq_cid;
		/* SRQ context id */
		uint32_t unused_0;
		} __attribute__((packed));

		/* Query SRQ command (24 bytes) */

		struct cmdq_query_srq {
		uint8_t opcode;
		/* Command opcode. */
		/* Query SRP command retrieves info about the specified SRQ. */
		#define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ UINT32_C(0x8)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t srq_cid;
		/* SRQ context id */
		uint32_t unused_0;
		} __attribute__((packed));

		/* Create CQ command (48 bytes) */

		struct cmdq_create_cq {
		uint8_t opcode;
		/* Command opcode. */
		/* Create CQ command allocates a CQ with the specified parameters. */
		#define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ UINT32_C(0x9)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint64_t cq_handle;
		/* CQ handle. */
		uint32_t pg_size_lvl;
		/* unused27 is 27 b */
		/* PBL indirect levels. */
		#define CMDQ_CREATE_CQ_LVL_MASK UINT32_C(0x3)
		#define CMDQ_CREATE_CQ_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_CREATE_CQ_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_CREATE_CQ_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_CREATE_CQ_LVL_LVL_2 UINT32_C(0x2)
		/* page size. */
		#define CMDQ_CREATE_CQ_PG_SIZE_MASK UINT32_C(0x1c)
		#define CMDQ_CREATE_CQ_PG_SIZE_SFT 2
		/* 4KB. */
		#define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
		/* 8KB. */
		#define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
		/* 64KB. */
		#define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
		/* 2MB. */
		#define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
		/* 8MB. */
		#define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
		/* 1GB. */
		#define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
		/* unused27 is 27 b */
		uint32_t cq_fco_cnq_id;
		/* Offset of first CQE in the first Page, in 32 byte units */
		/* cnq_id is 12 b */
		#define CMDQ_CREATE_CQ_CNQ_ID_MASK UINT32_C(0xfff)
		#define CMDQ_CREATE_CQ_CNQ_ID_SFT 0
		/* Offset of first CQE in the first Page, in 32 byte units */
		#define CMDQ_CREATE_CQ_CQ_FCO_MASK UINT32_C(0xfffff000)
		#define CMDQ_CREATE_CQ_CQ_FCO_SFT 12
		uint32_t dpi;
		/* Doorbell page index. */
		uint32_t cq_size;
		/* Max number of CQ wqes. */
		uint64_t pbl;
		/* CQ PBL physical address. */
		} __attribute__((packed));

		/* Destroy CQ command (24 bytes) */

		struct cmdq_destroy_cq {
		uint8_t opcode;
		/* Command opcode. */
		/* Destroy CQ command deletes and flushes the specified CQ. */
		#define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ UINT32_C(0xa)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t cq_cid;
		/* CQ context id */
		uint32_t unused_0;
		} __attribute__((packed));

		/* Resize CQ command (40 bytes) */

		struct cmdq_resize_cq {
		uint8_t opcode;
		/* Command opcode. */
		/* Resize CQ command resizes the specified CQ. */
		#define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ UINT32_C(0xc)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t cq_cid;
		/* CQ context id */
		uint32_t new_cq_size_pg_size_lvl;
		/* PBL indirect levels. */
		#define CMDQ_RESIZE_CQ_LVL_MASK UINT32_C(0x3)
		#define CMDQ_RESIZE_CQ_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_RESIZE_CQ_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_RESIZE_CQ_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_RESIZE_CQ_LVL_LVL_2 UINT32_C(0x2)
		/* page size. */
		#define CMDQ_RESIZE_CQ_PG_SIZE_MASK UINT32_C(0x1c)
		#define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2
		/* 4KB. */
		#define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
		/* 8KB. */
		#define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
		/* 64KB. */
		#define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
		/* 2MB. */
		#define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
		/* 8MB. */
		#define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
		/* 1GB. */
		#define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
		/* New max number of CQ wqes. */
		#define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK UINT32_C(0x1fffe0)
		#define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5
		uint64_t new_pbl;
		/* CQ PBL physical address. */
		uint32_t new_cq_fco;
		/* Offset of first CQE in the first Page, in 32 byte units */
		uint32_t unused_2;
		} __attribute__((packed));

		/* Allocate MRW command (32 bytes) */

		struct cmdq_allocate_mrw {
		uint8_t opcode;
		/* Command opcode. */
		/*
		* Allocate MRW command allocates a MR/MW with the specified
		* parameters and returns the region's L_KEY/R_KEY
		*/
		#define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW UINT32_C(0xd)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint64_t mrw_handle;
		/* MRW handle. */
		uint8_t mrw_flags;
		/* unused4 is 4 b */
		/* Allocate MRW flags. */
		#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK UINT32_C(0xf)
		#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0
		/* Allocate Memory Region */
		#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR UINT32_C(0x0)
		/* Allocate Physical Memory Region */
		#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR UINT32_C(0x1)
		/* Allocate Memory Window (type 1) */
		#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2)
		/* Allocate Memory Window (type 2A) */
		#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3)
		/* Allocate Memory Window (type 2B) */
		#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4)
		/* unused4 is 4 b */
		uint8_t access;
		/* Access flags. */
		#define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_MASK UINT32_C(0x1f)
		#define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_SFT 0
		/* Consumer owns the key */
		#define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY UINT32_C(0x20)
		uint16_t unused_1;
		/* unused16 is 16 b */
		uint32_t pd_id;
		/* Protection domain id. */
		} __attribute__((packed));

		/* De-allocate key command (24 bytes) */

		struct cmdq_deallocate_key {
		uint8_t opcode;
		/* Command opcode. */
		/*
		* De-allocate key command frees a MR/MW entry associated with
		* the specified key.
		*/
		#define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY UINT32_C(0xe)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint8_t mrw_flags;
		/* unused4 is 4 b */
		/* Deallocate MRW flags. */
		#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK UINT32_C(0xf)
		#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0
		/* Deallocate Memory Region */
		#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR UINT32_C(0x0)
		/* Deallocate Physical Memory Region */
		#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR UINT32_C(0x1)
		/* Deallocate Memory Window (type 1) */
		#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2)
		/* Deallocate Memory Window (type 2A) */
		#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3)
		/* Deallocate Memory Window (type 2B) */
		#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4)
		/* unused4 is 4 b */
		uint8_t unused_1[3];
		/* unused24 is 24 b */
		uint32_t key;
		/* key is 32 b */
		} __attribute__((packed));

		/* Register MR command (48 bytes) */

		struct cmdq_register_mr {
		uint8_t opcode;
		/* Command opcode. */
		/* Register MR command registers memory to the specified MR. */
		#define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR UINT32_C(0xf)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint8_t log2_pg_size_lvl;
		/* unused1 is 1 b */
		/* PBL indirect levels. */
		#define CMDQ_REGISTER_MR_LVL_MASK UINT32_C(0x3)
		#define CMDQ_REGISTER_MR_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_REGISTER_MR_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_REGISTER_MR_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_REGISTER_MR_LVL_LVL_2 UINT32_C(0x2)
		/*
		* Log base 2 of page size; 12 is the minimum for 4KB. HW supported
		* values are enumerated below.
		*/
		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK UINT32_C(0x7c)
		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2
		/* 4KB. */
		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (UINT32_C(0xc) << 2)
		/* 8KB. */
		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (UINT32_C(0xd) << 2)
		/* 64KB. */
		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (UINT32_C(0x10) << 2)
		/* 256KB. */
		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (UINT32_C(0x12) << 2)
		/* 1MB. */
		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (UINT32_C(0x14) << 2)
		/* 2MB. */
		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (UINT32_C(0x15) << 2)
		/* 4MB. */
		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (UINT32_C(0x16) << 2)
		/* 1GB. */
		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (UINT32_C(0x1e) << 2)
		/* unused1 is 1 b */
		uint8_t access;
		/* Access flags. */
		/* Local write access. */
		#define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE UINT32_C(0x1)
		/* Remote read access. */
		#define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ UINT32_C(0x2)
		/* Remote write access. */
		#define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE UINT32_C(0x4)
		/* Remote atomic access. */
		#define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC UINT32_C(0x8)
		/* Bind access allowed. */
		#define CMDQ_REGISTER_MR_ACCESS_MW_BIND UINT32_C(0x10)
		/* Indicate Zero Based Virtual Address (ZBVA). */
		#define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED UINT32_C(0x20)
		uint16_t log2_pbl_pg_size;
		/* unused11 is 11 b */
		/*
		* Log base 2 of PBL page size; 12 is the minimum for 4KB. HW supported
		* values are enumerated below
		*/
		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK UINT32_C(0x1f)
		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0
		/* 4KB. */
		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K UINT32_C(0xc)
		/* 8KB. */
		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K UINT32_C(0xd)
		/* 64KB. */
		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K UINT32_C(0x10)
		/* 256KB. */
		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K UINT32_C(0x12)
		/* 1MB. */
		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M UINT32_C(0x14)
		/* 2MB. */
		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M UINT32_C(0x15)
		/* 4MB. */
		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M UINT32_C(0x16)
		/* 1GB. */
		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G UINT32_C(0x1e)
		/* unused11 is 11 b */
		uint32_t key;
		/* KEY of the MR. */
		uint64_t pbl;
		/* Page table of the MR memory. */
		uint64_t va;
		/* Virtual address of the MR. */
		uint64_t mr_size;
		/* Size of the MR. */
		} __attribute__((packed));

		/* Deregister MR command (24 bytes) */

		struct cmdq_deregister_mr {
		uint8_t opcode;
		/* Command opcode. */
		/* Deregister MR command de-registers memory from the specified MR. */
		#define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR UINT32_C(0x10)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t lkey;
		/* L_KEY of the MR. */
		uint32_t unused_0;
		} __attribute__((packed));

		/* Add GID command (48 bytes) */

		struct cmdq_add_gid {
		uint8_t opcode;
		/* Command opcode. */
		/* Add GID command adds a GID to the local address table. */
		#define CMDQ_ADD_GID_OPCODE_ADD_GID UINT32_C(0x11)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t gid[4];
		/* GID */
		uint16_t src_mac[3];
		/* Source MAC. */
		uint16_t vlan;
		/* flags. */
		/* Source VLAN id. */
		#define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK UINT32_C(0xfff)
		#define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0
		/* This set of bits select the TPID of the VLAN Tag. */
		#define CMDQ_ADD_GID_VLAN_TPID_MASK UINT32_C(0x7000)
		#define CMDQ_ADD_GID_VLAN_TPID_SFT 12
		/* TPID = 0x88A8. */
		#define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12)
		/* TPID = 0x8100. */
		#define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12)
		/* TPID = 0x9100. */
		#define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12)
		/* TPID = 0x9200. */
		#define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12)
		/* TPID = 0x9300. */
		#define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12)
		/* TPID = Configurable 1. */
		#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12)
		/* TPID = Configurable 2. */
		#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12)
		/* TPID = Configurable 3. */
		#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12)
		#define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3
		/*
		* Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE
		* header.
		*/
		#define CMDQ_ADD_GID_VLAN_VLAN_EN UINT32_C(0x8000)
		uint16_t ipid;
		/* Identifier field in the IP header. */
		uint16_t stats_ctx;
		/* Stats context ID to use with this SGID */
		/* stats_ctx_id is 15 b */
		#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff)
		#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0
		/*
		* Setting this bit to 1 enables use of own stats context ID instead of
		* per-function
		*/
		#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000)
		uint32_t unused_0;
		} __attribute__((packed));

		/* Delete GID command (24 bytes) */

		struct cmdq_delete_gid {
		uint8_t opcode;
		/* Command opcode. */
		/* Delete GID command deletes a GID from the local address table. */
		#define CMDQ_DELETE_GID_OPCODE_DELETE_GID UINT32_C(0x12)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint16_t gid_index;
		/* GID index */
		uint16_t unused_0;
		/* unused16 is 16 b */
		uint32_t unused_1;
		} __attribute__((packed));

		/* Modify GID command (48 bytes) */

		struct cmdq_modify_gid {
		uint8_t opcode;
		/* Command opcode. */
		/* Modify GID command modifies a GID in the local address table. */
		#define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID UINT32_C(0x17)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t gid[4];
		/* GID */
		uint16_t src_mac[3];
		/* Source MAC. */
		uint16_t vlan;
		/* flags. */
		/* Source VLAN id. */
		#define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK UINT32_C(0xfff)
		#define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0
		/* This set of bits select the TPID of the VLAN Tag. */
		#define CMDQ_MODIFY_GID_VLAN_TPID_MASK UINT32_C(0x7000)
		#define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12
		/* TPID = 0x88A8. */
		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12)
		/* TPID = 0x8100. */
		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12)
		/* TPID = 0x9100. */
		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12)
		/* TPID = 0x9200. */
		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12)
		/* TPID = 0x9300. */
		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12)
		/* TPID = Configurable 1. */
		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12)
		/* TPID = Configurable 2. */
		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12)
		/* TPID = Configurable 3. */
		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12)
		#define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3
		/*
		* Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE
		* header.
		*/
		#define CMDQ_MODIFY_GID_VLAN_VLAN_EN UINT32_C(0x8000)
		uint16_t ipid;
		/* Identifier field in the IP header. */
		uint16_t gid_index;
		/* GID index */
		uint16_t stats_ctx;
		/* Stats context ID to use with this SGID */
		/* stats_ctx_id is 15 b */
		#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff)
		#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0
		/*
		* Setting this bit to 1 enables use of own stats context ID instead of
		* per-function
		*/
		#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000)
		uint16_t unused_0;
		} __attribute__((packed));

		/* Query GID command (24 bytes) */

		struct cmdq_query_gid {
		uint8_t opcode;
		/* Command opcode. */
		/* Query GID command queries a GID in the local address table. */
		#define CMDQ_QUERY_GID_OPCODE_QUERY_GID UINT32_C(0x18)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint16_t gid_index;
		/* GID index */
		uint16_t unused_0;
		/* unused16 is 16 b */
		uint32_t unused_1;
		} __attribute__((packed));

		/* Create QP1 command (80 bytes) */

		struct cmdq_create_qp1 {
		uint8_t opcode;
		/* Command opcode. */
		/* Create QP1 command allocates a QP1 only. */
		#define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 UINT32_C(0x13)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint64_t qp_handle;
		/* QP1 handle. */
		uint32_t qp_flags;
		/* Create QP1 flags. */
		/* SRQ is used. */
		#define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED UINT32_C(0x1)
		/* post CQE for all SQ WQEs. */
		#define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2)
		/* This QP can use reserved L_Key */
		#define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4)
		uint8_t type;
		/* Supported QP1 types. */
		/* General Services Interface on QP 1. */
		#define CMDQ_CREATE_QP1_TYPE_GSI UINT32_C(0x1)
		uint8_t sq_pg_size_sq_lvl;
		/* SQ page size. */
		/* SQ PBL indirect levels. */
		#define CMDQ_CREATE_QP1_SQ_LVL_MASK UINT32_C(0xf)
		#define CMDQ_CREATE_QP1_SQ_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 UINT32_C(0x2)
		/* SQ page size. */
		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK UINT32_C(0xf0)
		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4
		/* 4KB. */
		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
		/* 8KB. */
		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
		/* 64KB. */
		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
		/* 2MB. */
		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
		/* 8MB. */
		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
		/* 1GB. */
		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
		uint8_t rq_pg_size_rq_lvl;
		/* RQ page size. */
		/* RQ PBL indirect levels. */
		#define CMDQ_CREATE_QP1_RQ_LVL_MASK UINT32_C(0xf)
		#define CMDQ_CREATE_QP1_RQ_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 UINT32_C(0x2)
		/* RQ page size. */
		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK UINT32_C(0xf0)
		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4
		/* 4KB. */
		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
		/* 8KB. */
		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
		/* 64KB. */
		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
		/* 2MB. */
		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
		/* 8MB. */
		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
		/* 1GB. */
		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
		uint8_t unused_0;
		uint32_t dpi;
		/* Doorbell page index. */
		uint32_t sq_size;
		/* Max number of SQ wqes. */
		uint32_t rq_size;
		/* Max number of RQ wqes. */
		uint16_t sq_fwo_sq_sge;
		/* Offset of First WQE in the first SQ page, in 128 byte units */
		/* Max send SGEs per SWQE. */
		#define CMDQ_CREATE_QP1_SQ_SGE_MASK UINT32_C(0xf)
		#define CMDQ_CREATE_QP1_SQ_SGE_SFT 0
		/* Offset of First WQE in the first SQ page, in 128 byte units */
		#define CMDQ_CREATE_QP1_SQ_FWO_MASK UINT32_C(0xfff0)
		#define CMDQ_CREATE_QP1_SQ_FWO_SFT 4
		uint16_t rq_fwo_rq_sge;
		/* Offset of First WQE in the first RQ page, in 128 byte units */
		/* Max recv SGEs per RWQE (NOT SUPPORTED BY HARDWARE). */
		#define CMDQ_CREATE_QP1_RQ_SGE_MASK UINT32_C(0xf)
		#define CMDQ_CREATE_QP1_RQ_SGE_SFT 0
		/* Offset of First WQE in the first RQ page, in 128 byte units */
		#define CMDQ_CREATE_QP1_RQ_FWO_MASK UINT32_C(0xfff0)
		#define CMDQ_CREATE_QP1_RQ_FWO_SFT 4
		uint32_t scq_cid;
		/* Send CQ context id. */
		uint32_t rcq_cid;
		/* Receive CQ context id. */
		uint32_t srq_cid;
		/* SRQ CQ context id. */
		uint32_t pd_id;
		/* Protection domain id. */
		uint64_t sq_pbl;
		/* SQ PBL physical address. */
		uint64_t rq_pbl;
		/* RQ PBL physical address. */
		} __attribute__((packed));

		/* Destroy QP1 command (24 bytes) */

		struct cmdq_destroy_qp1 {
		uint8_t opcode;
		/* Command opcode. */
		/* Destroy QP1 command deletes and flushes the specified QP1. */
		#define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 UINT32_C(0x14)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t qp1_cid;
		/* QP1 context id */
		uint32_t unused_0;
		} __attribute__((packed));

		/* Create AH command (64 bytes) */

		struct cmdq_create_ah {
		uint8_t opcode;
		/* Command opcode. */
		/* Create AH command allocates an AH with the specified parameters. */
		#define CMDQ_CREATE_AH_OPCODE_CREATE_AH UINT32_C(0x15)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint64_t ah_handle;
		/* AH handle. */
		uint32_t dgid[4];
		/* Destination GID. */
		uint8_t type;
		/* V1, V2IPv4 or V2IPv6. */
		/* V2IPv4. */
		#define CMDQ_CREATE_AH_TYPE_V1 UINT32_C(0x0)
		/* V2IPv4. */
		#define CMDQ_CREATE_AH_TYPE_V2IPV4 UINT32_C(0x2)
		/* V2IPv6. */
		#define CMDQ_CREATE_AH_TYPE_V2IPV6 UINT32_C(0x3)
		uint8_t hop_limit;
		/* IPv6 Hop limit. */
		uint16_t sgid_index;
		/* SGID index. */
		uint32_t dest_vlan_id_flow_label;
		/* Destination VLAN ID. */
		/* Flow label. */
		#define CMDQ_CREATE_AH_FLOW_LABEL_MASK UINT32_C(0xfffff)
		#define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0
		/* Destination VLAN ID. */
		#define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK UINT32_C(0xfff00000)
		#define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20
		uint32_t pd_id;
		/* Protection domain id. */
		uint32_t unused_0;
		uint16_t dest_mac[3];
		/* Destination MAC address. */
		uint8_t traffic_class;
		/* Traffic class. */
		uint8_t enable_cc;
		/* Enable congestion control. */
		#define CMDQ_CREATE_AH_ENABLE_CC UINT32_C(0x1)
		} __attribute__((packed));

		/* Destroy AH command (24 bytes) */

		struct cmdq_destroy_ah {
		uint8_t opcode;
		/* Command opcode. */
		/* Destroy AH command deletes the specified AH. */
		#define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH UINT32_C(0x16)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t ah_cid;
		/* AH context id */
		uint32_t unused_0;
		} __attribute__((packed));

		/* Initialize Firmware command (112 bytes) */

		struct cmdq_initialize_fw {
		uint8_t opcode;
		/* Command opcode. */
		/*
		* Initialize firmware command initializes the firmware with the
		* specified parameters.
		*/
		#define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW UINT32_C(0x80)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint8_t qpc_pg_size_qpc_lvl;
		/* QPC page size. */
		/* QPC PBL indirect levels. */
		#define CMDQ_INITIALIZE_FW_QPC_LVL_MASK UINT32_C(0xf)
		#define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 UINT32_C(0x2)
		/* QPC page size. */
		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK UINT32_C(0xf0)
		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4
		/* 4KB. */
		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
		/* 8KB. */
		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
		/* 64KB. */
		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
		/* 2MB. */
		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
		/* 8MB. */
		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
		/* 1GB. */
		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
		uint8_t mrw_pg_size_mrw_lvl;
		/* MRW page size. */
		/* MRW PBL indirect levels. */
		#define CMDQ_INITIALIZE_FW_MRW_LVL_MASK UINT32_C(0xf)
		#define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 UINT32_C(0x2)
		/* MRW page size. */
		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK UINT32_C(0xf0)
		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4
		/* 4KB. */
		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
		/* 8KB. */
		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
		/* 64KB. */
		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
		/* 2MB. */
		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
		/* 8MB. */
		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
		/* 1GB. */
		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
		uint8_t srq_pg_size_srq_lvl;
		/* SRQ page size. */
		/* SRQ PBL indirect levels. */
		#define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK UINT32_C(0xf)
		#define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 UINT32_C(0x2)
		/* SRQ page size. */
		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK UINT32_C(0xf0)
		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4
		/* 4KB. */
		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
		/* 8KB. */
		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
		/* 64KB. */
		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
		/* 2MB. */
		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
		/* 8MB. */
		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
		/* 1GB. */
		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
		uint8_t cq_pg_size_cq_lvl;
		/* CQ page size. */
		/* CQ PBL indirect levels. */
		#define CMDQ_INITIALIZE_FW_CQ_LVL_MASK UINT32_C(0xf)
		#define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 UINT32_C(0x2)
		/* CQ page size. */
		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK UINT32_C(0xf0)
		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4
		/* 4KB. */
		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
		/* 8KB. */
		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
		/* 64KB. */
		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
		/* 2MB. */
		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
		/* 8MB. */
		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
		/* 1GB. */
		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
		uint8_t tqm_pg_size_tqm_lvl;
		/* TQM page size. */
		/* TQM PBL indirect levels. */
		#define CMDQ_INITIALIZE_FW_TQM_LVL_MASK UINT32_C(0xf)
		#define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 UINT32_C(0x2)
		/* TQM page size. */
		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK UINT32_C(0xf0)
		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4
		/* 4KB. */
		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
		/* 8KB. */
		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
		/* 64KB. */
		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
		/* 2MB. */
		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
		/* 8MB. */
		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
		/* 1GB. */
		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
		uint8_t tim_pg_size_tim_lvl;
		/* TIM page size. */
		/* TIM PBL indirect levels. */
		#define CMDQ_INITIALIZE_FW_TIM_LVL_MASK UINT32_C(0xf)
		#define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0
		/* PBL pointer is physical start address. */
		#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 UINT32_C(0x0)
		/* PBL pointer points to PTE table. */
		#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 UINT32_C(0x1)
		/*
		* PBL pointer points to PDE table with each entry pointing to
		* PTE tables.
		*/
		#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 UINT32_C(0x2)
		/* TIM page size. */
		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK UINT32_C(0xf0)
		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4
		/* 4KB. */
		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
		/* 8KB. */
		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
		/* 64KB. */
		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
		/* 2MB. */
		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
		/* 8MB. */
		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
		/* 1GB. */
		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
		uint16_t reserved16;
		uint64_t qpc_page_dir;
		/* Kernel notification queue page directory. */
		uint64_t mrw_page_dir;
		/* MRW page directory. */
		uint64_t srq_page_dir;
		/* SRQ page directory. */
		uint64_t cq_page_dir;
		/* CQ page directory. */
		uint64_t tqm_page_dir;
		/* TQM page directory. */
		uint64_t tim_page_dir;
		/* TIM page directory. */
		uint32_t number_of_qp;
		/* Number of QPs. */
		uint32_t number_of_mrw;
		/* Number of MRWs. */
		uint32_t number_of_srq;
		/* Number of SRQs. */
		uint32_t number_of_cq;
		/* Number of CQs. */
		uint32_t max_qp_per_vf;
		/* Number of QPs per VF. */
		uint32_t max_mrw_per_vf;
		/* Number of MRWs per VF. */
		uint32_t max_srq_per_vf;
		/* Number of SRQs per VF. */
		uint32_t max_cq_per_vf;
		/* Number of CQs per VF. */
		uint32_t max_gid_per_vf;
		/* Number of GIDs per VF. */
		uint32_t stat_ctx_id;
		/* Statistics context index for this function. */
		} __attribute__((packed));

		/* De-initialize Firmware command (16 bytes) */

		struct cmdq_deinitialize_fw {
		uint8_t opcode;
		/* Command opcode. */
		/* De-initialize firmware command deinitializes the firmware. */
		#define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW UINT32_C(0x81)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		} __attribute__((packed));

		/* Stop function command (16 bytes) */

		struct cmdq_stop_func {
		uint8_t opcode;
		/* Command opcode. */
		/* Stop the function */
		#define CMDQ_STOP_FUNC_OPCODE_STOP_FUNC UINT32_C(0x82)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		} __attribute__((packed));

		/* Query function command (16 bytes) */

		struct cmdq_query_func {
		uint8_t opcode;
		/* Command opcode. */
		/* Query the HW capabilities for the function. */
		#define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC UINT32_C(0x83)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		} __attribute__((packed));

		/* Set function resources command (56 bytes) */

		struct cmdq_set_func_resources {
		uint8_t opcode;
		/* Command opcode. */
		/*
		* Set the following resources for the function: - Max QP, CQ,
		* MR+MW, SRQ per PF - Max QP, CQ, MR+MW, SRQ per VF
		*/
		#define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t number_of_qp;
		/*
		* Number of QPs. It is the responsibility of the host to first extend
		* the existing PBL with new addresses to pages to handle the
		* adjustment. Must be greater or equal to current.
		*/
		uint32_t number_of_mrw;
		/*
		* Number of MRWs. It is the responsibility of the host to first extend
		* the existing PBL with new addresses to pages to handle the
		* adjustment. Must be greater or equal to current.
		*/
		uint32_t number_of_srq;
		/*
		* Number of SRQs. It is the responsibility of the host to first extend
		* the existing PBL with new addresses to pages to handle the
		* adjustment. Must be greater or equal to current.
		*/
		uint32_t number_of_cq;
		/*
		* Number of CQs. It is the responsibility of the host to first extend
		* the existing PBL with new addresses to pages to handle the
		* adjustment. Must be greater or equal to current.
		*/
		uint32_t max_qp_per_vf;
		/* Number of QPs per VF. */
		uint32_t max_mrw_per_vf;
		/* Number of MRWs per VF. */
		uint32_t max_srq_per_vf;
		/* Number of SRQs per VF. */
		uint32_t max_cq_per_vf;
		/* Number of CQs per VF. */
		uint32_t max_gid_per_vf;
		/* Number of GIDs per VF. */
		uint32_t stat_ctx_id;
		/* Statistics context index for this function. */
		} __attribute__((packed));

		/* Read hardware resource context command (24 bytes) */

		struct cmdq_read_context {
		uint8_t opcode;
		/* Command opcode. */
		/*
		* Read the current state of any internal resource context. Can
		* only be issued from a PF.
		*/
		#define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT UINT32_C(0x85)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t type_xid;
		/* Context type */
		/* Context ID */
		#define CMDQ_READ_CONTEXT_XID_MASK UINT32_C(0xffffff)
		#define CMDQ_READ_CONTEXT_XID_SFT 0
		/* Context type */
		#define CMDQ_READ_CONTEXT_TYPE_MASK UINT32_C(0xff000000)
		#define CMDQ_READ_CONTEXT_TYPE_SFT 24
		/*
		* Read QPC. The context (448 bytes) goes to resp_addr (as is,
		* without a header), and resp_size should be set to 28 (448/16)
		*/
		#define CMDQ_READ_CONTEXT_TYPE_QPC (UINT32_C(0x0) << 24)
		/*
		* Read CQ. The context (64 bytes) goes to resp_addr (as is,
		* without a header), and resp_size should be set to 4 (64/16)
		*/
		#define CMDQ_READ_CONTEXT_TYPE_CQ (UINT32_C(0x1) << 24)
		/*
		* Read MRW. The context (128 bytes) goes to resp_addr (as is,
		* without a header), and resp_size should be set to 8 (128/16)
		*/
		#define CMDQ_READ_CONTEXT_TYPE_MRW (UINT32_C(0x2) << 24)
		/*
		* Read SRQ. The context (64 bytes) goes to resp_addr (as is,
		* without a header), and resp_size should be set to 4 (64/16)
		*/
		#define CMDQ_READ_CONTEXT_TYPE_SRQ (UINT32_C(0x3) << 24)
		uint32_t unused_0;
		} __attribute__((packed));

		/* Send a request from VF to pass a command to the PF. VF HSI is suspended until the PF returns the response (32 bytes) */

		struct cmdq_vf_backchannel_request {
		uint8_t opcode;
		/* Command opcode. */
		/*
		* Send a request from VF to pass a command to the PF. VF HSI is
		* suspended until the PF returns the response
		*/
		#define CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint64_t command_addr;
		/* Address of command request structure in VF space */
		uint16_t command_length;
		/*
		* Command request length (up to 4K). An optional address of the
		* extended response buffer should be provided in the request
		*/
		uint16_t unused_0[3];
		} __attribute__((packed));

		/* Read VF memory (primarily to get the backchannel request blob). Can only be issued from a PF. (32 bytes) */

		struct cmdq_read_vf_memory {
		uint8_t opcode;
		/* Command opcode. */
		/*
		* Read VF memory (primarily to get the backchannel request
		* blob). Can only be issued from a PF.
		*/
		#define CMDQ_READ_VF_MEMORY_OPCODE_READ_VF_MEMORY UINT32_C(0x87)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint64_t addr;
		/* Address of memory in VF space to read */
		uint16_t vf_id;
		/* VF id, as provided in 0xC0 VF request notification */
		uint16_t length;
		/* Length to read, up to 4K */
		uint32_t unused_0;
		} __attribute__((packed));

		/* Write VF memory (primarily to put the backchannel response blob), and reenable VF HSI (post a CAG completion to it). Can only be issued from a PF. (40 bytes) */

		struct cmdq_complete_vf_request {
		uint8_t opcode;
		/* Command opcode. */
		/*
		* Write VF memory (primarily to put the backchannel response
		* blob), and reenable VF HSI (post a CAG completion to it). Can
		* only be issued from a PF.
		*/
		#define CMDQ_COMPLETE_VF_REQUEST_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint64_t addr;
		/*
		* Optional address of extended response in VF space to write. Length is
		* in resp_size in 16 byte units.
		*/
		uint32_t vf_misc;
		/* Completion misc field to VF CREQ */
		uint16_t vf_id;
		/* VF id, as provided in 0xC0 VF request notification */
		uint16_t vf_cookie;
		/* Completion cookie for the VF command, goes to VF CREQ */
		uint8_t vf_status;
		/* Completion status for the VF command, goes to VF CREQ */
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* Map TC to COS. Can only be issued from a PF (24 bytes) */

		struct cmdq_map_tc_to_cos {
		uint8_t opcode;
		/* Command opcode. */
		/* Map TC to COS. Can only be issued from a PF. */
		#define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint16_t cos0;
		/* 1st COS index mapped to RoCE */
		/* Don't change this COS. */
		#define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE UINT32_C(0xffff)
		uint16_t cos1;
		/* 2nd COS index mapped to RoCE */
		/* Disable this COS. */
		#define CMDQ_MAP_TC_TO_COS_COS1_DISABLE UINT32_C(0x8000)
		/* Don't change this COS. */
		#define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE UINT32_C(0xffff)
		uint32_t unused_0;
		} __attribute__((packed));

		/* Query version command (16 bytes) */

		struct cmdq_query_version {
		uint8_t opcode;
		/* Command opcode. */
		/* Query version. */
		#define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION UINT32_C(0x8b)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		} __attribute__((packed));

		/* Modify congestion control command (56 bytes) */

		struct cmdq_modify_roce_cc {
		uint8_t opcode;
		/* Command opcode. */
		/* Modify congestion control. Can only be issued from a PF. */
		#define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		uint32_t modify_mask;
		/* Modify mask signifies the field that is requesting the change. */
		/* Enable change. */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC UINT32_C(0x1)
		/* Running average weight change. */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G UINT32_C(0x2)
		/* Number of phases in Fast Recovery. */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE UINT32_C(0x4)
		/* The starting value of rate change. */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR UINT32_C(0x8)
		/* The starting value of target rate change. */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR UINT32_C(0x10)
		/* IP TOS ECN change */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN UINT32_C(0x20)
		/* IP TOS DSCP change */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP UINT32_C(0x40)
		/* Alternate IP TOS ECN change */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP UINT32_C(0x80)
		/* Alternate IP TOS DSCP change */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP UINT32_C(0x100)
		/* Round trip time in units of usecs */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT UINT32_C(0x200)
		/* 0 for DCTCP , 1 for TCP */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE UINT32_C(0x400)
		/* The value used as CP when cc_mode is 1(TCP) */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP UINT32_C(0x800)
		/* Specifies the RoCE Tx Queue ( o to 3) to use for sending CNP packets */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE UINT32_C(0x1000)
		/* Inactivity time after which QP CC parameters are initialized */
		#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP UINT32_C(0x2000)
		uint8_t enable_cc;
		/* rsvd1 is 7 b */
		/* Enable. */
		#define CMDQ_MODIFY_ROCE_CC_ENABLE_CC UINT32_C(0x1)
		/* rsvd1 is 7 b */
		#define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK UINT32_C(0xfe)
		#define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1
		uint8_t g;
		/* rsvd2 is 5 b */
		/* Congestion Probability averaging factor. */
		#define CMDQ_MODIFY_ROCE_CC_G_MASK UINT32_C(0x7)
		#define CMDQ_MODIFY_ROCE_CC_G_SFT 0
		/* rsvd2 is 5 b */
		#define CMDQ_MODIFY_ROCE_CC_RSVD2_MASK UINT32_C(0xf8)
		#define CMDQ_MODIFY_ROCE_CC_RSVD2_SFT 3
		uint8_t num_phases_per_state;
		/* Number of phases in Fast Recovery. */
		uint8_t rsvd9;
		/* rsvd9 is 8 b */
		uint16_t init_cr;
		/* The starting value of rate. */
		uint16_t init_tr;
		/* The starting value of target rate. */
		uint8_t tos_dscp_tos_ecn;
		/* IP TOS DSCP. */
		/* IP TOS ECN. Valid values are 1 or 2 when ECN is enabled. */
		#define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK UINT32_C(0x3)
		#define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0
		/* IP TOS DSCP. */
		#define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK UINT32_C(0xfc)
		#define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2
		uint8_t alt_vlan_pcp;
		/* rsvd3 is 5 b */
		/* Alternate vlan pcp value for CNP packets. */
		#define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK UINT32_C(0x7)
		#define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0
		/* rsvd3 is 5 b */
		#define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK UINT32_C(0xf8)
		#define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3
		uint16_t alt_tos_dscp;
		/* rsvd4 is 10 b */
		/* Alternate IP TOS DSCP. */
		#define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
		#define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0
		/* rsvd4 is 10 b */
		#define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK UINT32_C(0xffc0)
		#define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6
		uint16_t rtt;
		/* rsvd5 is 2 b */
		/* Round trip time in units of usecs */
		#define CMDQ_MODIFY_ROCE_CC_RTT_MASK UINT32_C(0x3fff)
		#define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0
		/* rsvd5 is 2 b */
		#define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK UINT32_C(0xc000)
		#define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14
		uint16_t tcp_cp;
		/* rsvd6 is 6 b */
		/* The value used as CP when cc_mode is 1(TCP) */
		#define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK UINT32_C(0x3ff)
		#define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0
		/* rsvd6 is 6 b */
		#define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK UINT32_C(0xfc00)
		#define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10
		uint8_t cc_mode;
		/* rsvd7 is 7 b */
		/* 0 for DCTCP , 1 for TCP */
		#define CMDQ_MODIFY_ROCE_CC_CC_MODE UINT32_C(0x1)
		/* rsvd7 is 7 b */
		#define CMDQ_MODIFY_ROCE_CC_RSVD7_MASK UINT32_C(0xfe)
		#define CMDQ_MODIFY_ROCE_CC_RSVD7_SFT 1
		uint8_t tx_queue;
		/* rsvd8 is 6 b */
		/* Specifies the RoCE Tx Queue ( o to 3) to use for sending CNP packets */
		#define CMDQ_MODIFY_ROCE_CC_TX_QUEUE_MASK UINT32_C(0x3)
		#define CMDQ_MODIFY_ROCE_CC_TX_QUEUE_SFT 0
		/* rsvd8 is 6 b */
		#define CMDQ_MODIFY_ROCE_CC_RSVD8_MASK UINT32_C(0xfc)
		#define CMDQ_MODIFY_ROCE_CC_RSVD8_SFT 2
		uint16_t inactivity_th;
		/* Inactivity time after which QP CC parameters are initialized */
		uint64_t reserved64;
		uint64_t reserved64_1;
		} __attribute__((packed));

		/* Query congestion control command (16 bytes) */

		struct cmdq_query_roce_cc {
		uint8_t opcode;
		/* Command opcode. */
		/* Query congestion control. */
		#define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
		uint8_t cmd_size;
		/* Size of the command in 16-byte units. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t resp_addr;
		/* Host address of the response. */
		} __attribute__((packed));

		/* Command-Response Event Queue (CREQ) Structures */
		/* Description: This is an async event indicating error happened on a QP. */
		/* Base CREQ Record (16 bytes) */

		struct creq_base {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_BASE_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_BASE_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_BASE_TYPE_QP_EVENT UINT32_C(0x38)
		/* Function Async Notification */
		#define CREQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
		#define CREQ_BASE_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_BASE_RESERVED2_SFT 6
		uint8_t reserved56[7];
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_BASE_V UINT32_C(0x1)
		#define CREQ_BASE_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_BASE_RESERVED7_SFT 1
		uint8_t event;
		/* This is the modifier on to the type field. */
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* RoCE Function Async Event Notification (16 bytes) */

		struct creq_func_event {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_FUNC_EVENT_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_FUNC_EVENT_TYPE_SFT 0
		/* Function Async Notification */
		#define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT UINT32_C(0x3a)
		#define CREQ_FUNC_EVENT_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_FUNC_EVENT_RESERVED2_SFT 6
		uint8_t reserved56[7];
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_FUNC_EVENT_V UINT32_C(0x1)
		#define CREQ_FUNC_EVENT_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_FUNC_EVENT_RESERVED7_SFT 1
		uint8_t event;
		/*
		* This value defines what type of async event has occurred on the
		* function.
		*/
		/*
		* Invalid PBL or PCIE UR response occurred in SQ WQE or IRRQ
		* read access.
		*/
		#define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR UINT32_C(0x1)
		/* Invalid PBL or PCIE UR response occurred during data read access. */
		#define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR UINT32_C(0x2)
		/*
		* Invalid PBL or PCIE UR response occurred in RQ/SRQ WQE or
		* ORRQ read access.
		*/
		#define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR UINT32_C(0x3)
		/* Invalid PBL occurred during data write access. */
		#define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR UINT32_C(0x4)
		/* Invalid PBL occurred during CQ write access. */
		#define CREQ_FUNC_EVENT_EVENT_CQ_ERROR UINT32_C(0x5)
		/* Invalid PBL or PCIE UR response occurred in TQM read access. */
		#define CREQ_FUNC_EVENT_EVENT_TQM_ERROR UINT32_C(0x6)
		/* PCIE UR response occurred in CFC read access. */
		#define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR UINT32_C(0x7)
		/* PCIE UR response occurred in CFC read access. */
		#define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR UINT32_C(0x8)
		/* PCIE UR response occurred in CFC read access. */
		#define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR UINT32_C(0x9)
		/* PCIE UR response occurred in CFC read access. */
		#define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR UINT32_C(0xa)
		/* Invalid PBL or PCIE UR response occurred on timer read access. */
		#define CREQ_FUNC_EVENT_EVENT_TIM_ERROR UINT32_C(0xb)
		/* A VF sent a backchannel command request */
		#define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST UINT32_C(0x80)
		/*
		* Communication resource (QPC, CQ, SRQ, MRW) exhausted, and
		* resource array extension is enabled
		*/
		#define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED UINT32_C(0x81)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* RoCE Slowpath Command Completion (16 bytes) */

		struct creq_qp_event {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_QP_EVENT_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_QP_EVENT_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_QP_EVENT_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_QP_EVENT_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_QP_EVENT_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		/* Success. */
		#define CREQ_QP_EVENT_STATUS_SUCCESS UINT32_C(0x0)
		/* Fail. */
		#define CREQ_QP_EVENT_STATUS_FAIL UINT32_C(0x1)
		/* Resources. */
		#define CREQ_QP_EVENT_STATUS_RESOURCES UINT32_C(0x2)
		/* Invalid command. */
		#define CREQ_QP_EVENT_STATUS_INVALID_CMD UINT32_C(0x3)
		/* Not implemented. */
		#define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED UINT32_C(0x4)
		/* Invalid parameter. */
		#define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER UINT32_C(0x5)
		/* Hardware operation failed. */
		#define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR UINT32_C(0x6)
		/* Firmware operation failed due to internal error. */
		#define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR UINT32_C(0x7)
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t reserved32;
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_QP_EVENT_V UINT32_C(0x1)
		#define CREQ_QP_EVENT_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_QP_EVENT_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Create QP command response. */
		#define CREQ_QP_EVENT_EVENT_CREATE_QP UINT32_C(0x1)
		/* Destroy QP command response. */
		#define CREQ_QP_EVENT_EVENT_DESTROY_QP UINT32_C(0x2)
		/* Modify QP command response. */
		#define CREQ_QP_EVENT_EVENT_MODIFY_QP UINT32_C(0x3)
		/* Query QP command response. */
		#define CREQ_QP_EVENT_EVENT_QUERY_QP UINT32_C(0x4)
		/* Create SRQ command response. */
		#define CREQ_QP_EVENT_EVENT_CREATE_SRQ UINT32_C(0x5)
		/* Destroy SRQ command response. */
		#define CREQ_QP_EVENT_EVENT_DESTROY_SRQ UINT32_C(0x6)
		/* Query SRQ command response. */
		#define CREQ_QP_EVENT_EVENT_QUERY_SRQ UINT32_C(0x8)
		/* Create CQ command response. */
		#define CREQ_QP_EVENT_EVENT_CREATE_CQ UINT32_C(0x9)
		/* Destroy CQ command response. */
		#define CREQ_QP_EVENT_EVENT_DESTROY_CQ UINT32_C(0xa)
		/* Resize CQ command response. */
		#define CREQ_QP_EVENT_EVENT_RESIZE_CQ UINT32_C(0xc)
		/* Allocate MRW command response. */
		#define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW UINT32_C(0xd)
		/* De-allocate key command response. */
		#define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY UINT32_C(0xe)
		/* Register MR command response. */
		#define CREQ_QP_EVENT_EVENT_REGISTER_MR UINT32_C(0xf)
		/* Deregister MR command response. */
		#define CREQ_QP_EVENT_EVENT_DEREGISTER_MR UINT32_C(0x10)
		/* Add GID command response. */
		#define CREQ_QP_EVENT_EVENT_ADD_GID UINT32_C(0x11)
		/* Delete GID command response. */
		#define CREQ_QP_EVENT_EVENT_DELETE_GID UINT32_C(0x12)
		/* Modify GID command response. */
		#define CREQ_QP_EVENT_EVENT_MODIFY_GID UINT32_C(0x17)
		/* Query GID command response. */
		#define CREQ_QP_EVENT_EVENT_QUERY_GID UINT32_C(0x18)
		/* Create QP1 command response. */
		#define CREQ_QP_EVENT_EVENT_CREATE_QP1 UINT32_C(0x13)
		/* Destroy QP1 command response. */
		#define CREQ_QP_EVENT_EVENT_DESTROY_QP1 UINT32_C(0x14)
		/* Create AH command response. */
		#define CREQ_QP_EVENT_EVENT_CREATE_AH UINT32_C(0x15)
		/* Destroy AH command response. */
		#define CREQ_QP_EVENT_EVENT_DESTROY_AH UINT32_C(0x16)
		/* Initialize firmware command response. */
		#define CREQ_QP_EVENT_EVENT_INITIALIZE_FW UINT32_C(0x80)
		/* De-initialize firmware command response. */
		#define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW UINT32_C(0x81)
		/* Stop PF command response. */
		#define CREQ_QP_EVENT_EVENT_STOP_FUNC UINT32_C(0x82)
		/* Query info PF command response. */
		#define CREQ_QP_EVENT_EVENT_QUERY_FUNC UINT32_C(0x83)
		/* Set function resources command response. */
		#define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84)
		/* Map TC to COS response. */
		#define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS UINT32_C(0x8a)
		/* Query firmware and interface version response. */
		#define CREQ_QP_EVENT_EVENT_QUERY_VERSION UINT32_C(0x8b)
		/* Modify congestion control response. */
		#define CREQ_QP_EVENT_EVENT_MODIFY_ROCE_CC UINT32_C(0x8c)
		/* Query congestion control response. */
		#define CREQ_QP_EVENT_EVENT_QUERY_ROCE_CC UINT32_C(0x8d)
		/* QP error notification event. */
		#define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Create QP command response (16 bytes) */

		struct creq_create_qp_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_CREATE_QP_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_CREATE_QP_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_CREATE_QP_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_CREATE_QP_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* QP context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_CREATE_QP_RESP_V UINT32_C(0x1)
		#define CREQ_CREATE_QP_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_CREATE_QP_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Create QP command response. */
		#define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP UINT32_C(0x1)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Destroy QP command response (16 bytes) */

		struct creq_destroy_qp_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_DESTROY_QP_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_DESTROY_QP_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_DESTROY_QP_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_DESTROY_QP_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* QP context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_DESTROY_QP_RESP_V UINT32_C(0x1)
		#define CREQ_DESTROY_QP_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_DESTROY_QP_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Destroy QP command response. */
		#define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP UINT32_C(0x2)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Modify QP command response (16 bytes) */

		struct creq_modify_qp_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_MODIFY_QP_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_MODIFY_QP_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_MODIFY_QP_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_MODIFY_QP_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* QP context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_MODIFY_QP_RESP_V UINT32_C(0x1)
		#define CREQ_MODIFY_QP_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_MODIFY_QP_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Modify QP command response. */
		#define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP UINT32_C(0x3)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Query QP command response (16 bytes) */

		struct creq_query_qp_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_QUERY_QP_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_QUERY_QP_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_QUERY_QP_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_QUERY_QP_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t size;
		/* Side buffer size in 16-byte units */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_QUERY_QP_RESP_V UINT32_C(0x1)
		#define CREQ_QUERY_QP_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_QUERY_QP_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Query QP command response. */
		#define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP UINT32_C(0x4)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Query QP command response side buffer structure (104 bytes) */

		struct creq_query_qp_resp_sb {
		uint8_t opcode;
		/* Command opcode. */
		/* Query QP command response. */
		#define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP UINT32_C(0x4)
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint32_t xid;
		/* QP context id */
		uint8_t en_sqd_async_notify_state;
		/* Enable congestion control. */
		/* QP state */
		#define CREQ_QUERY_QP_RESP_SB_STATE_MASK UINT32_C(0xf)
		#define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0
		/* Reset. */
		#define CREQ_QUERY_QP_RESP_SB_STATE_RESET UINT32_C(0x0)
		/* Init. */
		#define CREQ_QUERY_QP_RESP_SB_STATE_INIT UINT32_C(0x1)
		/* Ready To Receive. */
		#define CREQ_QUERY_QP_RESP_SB_STATE_RTR UINT32_C(0x2)
		/* Ready To Send. */
		#define CREQ_QUERY_QP_RESP_SB_STATE_RTS UINT32_C(0x3)
		/* SQ Drain. */
		#define CREQ_QUERY_QP_RESP_SB_STATE_SQD UINT32_C(0x4)
		/* SQ Error. */
		#define CREQ_QUERY_QP_RESP_SB_STATE_SQE UINT32_C(0x5)
		/* Error. */
		#define CREQ_QUERY_QP_RESP_SB_STATE_ERR UINT32_C(0x6)
		/* SQ drain asynchronous notification. */
		#define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY UINT32_C(0x10)
		/* Enable congestion control. */
		uint8_t access;
		/* Access flags. */
		/* Local write access. */
		#define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE UINT32_C(0x1)
		/* Remote write access. */
		#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE UINT32_C(0x2)
		/* Remote read access. */
		#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ UINT32_C(0x4)
		/* Remote atomic access. */
		#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC UINT32_C(0x8)
		uint16_t pkey;
		/* P_KEY index. */
		uint32_t qkey;
		/* Q_KEY. */
		uint32_t reserved32;
		uint32_t dgid[4];
		/* Destination GID. */
		uint32_t flow_label;
		/* Flow label. */
		uint16_t sgid_index;
		/* Source GID index. */
		uint8_t hop_limit;
		/* Hop limit. */
		uint8_t traffic_class;
		/* Traffic class. */
		uint16_t dest_mac[3];
		/* Destination MAC address. */
		uint16_t path_mtu_dest_vlan_id;
		/* Path MTU. */
		/* Destination VLAN ID. */
		#define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK UINT32_C(0xfff)
		#define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0
		/* Path MTU. */
		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK UINT32_C(0xf000)
		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12
		/* 256. */
		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (UINT32_C(0x0) << 12)
		/* 512. */
		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (UINT32_C(0x1) << 12)
		/* 1024. */
		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (UINT32_C(0x2) << 12)
		/* 2048. */
		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (UINT32_C(0x3) << 12)
		/* 4096. */
		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (UINT32_C(0x4) << 12)
		/* 8192. */
		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (UINT32_C(0x5) << 12)
		uint8_t timeout;
		/* Timeout value for SWQEs. */
		uint8_t retry_cnt;
		/* Max retry count for WQEs. */
		uint8_t rnr_retry;
		/* Max RNR retry count for WQEs. */
		uint8_t min_rnr_timer;
		/* Min RNR timer that the QP will report to the remote. */
		uint32_t rq_psn;
		/* RQ start packet sequence number. */
		uint32_t sq_psn;
		/* SQ start packet sequence number. */
		uint8_t max_rd_atomic;
		/* Max outstanding RDMA read atomic. */
		uint8_t max_dest_rd_atomic;
		/* Max destination outstanding RDMA read atomic. */
		uint8_t tos_dscp_tos_ecn;
		/* IP TOS DSCP. */
		/* IP TOS ECN. */
		#define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK UINT32_C(0x3)
		#define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0
		/* IP TOS DSCP. */
		#define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc)
		#define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2
		uint8_t enable_cc;
		/* enable_cc is 1 b */
		#define CREQ_QUERY_QP_RESP_SB_ENABLE_CC UINT32_C(0x1)
		#define CREQ_QUERY_QP_RESP_SB_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_QUERY_QP_RESP_SB_RESERVED7_SFT 1
		uint32_t sq_size;
		/* Max send WQE. */
		uint32_t rq_size;
		/* Max recv WQE. */
		uint16_t sq_sge;
		/* Max send SGEs per SWQE. */
		uint16_t rq_sge;
		/* Max recv SGEs per RWQE (NOT SUPPORTED BY HARDWARE). */
		uint32_t max_inline_data;
		/* Max inline data length (upto 120 bytes). */
		uint32_t dest_qp_id;
		/* Destination QP id. */
		uint32_t unused_1;
		uint16_t src_mac[3];
		/* Source MAC. */
		uint16_t vlan_pcp_vlan_dei_vlan_id;
		/* VLAN PCP field - Priority Code Point. */
		/* Source VLAN id. */
		#define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK UINT32_C(0xfff)
		#define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0
		/* VLAN DEI field - Drop Eligibility Indicator. */
		#define CREQ_QUERY_QP_RESP_SB_VLAN_DEI UINT32_C(0x1000)
		/* VLAN PCP field - Priority Code Point. */
		#define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK UINT32_C(0xe000)
		#define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13
		} __attribute__((packed));

		/* Create SRQ command response (16 bytes) */

		struct creq_create_srq_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_CREATE_SRQ_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_CREATE_SRQ_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_CREATE_SRQ_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* SRQ context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_CREATE_SRQ_RESP_V UINT32_C(0x1)
		#define CREQ_CREATE_SRQ_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_CREATE_SRQ_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Create SRQ command response. */
		#define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ UINT32_C(0x5)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Destroy SRQ command response (16 bytes) */

		struct creq_destroy_srq_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_DESTROY_SRQ_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_DESTROY_SRQ_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_DESTROY_SRQ_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* SRQ context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_DESTROY_SRQ_RESP_V UINT32_C(0x1)
		#define CREQ_DESTROY_SRQ_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_DESTROY_SRQ_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Destroy SRQ command response. */
		#define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ UINT32_C(0x6)
		uint16_t enable_for_arm[3];
		/* Set to 1 if this SRQ is allowed to be armed for threshold async event */
		#define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK UINT32_C(0x30000)
		#define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16
		#define CREQ_DESTROY_SRQ_RESP_RESERVED46_MASK UINT32_C(0xfffc0000)
		#define CREQ_DESTROY_SRQ_RESP_RESERVED46_SFT 18
		} __attribute__((packed));

		/* Query SRQ command response (16 bytes) */

		struct creq_query_srq_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_QUERY_SRQ_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_QUERY_SRQ_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_QUERY_SRQ_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t size;
		/* Side buffer size in 16-byte units */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_QUERY_SRQ_RESP_V UINT32_C(0x1)
		#define CREQ_QUERY_SRQ_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_QUERY_SRQ_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Query SRQ command response. */
		#define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ UINT32_C(0x8)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Query SRQ command response side buffer structure (24 bytes) */

		struct creq_query_srq_resp_sb {
		uint8_t opcode;
		/* Command opcode. */
		/* Query SRQ command response. */
		#define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ UINT32_C(0x8)
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint32_t xid;
		/* SRQ context id */
		uint16_t srq_limit;
		/* Watermark value to generate a SRQ limit event. */
		uint16_t reserved16;
		uint32_t data[4];
		/* data is 128 b */
		} __attribute__((packed));

		/* Create CQ command Response (16 bytes) */

		struct creq_create_cq_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_CREATE_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_CREATE_CQ_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_CREATE_CQ_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_CREATE_CQ_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* CQ context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_CREATE_CQ_RESP_V UINT32_C(0x1)
		#define CREQ_CREATE_CQ_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_CREATE_CQ_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Create CQ command response. */
		#define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ UINT32_C(0x9)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Destroy CQ command response (16 bytes) */

		struct creq_destroy_cq_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_DESTROY_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_DESTROY_CQ_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_DESTROY_CQ_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* CQ context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_DESTROY_CQ_RESP_V UINT32_C(0x1)
		#define CREQ_DESTROY_CQ_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_DESTROY_CQ_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Destroy CQ command response. */
		#define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ UINT32_C(0xa)
		uint16_t cq_arm_lvl;
		/*
		* CQ ARM Level: 0 ? Not Armed 1 ? Arm SE Only, Generate CNQE only for
		* incoming Solicted Events 2 ? Arm all, Generate CNQE for Rx and Tx
		*/
		#define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK UINT32_C(0x3)
		#define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0
		#define CREQ_DESTROY_CQ_RESP_RESERVED14_MASK UINT32_C(0xfffc)
		#define CREQ_DESTROY_CQ_RESP_RESERVED14_SFT 2
		uint16_t total_cnq_events;
		/*
		* The total number of CNQ events for the CQ, incremented on each CNQ
		* event for the CQ (including firmware-generated CQ error
		* notification).
		*/
		uint16_t reserved16;
		} __attribute__((packed));

		/* Resize CQ command response (16 bytes) */

		struct creq_resize_cq_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_RESIZE_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_RESIZE_CQ_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_RESIZE_CQ_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* CQ context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_RESIZE_CQ_RESP_V UINT32_C(0x1)
		#define CREQ_RESIZE_CQ_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_RESIZE_CQ_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Resize CQ command response. */
		#define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ UINT32_C(0xc)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Allocate MRW command response (16 bytes) */

		struct creq_allocate_mrw_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_ALLOCATE_MRW_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_ALLOCATE_MRW_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* L_KEY for MR, R_KEY for MW */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_ALLOCATE_MRW_RESP_V UINT32_C(0x1)
		#define CREQ_ALLOCATE_MRW_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_ALLOCATE_MRW_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Allocate MRW command response. */
		#define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW UINT32_C(0xd)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* De-allocate key command response (16 bytes) */

		struct creq_deallocate_key_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* L_KEY for MR, R_KEY for MW */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_DEALLOCATE_KEY_RESP_V UINT32_C(0x1)
		#define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* De-allocate key command response. */
		#define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY UINT32_C(0xe)
		uint16_t reserved16;
		uint32_t bound_window_info;
		/*
		* This is advisory data to facilitate eventual descruction of lingering
		* memory regions in Windows. For memory window, it contains non-zero
		* HWID of a region this window was bound to (without the 8-bit key
		* portion). The host may check if the region is lingering in destroyed
		* state and try to destroy it now. For memory region, if deallocation
		* fails because there are windows bound to this region, this field will
		* contain approximate number of those windows. This number is read from
		* the context right before the deregistration is attempted and can
		* potentially be slightly different from the current number.
		*/
		} __attribute__((packed));

		/* Register MR command response (16 bytes) */

		struct creq_register_mr_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_REGISTER_MR_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_REGISTER_MR_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_REGISTER_MR_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_REGISTER_MR_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* L_KEY */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_REGISTER_MR_RESP_V UINT32_C(0x1)
		#define CREQ_REGISTER_MR_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_REGISTER_MR_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Register MR command response. */
		#define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR UINT32_C(0xf)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Deregister MR command response (16 bytes) */

		struct creq_deregister_mr_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_DEREGISTER_MR_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_DEREGISTER_MR_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_DEREGISTER_MR_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* L_KEY */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_DEREGISTER_MR_RESP_V UINT32_C(0x1)
		#define CREQ_DEREGISTER_MR_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_DEREGISTER_MR_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Deregister MR command response. */
		#define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR UINT32_C(0x10)
		uint16_t reserved16;
		uint32_t bound_windows;
		/*
		* If deregister fails because there are windows bound to this region,
		* this field will contain approximate number of those windows. This
		* number is read from the context right before the deregistration is
		* attempted and can potentially be slightly different from the current
		* number.
		*/
		} __attribute__((packed));

		/* Add GID command response (16 bytes) */

		struct creq_add_gid_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_ADD_GID_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_ADD_GID_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_ADD_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_ADD_GID_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_ADD_GID_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* GID index */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_ADD_GID_RESP_V UINT32_C(0x1)
		#define CREQ_ADD_GID_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_ADD_GID_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Add GID command response. */
		#define CREQ_ADD_GID_RESP_EVENT_ADD_GID UINT32_C(0x11)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Delete GID command response (16 bytes) */

		struct creq_delete_gid_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_DELETE_GID_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_DELETE_GID_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_DELETE_GID_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_DELETE_GID_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* GID index */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_DELETE_GID_RESP_V UINT32_C(0x1)
		#define CREQ_DELETE_GID_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_DELETE_GID_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Delete GID command response. */
		#define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID UINT32_C(0x12)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Modify GID command response (16 bytes) */

		struct creq_modify_gid_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_MODIFY_GID_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_MODIFY_GID_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_MODIFY_GID_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_MODIFY_GID_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* GID index */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_MODIFY_GID_RESP_V UINT32_C(0x1)
		#define CREQ_MODIFY_GID_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_MODIFY_GID_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Add GID command response. */
		#define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID UINT32_C(0x11)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Query GID command response (16 bytes) */

		struct creq_query_gid_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_QUERY_GID_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_QUERY_GID_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_QUERY_GID_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_QUERY_GID_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t size;
		/* Side buffer size in 16-byte units */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_QUERY_GID_RESP_V UINT32_C(0x1)
		#define CREQ_QUERY_GID_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_QUERY_GID_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Query GID command response. */
		#define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID UINT32_C(0x18)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Query GID command response side buffer structure (40 bytes) */

		struct creq_query_gid_resp_sb {
		uint8_t opcode;
		/* Command opcode. */
		/* Query GID command response. */
		#define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID UINT32_C(0x18)
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint32_t gid[4];
		/* GID */
		uint16_t src_mac[3];
		/* Source MAC. */
		uint16_t vlan;
		/* flags. */
		/* Source VLAN id. */
		#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK UINT32_C(0xfff)
		#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0
		/* This set of bits select the TPID of the VLAN Tag. */
		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK UINT32_C(0x7000)
		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12
		/* TPID = 0x88A8. */
		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12)
		/* TPID = 0x8100. */
		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12)
		/* TPID = 0x9100. */
		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12)
		/* TPID = 0x9200. */
		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12)
		/* TPID = 0x9300. */
		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12)
		/* TPID = Configurable 1. */
		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12)
		/* TPID = Configurable 2. */
		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12)
		/* TPID = Configurable 3. */
		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12)
		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3
		/*
		* Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE
		* header.
		*/
		#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN UINT32_C(0x8000)
		uint16_t ipid;
		/* Identifier field in the IP header. */
		uint16_t gid_index;
		/* GID index */
		uint32_t unused_0;
		} __attribute__((packed));

		/* Create QP1 command response (16 bytes) */

		struct creq_create_qp1_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_CREATE_QP1_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_CREATE_QP1_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_CREATE_QP1_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_CREATE_QP1_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* QP1 context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_CREATE_QP1_RESP_V UINT32_C(0x1)
		#define CREQ_CREATE_QP1_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_CREATE_QP1_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Create QP1 command response. */
		#define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 UINT32_C(0x13)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Destroy QP1 command response (16 bytes) */

		struct creq_destroy_qp1_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_DESTROY_QP1_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_DESTROY_QP1_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_DESTROY_QP1_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* QP1 context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_DESTROY_QP1_RESP_V UINT32_C(0x1)
		#define CREQ_DESTROY_QP1_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_DESTROY_QP1_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Destroy QP1 command response. */
		#define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 UINT32_C(0x14)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Create AH command response (16 bytes) */

		struct creq_create_ah_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_CREATE_AH_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_CREATE_AH_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_CREATE_AH_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_CREATE_AH_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* AH context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_CREATE_AH_RESP_V UINT32_C(0x1)
		#define CREQ_CREATE_AH_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_CREATE_AH_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Create AH command response. */
		#define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH UINT32_C(0x15)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Destroy AH command response (16 bytes) */

		struct creq_destroy_ah_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_DESTROY_AH_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_DESTROY_AH_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_DESTROY_AH_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_DESTROY_AH_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t xid;
		/* AH context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_DESTROY_AH_RESP_V UINT32_C(0x1)
		#define CREQ_DESTROY_AH_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_DESTROY_AH_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Destroy AH command response. */
		#define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH UINT32_C(0x16)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Initialize Firmware command response (16 bytes) */

		struct creq_initialize_fw_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_INITIALIZE_FW_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_INITIALIZE_FW_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_INITIALIZE_FW_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t reserved32;
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_INITIALIZE_FW_RESP_V UINT32_C(0x1)
		#define CREQ_INITIALIZE_FW_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_INITIALIZE_FW_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Initialize firmware command response. */
		#define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW UINT32_C(0x80)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* De-initialize Firmware command response (16 bytes) */

		struct creq_deinitialize_fw_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t reserved32;
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_DEINITIALIZE_FW_RESP_V UINT32_C(0x1)
		#define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* De-initialize firmware command response. */
		#define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW UINT32_C(0x81)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Stop function command response (16 bytes) */

		struct creq_stop_func_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_STOP_FUNC_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_STOP_FUNC_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_STOP_FUNC_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_STOP_FUNC_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t reserved32;
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_STOP_FUNC_RESP_V UINT32_C(0x1)
		#define CREQ_STOP_FUNC_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_STOP_FUNC_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Stop PF command response. */
		#define CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC UINT32_C(0x82)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Query function command response (16 bytes) */

		struct creq_query_func_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_QUERY_FUNC_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_QUERY_FUNC_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_QUERY_FUNC_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t size;
		/* Side buffer size in 16-byte units */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_QUERY_FUNC_RESP_V UINT32_C(0x1)
		#define CREQ_QUERY_FUNC_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_QUERY_FUNC_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Query info PF command response. */
		#define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC UINT32_C(0x83)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Query function command response side buffer structure (88 bytes) */

		struct creq_query_func_resp_sb {
		uint8_t opcode;
		/* Command opcode. */
		/* Query info PF command response. */
		#define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC UINT32_C(0x83)
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint64_t max_mr_size;
		/* Max MR size supported. */
		uint32_t max_qp;
		/* Max QP supported. */
		uint16_t max_qp_wr;
		/* Max WQEs per QP. */
		uint16_t dev_cap_flags;
		/* Device capability flags. */
		/* Allow QP resizing. */
		#define CREQ_QUERY_FUNC_RESP_SB_DEV_CAP_FLAGS_RESIZE_QP UINT32_C(0x1)
		uint32_t max_cq;
		/* Max CQs supported. */
		uint32_t max_cqe;
		/* Max CQEs per CQ supported. */
		uint32_t max_pd;
		/* Max PDs supported. */
		uint8_t max_sge;
		/* Max SGEs per QP WQE supported. */
		uint8_t max_srq_sge;
		/* Max SGEs per SRQ WQE supported. */
		uint8_t max_qp_rd_atom;
		/* Max outstanding RDMA read & atomic supported. */
		uint8_t max_qp_init_rd_atom;
		/*
		* Max outstanding RDMA read & atomic that can be sent from an
		* initiator.
		*/
		uint32_t max_mr;
		/* Max MRs supported. */
		uint32_t max_mw;
		/* Max MWs supported. */
		uint32_t max_raw_eth_qp;
		/* Max Raw Ethertype QPs supported. */
		uint32_t max_ah;
		/* Max AHs supported. */
		uint32_t max_fmr;
		/* Max FMRs supported. */
		uint32_t max_srq_wr;
		/* Max WQEs per SRQ supported. */
		uint32_t max_pkeys;
		/* Max PKEYs supported. */
		uint32_t max_inline_data;
		/* Max inline data supported. */
		uint8_t max_map_per_fmr;
		/* Max mappings per FMR supported. */
		uint8_t l2_db_space_size;
		/* L2 DB space size in pages. */
		uint16_t max_srq;
		/* Max SRQs supported. */
		uint32_t max_gid;
		/* Max GIDs supported. */
		uint32_t tqm_alloc_reqs[12];
		/*
		* An array of 48 8-bit values to specify allocation multiplier for TQM
		* host buffer regions. Each region occupies 16 MB of TQM PBL address
		* space: 0x00000000, 0x01000000, 0x02000000, etc. The host needs to
		* allocate (<Number of QPs>*multiplier, rounded up to page size) of
		* physical memory for non-zero slots and map the pages to the
		* corresponding 16MB regions. Typically there are total 3 non-zero
		* values in this array, their values are 16, 16, 12. Cu+ will only
		* populate up to index 11. SR may populate up to index 47.
		*/
		} __attribute__((packed));

		/* Set resources command response (16 bytes) */

		struct creq_set_func_resources_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t reserved32;
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_SET_FUNC_RESOURCES_RESP_V UINT32_C(0x1)
		#define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Set function resources command response. */
		#define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Map TC to COS response (16 bytes) */

		struct creq_map_tc_to_cos_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t reserved32;
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_MAP_TC_TO_COS_RESP_V UINT32_C(0x1)
		#define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Map TC to COS response. */
		#define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS UINT32_C(0x8a)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Query version response (16 bytes) */

		struct creq_query_version_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_QUERY_VERSION_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_QUERY_VERSION_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_QUERY_VERSION_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint8_t fw_maj;
		/* firmware major version */
		uint8_t fw_minor;
		/* firmware minor version */
		uint8_t fw_bld;
		/* firmware build version */
		uint8_t fw_rsvd;
		/* firmware reserved version */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_QUERY_VERSION_RESP_V UINT32_C(0x1)
		#define CREQ_QUERY_VERSION_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_QUERY_VERSION_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Query firmware and interface version response. */
		#define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION UINT32_C(0x8b)
		uint16_t reserved16;
		uint8_t intf_maj;
		/* interface major version */
		uint8_t intf_minor;
		/* interface minor version */
		uint8_t intf_bld;
		/* interface build version */
		uint8_t intf_rsvd;
		/* interface reserved version */
		} __attribute__((packed));

		/* Modify congestion control command response (16 bytes) */

		struct creq_modify_roce_cc_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_MODIFY_ROCE_CC_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_MODIFY_ROCE_CC_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t reserved32;
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_MODIFY_ROCE_CC_RESP_V UINT32_C(0x1)
		#define CREQ_MODIFY_ROCE_CC_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_MODIFY_ROCE_CC_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Modify congestion control response. */
		#define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC UINT32_C(0x8c)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Query congestion control command response (16 bytes) */

		struct creq_query_roce_cc_resp {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_QUERY_ROCE_CC_RESP_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_QUERY_ROCE_CC_RESP_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint32_t size;
		/* Side buffer size in 16-byte units */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_QUERY_ROCE_CC_RESP_V UINT32_C(0x1)
		#define CREQ_QUERY_ROCE_CC_RESP_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_QUERY_ROCE_CC_RESP_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* Query congestion control response. */
		#define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC UINT32_C(0x8d)
		uint16_t reserved48[3];
		} __attribute__((packed));

		/* Query congestion control command response side buffer structure (32 bytes) */

		struct creq_query_roce_cc_resp_sb {
		uint8_t opcode;
		/* Command opcode. */
		/* Query congestion control response. */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
		uint8_t status;
		/* Status of the response. */
		uint16_t cookie;
		/* Driver supplied handle to associate the command and the response. */
		uint16_t flags;
		/* Flags and attribs of the command. */
		uint8_t resp_size;
		/* Size of the response buffer in 16-byte units. */
		uint8_t reserved8;
		uint8_t enable_cc;
		/* unused7 is 7 b */
		/* Enable. */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC UINT32_C(0x1)
		/* unused7 is 7 b */
		uint8_t tos_dscp_tos_ecn;
		/* IP TOS DSCP. */
		/* IP TOS ECN. */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK UINT32_C(0x3)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0
		/* IP TOS DSCP. */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2
		uint8_t g;
		/* unused5 is 5 b */
		/* Congestion Probability averaging factor. */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_G_MASK UINT32_C(0x7)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_G_SFT 0
		/* unused5 is 5 b */
		uint8_t num_phases_per_state;
		/* Number of phases in Fast Recovery and Active Increase. */
		uint16_t init_cr;
		/* The starting value of rate. */
		uint16_t init_tr;
		/* The starting value of target rate. */
		uint8_t alt_vlan_pcp;
		/* rsvd1 is 5 b */
		/* Alternate vlan pcp value for CNP packets. */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK UINT32_C(0x7)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0
		/* rsvd1 is 5 b */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK UINT32_C(0xf8)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3
		uint8_t alt_tos_dscp;
		/* rsvd4 is 2 b */
		/* Alternate IP TOS DSCP. */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0
		/* rsvd4 is 2 b */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK UINT32_C(0xc0)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6
		uint8_t cc_mode;
		/* rsvd2 is 7 b */
		/* 0 for DCTCP , 1 for TCP */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE UINT32_C(0x1)
		/* rsvd2 is 7 b */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD2_MASK UINT32_C(0xfe)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD2_SFT 1
		uint8_t tx_queue;
		/* rsvd3 is 6 b */
		/* Specifies the RoCE Tx Queue ( o to 3) to use for sending CNP packets */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_TX_QUEUE_MASK UINT32_C(0x3)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_TX_QUEUE_SFT 0
		/* rsvd3 is 6 b */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD3_MASK UINT32_C(0xfc)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD3_SFT 2
		uint16_t rtt;
		/* rsvd5 is 2 b */
		/* Round trip time in units of usecs */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK UINT32_C(0x3fff)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0
		/* rsvd5 is 2 b */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK UINT32_C(0xc000)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14
		uint16_t tcp_cp;
		/* rsvd6 is 6 b */
		/* The value used as CP when cc_mode is 1(TCP) */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK UINT32_C(0x3ff)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0
		/* rsvd6 is 6 b */
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK UINT32_C(0xfc00)
		#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10
		uint16_t inactivity_th;
		/* Inactivity time after which QP CC parameters are initialized */
		uint16_t reserved16;
		uint32_t reserved32;
		} __attribute__((packed));

		/* QP error notification event (16 bytes) */

		struct creq_qp_error_notification {
		uint8_t type;
		/*
		* This field indicates the exact type of the completion. By convention,
		* the LSB identifies the length of the record in 16B units. Even values
		* indicate 16B records. Odd values indicate 32B records.
		*/
		#define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK UINT32_C(0x3f)
		#define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0
		/* QP Async Notification */
		#define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT UINT32_C(0x38)
		#define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_MASK UINT32_C(0xc0)
		#define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_SFT 6
		uint8_t status;
		/* Status of the response. */
		uint8_t req_slow_path_state;
		/* requestor slow path state */
		uint8_t req_err_state_reason;
		/* requestor error reason */
		uint32_t xid;
		/* QP context id */
		uint8_t v;
		/*
		* This value is written by the NIC such that it will be different for
		* each pass through the completion queue. The even passes will write 1.
		* The odd passes will write 0.
		*/
		#define CREQ_QP_ERROR_NOTIFICATION_V UINT32_C(0x1)
		#define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_MASK UINT32_C(0xfe)
		#define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_SFT 1
		uint8_t event;
		/* Event or command opcode. */
		/* QP error notification event. */
		#define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0)
		uint8_t res_slow_path_state;
		/* responder slow path state */
		uint8_t res_err_state_reason;
		uint16_t sq_cons_idx;
		/*
		* Final SQ Consumer Index value. Any additional SQ WQEs will have to be
		* completed by the user provider.
		*/
		uint16_t rq_cons_idx;
		/*
		* Final RQ Consumer Index value. Any additional RQ WQEs will have to be
		* completed by the user provider.
		*/
		} __attribute__((packed));

		/* RoCE Slowpath Data Structures */
		/*
		* Note: This section documents the Host Structures used between software and
		* RoCE control firmware.
		*/
		/* hwrm_selftest_qlist */
		/*
		* Description: This function is called by a driver to determine which selftests
		* are available to be run against the requested function.
		*/
		/* Input (16 bytes) */

		struct hwrm_selftest_qlist_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		} __attribute__((packed));

		/* Output (248 bytes) */

		struct hwrm_selftest_qlist_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint8_t num_tests;
		/*
		* This field represents the number of tests available to be requested
		* by a driver.
		*/
		uint8_t available_tests;
		/* This field indicates which self-test is available to be run. */
		/* Can run the NVM test. */
		#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_NVM_TEST UINT32_C(0x1)
		/* Can run the link test. */
		#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_LINK_TEST UINT32_C(0x2)
		/* Can run the register test. */
		#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_REGISTER_TEST UINT32_C(0x4)
		/* Can run the memory test. */
		#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_MEMORY_TEST UINT32_C(0x8)
		/* Can run the PCIe serdes test. */
		#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_PCIE_SERDES_TEST UINT32_C(0x10)
		/* Can run the Ethernet serdes test. */
		#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20)
		uint8_t offline_tests;
		/* The NVM test is an offline test. */
		#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_NVM_TEST UINT32_C(0x1)
		/* The link test is an offline test. */
		#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_LINK_TEST UINT32_C(0x2)
		/* The register test is an offline test. */
		#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_REGISTER_TEST UINT32_C(0x4)
		/* The memory test is an offline test. */
		#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_MEMORY_TEST UINT32_C(0x8)
		/* The PCIe serdes test is an offline test. */
		#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_PCIE_SERDES_TEST UINT32_C(0x10)
		/* The Ethernet serdes test is an offline test. */
		#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20)
		uint8_t unused_0;
		uint16_t test_timeout;
		/*
		* This field represents the the maximum timeout for all the tests to
		* complete in milliseconds.
		*/
		uint8_t unused_1;
		uint8_t unused_2;
		char test0_name[32];
		/*
		* This field represents the name of the NVM test (ASCII chars with NULL
		* at the end).
		*/
		char test1_name[32];
		/*
		* This field represents the name of the link test (ASCII chars with
		* NULL at the end).
		*/
		char test2_name[32];
		/*
		* This field represents the name of the register test (ASCII chars with
		* NULL at the end).
		*/
		char test3_name[32];
		/*
		* This field represents the name of the memory test (ASCII chars with
		* NULL at the end).
		*/
		char test4_name[32];
		/*
		* This field represents the name of the PCIe serdes test (ASCII chars
		* with NULL at the end).
		*/
		char test5_name[32];
		/*
		* This field represents the name of the Ethernet serdes test (ASCII
		* chars with NULL at the end).
		*/
		char test6_name[32];
		/*
		* This field represents the name of some future test (ASCII chars with
		* NULL at the end).
		*/
		char test7_name[32];
		/*
		* This field represents the name of some future test (ASCII chars with
		* NULL at the end).
		*/
		} __attribute__((packed));

		/* hwrm_selftest_exec */
		/*
		* Description: This function is called by a driver to request which self tests
		* are to be run.
		*/
		/* Input (24 bytes) */

		struct hwrm_selftest_exec_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint8_t flags;
		/* This field indicates which self-test is being requested to run. */
		/* Run the NVM test. */
		#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_NVM_TEST UINT32_C(0x1)
		/* Run the link test. */
		#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_LINK_TEST UINT32_C(0x2)
		/* Run the register test. */
		#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_REGISTER_TEST UINT32_C(0x4)
		/* Run the memory test. */
		#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_MEMORY_TEST UINT32_C(0x8)
		/* Run the PCIe serdes test. */
		#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10)
		/* Run the Ethernet serdes test. */
		#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20)
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_selftest_exec_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint8_t requested_tests;
		/* The following tests were requested to be run. */
		/* A reqeust was made to run the NVM test. */
		#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_NVM_TEST UINT32_C(0x1)
		/* A request was made to run the link test. */
		#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_LINK_TEST UINT32_C(0x2)
		/* A request was made to run the register test. */
		#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_REGISTER_TEST UINT32_C(0x4)
		/* A request was made to run the memory test. */
		#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_MEMORY_TEST UINT32_C(0x8)
		/* A request was made to run the PCIe serdes test. */
		#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_PCIE_SERDES_TEST UINT32_C(0x10)
		/* A request was made to run the Ethernet serdes test. */
		#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20)
		uint8_t test_success;
		/*
		* If a test was requested to be run as seen in the requested_tests
		* field, this bit indicates whether the test was successful(1) or
		* failed(0).
		*/
		/*
		* If requested, a value of 1 indicates the NVM test completed
		* successfully.
		*/
		#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_NVM_TEST UINT32_C(0x1)
		/*
		* If requested, a value of 1 indicates the link test completed
		* successfully.
		*/
		#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_LINK_TEST UINT32_C(0x2)
		/*
		* If requested, a value of 1 indicates the register test completed
		* successfully.
		*/
		#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_REGISTER_TEST UINT32_C(0x4)
		/*
		* If requested, a value of 1 indicates the memory test completed
		* successfully.
		*/
		#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_MEMORY_TEST UINT32_C(0x8)
		/*
		* If requested, a value of 1 indicates the PCIe serdes test completed
		* successfully.
		*/
		#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PCIE_SERDES_TEST UINT32_C(0x10)
		/*
		* If requested, a value of 1 indicates the Ethernet serdes test
		* completed successfully.
		*/
		#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_ETHERNET_SERDES_TEST UINT32_C(0x20)
		uint16_t unused_0[3];
		} __attribute__((packed));

		/* hwrm_selftest_irq */
		/*
		* Description: This function is called by a driver to request the interrupt
		* test be run. In response to this request the interrupt associated with the
		* completion ring specified in the cmpl_ring field will be asserted to the
		* host.
		*/
		/* Input (16 bytes) */

		struct hwrm_selftest_irq_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		} __attribute__((packed));

		/* Output (8 bytes) */

		struct hwrm_selftest_irq_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		} __attribute__((packed));

		/* hwrm_selftest_retreive_serdes_data */
		/*
		* Description: This function is called by a driver to retreieve the data
		* collected when running the previous PCIe or Ethernet serdes test. The driver
		* can use multiple calls to this command to retreive the entire stored buffer
		* in the event it cannot do so with a single call.
		*/
		/* Input (32 bytes) */

		struct hwrm_selftest_retreive_serdes_data_input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		uint64_t resp_data_addr;
		/* Host address data is to DMA'd to. */
		uint32_t resp_data_offset;
		/*
		* This field contains the offset into the captured data to begin
		* copying the data to the host from. This should be set to 0 on the
		* initial call to this command.
		*/
		uint16_t data_len;
		/*
		* Size of the buffer pointed to by resp_data_addr. The firmware may use
		* this entire buffer or less than the entire buffer, but never more.
		*/
		uint8_t flags;
		/*
		* This field allows this command to request the individual serdes tests
		* to be run using this command.
		*/
		/* Unused. */
		#define HWRM_SELFTEST_RETREIVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_MASK UINT32_C(0xf)
		#define HWRM_SELFTEST_RETREIVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_SFT 0
		/* Run the PCIe serdes test. */
		#define HWRM_SELFTEST_RETREIVE_SERDES_DATA_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10)
		/* Run the Ethernet serdes test. */
		#define HWRM_SELFTEST_RETREIVE_SERDES_DATA_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20)
		uint8_t unused_0;
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_selftest_retreive_serdes_data_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint16_t total_data_len;
		/* Total length of stored data. */
		uint16_t copied_data_len;
		/*
		* Amount of data DMA'd to host by this call. The driver can use this
		* field along with the total_data_len field above to determine the
		* value to write to the resp_data_offset field in the next call if more
		* than one call to these commands is required to retreive all the
		* stored data.
		*/
		uint32_t unused_0;
		} __attribute__((packed));

		/* Hardware Resource Manager Specification */
		/* Description: This structure is used to configure a RSS Context. */
		/*
		* Note: The Hardware Resource Manager (HWRM) manages various hardware resources
		* inside the chip. The HWRM is implemented in firmware, and runs on embedded
		* processors inside the chip. This firmware service is vital part of the chip.
		* The chip can not be used by a driver or HWRM client without the HWRM.
		*/
		/* Input (16 bytes) */

		struct input {
		uint16_t req_type;
		/*
		* This value indicates what type of request this is. The format for the
		* rest of the command is determined by this field.
		*/
		uint16_t cmpl_ring;
		/*
		* This value indicates the what completion ring the request will be
		* optionally completed on. If the value is -1, then no CR completion
		* will be generated. Any other value must be a valid CR ring_id value
		* for this function.
		*/
		uint16_t seq_id;
		/* This value indicates the command sequence number. */
		uint16_t target_id;
		/*
		* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
		* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
		*/
		uint64_t resp_addr;
		/*
		* This is the host address where the response will be written when the
		* request is complete. This area must be 16B aligned and must be
		* cleared to zero before the request is made.
		*/
		} __attribute__((packed));

		/* Output (8 bytes) */

		struct output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		} __attribute__((packed));

		/* Short Command Structure (16 bytes) */

		struct hwrm_short_input {
		uint16_t req_type;
		/*
		* This field indicates the type of request in the request buffer. The
		* format for the rest of the command (request) is determined by this
		* field.
		*/
		uint16_t signature;
		/*
		* This field indicates a signature that is used to identify short form
		* of the command listed here. This field shall be set to 17185
		* (0x4321).
		*/
		/* Signature indicating this is a short form of HWRM command */
		#define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
		uint16_t unused_0;
		/* Reserved for future use. */
		uint16_t size;
		/* This value indicates the length of the request. */
		uint64_t req_addr;
		/*
		* This is the host address where the request was written. This area
		* must be 16B aligned.
		*/
		} __attribute__((packed));

		#define GET_HWRM_REQ_TYPE(x) \
		((x) == 0x98 ? "HWRM_CFA_ENCAP_RECORD_FREE": \
		((x) == 0x99 ? "HWRM_CFA_NTUPLE_FILTER_ALLOC": \
		((x) == 0x90 ? "HWRM_CFA_L2_FILTER_ALLOC": \
		((x) == 0x91 ? "HWRM_CFA_L2_FILTER_FREE": \
		((x) == 0x92 ? "HWRM_CFA_L2_FILTER_CFG": \
		((x) == 0x93 ? "HWRM_CFA_L2_SET_RX_MASK": \
		((x) == 0x94 ? "HWRM_CFA_VLAN_ANTISPOOF_CFG": \
		((x) == 0x95 ? "HWRM_CFA_TUNNEL_FILTER_ALLOC": \
		((x) == 0x96 ? "HWRM_CFA_TUNNEL_FILTER_FREE": \
		((x) == 0x97 ? "HWRM_CFA_ENCAP_RECORD_ALLOC": \
		((x) == 0x10 ? "RESERVED1": \
		((x) == 0x11 ? "HWRM_FUNC_RESET": \
		((x) == 0x12 ? "HWRM_FUNC_GETFID": \
		((x) == 0x13 ? "HWRM_FUNC_VF_ALLOC": \
		((x) == 0x14 ? "HWRM_FUNC_VF_FREE": \
		((x) == 0x15 ? "HWRM_FUNC_QCAPS": \
		((x) == 0x16 ? "HWRM_FUNC_QCFG": \
		((x) == 0x17 ? "HWRM_FUNC_CFG": \
		((x) == 0x18 ? "HWRM_FUNC_QSTATS": \
		((x) == 0x19 ? "HWRM_FUNC_CLR_STATS": \
		((x) == 0xe0 ? "HWRM_TEMP_MONITOR_QUERY": \
		((x) == 0xd3 ? "HWRM_FWD_ASYNC_EVENT_CMPL": \
		((x) == 0xd2 ? "HWRM_FWD_RESP": \
		((x) == 0x1a ? "HWRM_FUNC_DRV_UNRGTR": \
		((x) == 0x1b ? "HWRM_FUNC_VF_RESC_FREE": \
		((x) == 0x1c ? "HWRM_FUNC_VF_VNIC_IDS_QUERY": \
		((x) == 0x1d ? "HWRM_FUNC_DRV_RGTR": \
		((x) == 0x1e ? "HWRM_FUNC_DRV_QVER": \
		((x) == 0x1f ? "HWRM_FUNC_BUF_RGTR": \
		((x) == 0x9a ? "HWRM_CFA_NTUPLE_FILTER_FREE": \
		((x) == 0x9b ? "HWRM_CFA_NTUPLE_FILTER_CFG": \
		((x) == 0x9c ? "HWRM_CFA_EM_FLOW_ALLOC": \
		((x) == 0x9d ? "HWRM_CFA_EM_FLOW_FREE": \
		((x) == 0x9e ? "HWRM_CFA_EM_FLOW_CFG": \
		((x) == 0xd1 ? "HWRM_REJECT_FWD_RESP": \
		((x) == 0xd0 ? "HWRM_EXEC_FWD_RESP": \
		((x) == 0xff16 ? "HWRM_DBG_CFG": \
		((x) == 0xf1 ? "HWRM_WOL_FILTER_FREE": \
		((x) == 0xff14 ? "HWRM_DBG_DUMP": \
		((x) == 0xc8 ? "HWRM_FW_SET_TIME": \
		((x) == 0xc9 ? "HWRM_FW_GET_TIME": \
		((x) == 0xff15 ? "HWRM_DBG_ERASE_NVM": \
		((x) == 0xc0 ? "HWRM_FW_RESET": \
		((x) == 0xc1 ? "HWRM_FW_QSTATUS": \
		((x) == 0x70 ? "HWRM_VNIC_RSS_COS_LB_CTX_ALLOC": \
		((x) == 0x71 ? "HWRM_VNIC_RSS_COS_LB_CTX_FREE": \
		((x) == 0xb1 ? "HWRM_STAT_CTX_FREE": \
		((x) == 0xb0 ? "HWRM_STAT_CTX_ALLOC": \
		((x) == 0xb3 ? "HWRM_STAT_CTX_CLR_STATS": \
		((x) == 0xb2 ? "HWRM_STAT_CTX_QUERY": \
		((x) == 0xcb ? "HWRM_FW_GET_STRUCTURED_DATA": \
		((x) == 0xcc ? "HWRM_FW_IPC_MAILBOX": \
		((x) == 0xca ? "HWRM_FW_SET_STRUCTURED_DATA": \
		((x) == 0xfff6 ? "HWRM_NVM_GET_DEV_INFO": \
		((x) == 0x61 ? "HWRM_RING_GRP_FREE": \
		((x) == 0x60 ? "HWRM_RING_GRP_ALLOC": \
		((x) == 0x65 ? "RESERVED6": \
		((x) == 0x64 ? "RESERVED5": \
		((x) == 0xf0 ? "HWRM_WOL_FILTER_ALLOC": \
		((x) == 0xf3 ? "HWRM_WOL_REASON_QCFG": \
		((x) == 0xf2 ? "HWRM_WOL_FILTER_QCFG": \
		((x) == 0xf5 ? "HWRM_CFA_METER_PROFILE_ALLOC": \
		((x) == 0xa0 ? "HWRM_TUNNEL_DST_PORT_QUERY": \
		((x) == 0xa1 ? "HWRM_TUNNEL_DST_PORT_ALLOC": \
		((x) == 0xa2 ? "HWRM_TUNNEL_DST_PORT_FREE": \
		((x) == 0xf7 ? "HWRM_CFA_METER_PROFILE_CFG": \
		((x) == 0xfffc ? "HWRM_NVM_RAW_DUMP": \
		((x) == 0xf6 ? "HWRM_CFA_METER_PROFILE_FREE": \
		((x) == 0xfffb ? "HWRM_NVM_GET_DIR_INFO": \
		((x) == 0xfffa ? "HWRM_NVM_GET_DIR_ENTRIES": \
		((x) == 0x10a ? "HWRM_CFA_VLAN_ANTISPOOF_QCFG": \
		((x) == 0xfe ? "HWRM_CFA_VFR_FREE": \
		((x) == 0xe ? "HWRM_FUNC_BUF_UNRGTR": \
		((x) == 0xf ? "HWRM_FUNC_VF_CFG": \
		((x) == 0xffff ? "HWRM_NVM_RAW_WRITE_BLK": \
		((x) == 0xfffe ? "HWRM_NVM_WRITE": \
		((x) == 0xfffd ? "HWRM_NVM_READ": \
		((x) == 0x50 ? "HWRM_RING_ALLOC": \
		((x) == 0x51 ? "HWRM_RING_FREE": \
		((x) == 0x52 ? "HWRM_RING_CMPL_RING_QAGGINT_PARAMS": \
		((x) == 0x53 ? "HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS": \
		((x) == 0x4a ? "HWRM_VNIC_QCAPS": \
		((x) == 0x109 ? "HWRM_CFA_DECAP_FILTER_FREE": \
		((x) == 0x108 ? "HWRM_CFA_DECAP_FILTER_ALLOC": \
		((x) == 0x103 ? "HWRM_CFA_FLOW_ALLOC": \
		((x) == 0x102 ? "HWRM_CFA_VF_PAIR_INFO": \
		((x) == 0x101 ? "HWRM_CFA_VF_PAIR_FREE": \
		((x) == 0x100 ? "HWRM_CFA_VF_PAIR_ALLOC": \
		((x) == 0x107 ? "HWRM_CFA_FLOW_INFO": \
		((x) == 0x106 ? "HWRM_CFA_FLOW_STATS": \
		((x) == 0x105 ? "HWRM_CFA_FLOW_FLUSH": \
		((x) == 0x104 ? "HWRM_CFA_FLOW_FREE": \
		((x) == 0x49 ? "HWRM_VNIC_PLCMODES_QCFG": \
		((x) == 0x48 ? "HWRM_VNIC_PLCMODES_CFG": \
		((x) == 0x47 ? "HWRM_VNIC_RSS_QCFG": \
		((x) == 0x46 ? "HWRM_VNIC_RSS_CFG": \
		((x) == 0x45 ? "HWRM_VNIC_TPA_QCFG": \
		((x) == 0x44 ? "HWRM_VNIC_TPA_CFG": \
		((x) == 0x43 ? "HWRM_VNIC_QCFG": \
		((x) == 0x42 ? "HWRM_VNIC_CFG": \
		((x) == 0x41 ? "HWRM_VNIC_FREE": \
		((x) == 0x40 ? "HWRM_VNIC_ALLOC": \
		((x) == 0x0 ? "HWRM_VER_GET": \
		((x) == 0xfff9 ? "HWRM_NVM_FIND_DIR_ENTRY": \
		((x) == 0xfff8 ? "HWRM_NVM_MOD_DIR_ENTRY": \
		((x) == 0xfff7 ? "HWRM_NVM_ERASE_DIR_ENTRY": \
		((x) == 0x5e ? "HWRM_RING_RESET": \
		((x) == 0xfff5 ? "HWRM_NVM_VERIFY_UPDATE": \
		((x) == 0xfff4 ? "HWRM_NVM_MODIFY": \
		((x) == 0xfff3 ? "HWRM_NVM_INSTALL_UPDATE": \
		((x) == 0xfff2 ? "HWRM_NVM_SET_VARIABLE": \
		((x) == 0xfff1 ? "HWRM_NVM_GET_VARIABLE": \
		((x) == 0xfff0 ? "HWRM_NVM_FLUSH": \
		((x) == 0x2e ? "HWRM_PORT_LED_QCFG": \
		((x) == 0x2d ? "HWRM_PORT_LED_CFG": \
		((x) == 0x2f ? "HWRM_PORT_LED_QCAPS": \
		((x) == 0x2a ? "HWRM_PORT_PHY_QCAPS": \
		((x) == 0xfd ? "HWRM_CFA_VFR_ALLOC": \
		((x) == 0x2c ? "HWRM_PORT_PHY_I2C_READ": \
		((x) == 0x2b ? "HWRM_PORT_PHY_I2C_WRITE": \
		((x) == 0x38 ? "HWRM_QUEUE_PRI2COS_CFG": \
		((x) == 0x39 ? "HWRM_QUEUE_COS2BW_QCFG": \
		((x) == 0x32 ? "HWRM_QUEUE_CFG": \
		((x) == 0x33 ? "HWRM_FUNC_VLAN_CFG": \
		((x) == 0x30 ? "HWRM_QUEUE_QPORTCFG": \
		((x) == 0x31 ? "HWRM_QUEUE_QCFG": \
		((x) == 0x36 ? "HWRM_QUEUE_PFCENABLE_CFG": \
		((x) == 0x37 ? "HWRM_QUEUE_PRI2COS_QCFG": \
		((x) == 0x34 ? "HWRM_FUNC_VLAN_QCFG": \
		((x) == 0x35 ? "HWRM_QUEUE_PFCENABLE_QCFG": \
		((x) == 0x200 ? "HWRM_SELFTEST_QLIST": \
		((x) == 0x201 ? "HWRM_SELFTEST_EXEC": \
		((x) == 0x202 ? "HWRM_SELFTEST_IRQ": \
		((x) == 0x203 ? "HWRM_SELFTEST_RETREIVE_SERDES_DATA": \
		((x) == 0xff12 ? "HWRM_DBG_WRITE_DIRECT": \
		((x) == 0xff13 ? "HWRM_DBG_WRITE_INDIRECT": \
		((x) == 0xff10 ? "HWRM_DBG_READ_DIRECT": \
		((x) == 0xff11 ? "HWRM_DBG_READ_INDIRECT": \
		((x) == 0x25 ? "HWRM_PORT_CLR_STATS": \
		((x) == 0x24 ? "HWRM_PORT_LPBK_QSTATS": \
		((x) == 0x27 ? "HWRM_PORT_PHY_QCFG": \
		((x) == 0x26 ? "HWRM_PORT_LPBK_CLR_STATS": \
		((x) == 0x21 ? "HWRM_PORT_MAC_CFG": \
		((x) == 0x20 ? "HWRM_PORT_PHY_CFG": \
		((x) == 0x23 ? "HWRM_PORT_QSTATS": \
		((x) == 0x22 ? "HWRM_PORT_TS_QUERY": \
		((x) == 0xf9 ? "HWRM_CFA_METER_INSTANCE_FREE": \
		((x) == 0xf8 ? "HWRM_CFA_METER_INSTANCE_ALLOC": \
		((x) == 0x29 ? "HWRM_PORT_MAC_PTP_QCFG": \
		((x) == 0x28 ? "HWRM_PORT_MAC_QCFG": \
		((x) == 0xffef ? "HWRM_NVM_VALIDATE_OPTION": \
		((x) == 0xffee ? "HWRM_NVM_FACTORY_DEFAULTS": \
		((x) == 0x3b ? "HWRM_QUEUE_DSCP_QCAPS": \
		((x) == 0x3c ? "HWRM_QUEUE_DSCP2PRI_QCFG": \
		((x) == 0x3a ? "HWRM_QUEUE_COS2BW_CFG": \
		((x) == 0x3d ? "HWRM_QUEUE_DSCP2PRI_CFG": \
		"Unknown req_type"))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))

		/* Command numbering (8 bytes) */

		struct cmd_nums {
		uint16_t req_type;
		/*
		* This version of the specification defines the commands listed in the
		* table below. The following are general implementation requirements
		* for these commands: # All commands listed below that are marked
		* neither reserved nor experimental shall be implemented by the HWRM. #
		* A HWRM client compliant to this specification should not use commands
		* outside of the list below. # A HWRM client compliant to this
		* specification should not use command numbers marked reserved below. #
		* A command marked experimental below may not be implemented by the
		* HWRM. # A command marked experimental may change in the future
		* version of the HWRM specification. # A command not listed below may
		* be implemented by the HWRM. The behavior of commands that are not
		* listed below is outside the scope of this specification.
		*/
		#define HWRM_VER_GET (UINT32_C(0x0))
		#define HWRM_FUNC_BUF_UNRGTR (UINT32_C(0xe))
		#define HWRM_FUNC_VF_CFG (UINT32_C(0xf))
		/* Reserved for future use */
		#define RESERVED1 (UINT32_C(0x10))
		#define HWRM_FUNC_RESET (UINT32_C(0x11))
		#define HWRM_FUNC_GETFID (UINT32_C(0x12))
		#define HWRM_FUNC_VF_ALLOC (UINT32_C(0x13))
		#define HWRM_FUNC_VF_FREE (UINT32_C(0x14))
		#define HWRM_FUNC_QCAPS (UINT32_C(0x15))
		#define HWRM_FUNC_QCFG (UINT32_C(0x16))
		#define HWRM_FUNC_CFG (UINT32_C(0x17))
		#define HWRM_FUNC_QSTATS (UINT32_C(0x18))
		#define HWRM_FUNC_CLR_STATS (UINT32_C(0x19))
		#define HWRM_FUNC_DRV_UNRGTR (UINT32_C(0x1a))
		#define HWRM_FUNC_VF_RESC_FREE (UINT32_C(0x1b))
		#define HWRM_FUNC_VF_VNIC_IDS_QUERY (UINT32_C(0x1c))
		#define HWRM_FUNC_DRV_RGTR (UINT32_C(0x1d))
		#define HWRM_FUNC_DRV_QVER (UINT32_C(0x1e))
		#define HWRM_FUNC_BUF_RGTR (UINT32_C(0x1f))
		#define HWRM_PORT_PHY_CFG (UINT32_C(0x20))
		#define HWRM_PORT_MAC_CFG (UINT32_C(0x21))
		/* Experimental */
		#define HWRM_PORT_TS_QUERY (UINT32_C(0x22))
		#define HWRM_PORT_QSTATS (UINT32_C(0x23))
		#define HWRM_PORT_LPBK_QSTATS (UINT32_C(0x24))
		/* Experimental */
		#define HWRM_PORT_CLR_STATS (UINT32_C(0x25))
		/* Experimental */
		#define HWRM_PORT_LPBK_CLR_STATS (UINT32_C(0x26))
		#define HWRM_PORT_PHY_QCFG (UINT32_C(0x27))
		#define HWRM_PORT_MAC_QCFG (UINT32_C(0x28))
		/* Experimental */
		#define HWRM_PORT_MAC_PTP_QCFG (UINT32_C(0x29))
		#define HWRM_PORT_PHY_QCAPS (UINT32_C(0x2a))
		#define HWRM_PORT_PHY_I2C_WRITE (UINT32_C(0x2b))
		#define HWRM_PORT_PHY_I2C_READ (UINT32_C(0x2c))
		#define HWRM_PORT_LED_CFG (UINT32_C(0x2d))
		#define HWRM_PORT_LED_QCFG (UINT32_C(0x2e))
		#define HWRM_PORT_LED_QCAPS (UINT32_C(0x2f))
		#define HWRM_QUEUE_QPORTCFG (UINT32_C(0x30))
		#define HWRM_QUEUE_QCFG (UINT32_C(0x31))
		#define HWRM_QUEUE_CFG (UINT32_C(0x32))
		#define HWRM_FUNC_VLAN_CFG (UINT32_C(0x33))
		#define HWRM_FUNC_VLAN_QCFG (UINT32_C(0x34))
		#define HWRM_QUEUE_PFCENABLE_QCFG (UINT32_C(0x35))
		#define HWRM_QUEUE_PFCENABLE_CFG (UINT32_C(0x36))
		#define HWRM_QUEUE_PRI2COS_QCFG (UINT32_C(0x37))
		#define HWRM_QUEUE_PRI2COS_CFG (UINT32_C(0x38))
		#define HWRM_QUEUE_COS2BW_QCFG (UINT32_C(0x39))
		#define HWRM_QUEUE_COS2BW_CFG (UINT32_C(0x3a))
		/* Experimental */
		#define HWRM_QUEUE_DSCP_QCAPS (UINT32_C(0x3b))
		/* Experimental */
		#define HWRM_QUEUE_DSCP2PRI_QCFG (UINT32_C(0x3c))
		/* Experimental */
		#define HWRM_QUEUE_DSCP2PRI_CFG (UINT32_C(0x3d))
		#define HWRM_VNIC_ALLOC (UINT32_C(0x40))
		#define HWRM_VNIC_FREE (UINT32_C(0x41))
		#define HWRM_VNIC_CFG (UINT32_C(0x42))
		#define HWRM_VNIC_QCFG (UINT32_C(0x43))
		#define HWRM_VNIC_TPA_CFG (UINT32_C(0x44))
		/* Experimental */
		#define HWRM_VNIC_TPA_QCFG (UINT32_C(0x45))
		#define HWRM_VNIC_RSS_CFG (UINT32_C(0x46))
		#define HWRM_VNIC_RSS_QCFG (UINT32_C(0x47))
		#define HWRM_VNIC_PLCMODES_CFG (UINT32_C(0x48))
		#define HWRM_VNIC_PLCMODES_QCFG (UINT32_C(0x49))
		#define HWRM_VNIC_QCAPS (UINT32_C(0x4a))
		#define HWRM_RING_ALLOC (UINT32_C(0x50))
		#define HWRM_RING_FREE (UINT32_C(0x51))
		#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (UINT32_C(0x52))
		#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (UINT32_C(0x53))
		#define HWRM_RING_RESET (UINT32_C(0x5e))
		#define HWRM_RING_GRP_ALLOC (UINT32_C(0x60))
		#define HWRM_RING_GRP_FREE (UINT32_C(0x61))
		/* Reserved for future use */
		#define RESERVED5 (UINT32_C(0x64))
		/* Reserved for future use */
		#define RESERVED6 (UINT32_C(0x65))
		#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (UINT32_C(0x70))
		#define HWRM_VNIC_RSS_COS_LB_CTX_FREE (UINT32_C(0x71))
		#define HWRM_CFA_L2_FILTER_ALLOC (UINT32_C(0x90))
		#define HWRM_CFA_L2_FILTER_FREE (UINT32_C(0x91))
		#define HWRM_CFA_L2_FILTER_CFG (UINT32_C(0x92))
		#define HWRM_CFA_L2_SET_RX_MASK (UINT32_C(0x93))
		#define HWRM_CFA_VLAN_ANTISPOOF_CFG (UINT32_C(0x94))
		#define HWRM_CFA_TUNNEL_FILTER_ALLOC (UINT32_C(0x95))
		#define HWRM_CFA_TUNNEL_FILTER_FREE (UINT32_C(0x96))
		/* Experimental */
		#define HWRM_CFA_ENCAP_RECORD_ALLOC (UINT32_C(0x97))
		/* Experimental */
		#define HWRM_CFA_ENCAP_RECORD_FREE (UINT32_C(0x98))
		#define HWRM_CFA_NTUPLE_FILTER_ALLOC (UINT32_C(0x99))
		#define HWRM_CFA_NTUPLE_FILTER_FREE (UINT32_C(0x9a))
		#define HWRM_CFA_NTUPLE_FILTER_CFG (UINT32_C(0x9b))
		/* Experimental */
		#define HWRM_CFA_EM_FLOW_ALLOC (UINT32_C(0x9c))
		/* Experimental */
		#define HWRM_CFA_EM_FLOW_FREE (UINT32_C(0x9d))
		/* Experimental */
		#define HWRM_CFA_EM_FLOW_CFG (UINT32_C(0x9e))
		#define HWRM_TUNNEL_DST_PORT_QUERY (UINT32_C(0xa0))
		#define HWRM_TUNNEL_DST_PORT_ALLOC (UINT32_C(0xa1))
		#define HWRM_TUNNEL_DST_PORT_FREE (UINT32_C(0xa2))
		#define HWRM_STAT_CTX_ALLOC (UINT32_C(0xb0))
		#define HWRM_STAT_CTX_FREE (UINT32_C(0xb1))
		#define HWRM_STAT_CTX_QUERY (UINT32_C(0xb2))
		#define HWRM_STAT_CTX_CLR_STATS (UINT32_C(0xb3))
		#define HWRM_FW_RESET (UINT32_C(0xc0))
		#define HWRM_FW_QSTATUS (UINT32_C(0xc1))
		/* Experimental */
		#define HWRM_FW_SET_TIME (UINT32_C(0xc8))
		/* Experimental */
		#define HWRM_FW_GET_TIME (UINT32_C(0xc9))
		/* Experimental */
		#define HWRM_FW_SET_STRUCTURED_DATA (UINT32_C(0xca))
		/* Experimental */
		#define HWRM_FW_GET_STRUCTURED_DATA (UINT32_C(0xcb))
		/* Experimental */
		#define HWRM_FW_IPC_MAILBOX (UINT32_C(0xcc))
		#define HWRM_EXEC_FWD_RESP (UINT32_C(0xd0))
		#define HWRM_REJECT_FWD_RESP (UINT32_C(0xd1))
		#define HWRM_FWD_RESP (UINT32_C(0xd2))
		#define HWRM_FWD_ASYNC_EVENT_CMPL (UINT32_C(0xd3))
		#define HWRM_TEMP_MONITOR_QUERY (UINT32_C(0xe0))
		#define HWRM_WOL_FILTER_ALLOC (UINT32_C(0xf0))
		#define HWRM_WOL_FILTER_FREE (UINT32_C(0xf1))
		#define HWRM_WOL_FILTER_QCFG (UINT32_C(0xf2))
		#define HWRM_WOL_REASON_QCFG (UINT32_C(0xf3))
		/* Experimental */
		#define HWRM_CFA_METER_PROFILE_ALLOC (UINT32_C(0xf5))
		/* Experimental */
		#define HWRM_CFA_METER_PROFILE_FREE (UINT32_C(0xf6))
		/* Experimental */
		#define HWRM_CFA_METER_PROFILE_CFG (UINT32_C(0xf7))
		/* Experimental */
		#define HWRM_CFA_METER_INSTANCE_ALLOC (UINT32_C(0xf8))
		/* Experimental */
		#define HWRM_CFA_METER_INSTANCE_FREE (UINT32_C(0xf9))
		/* Experimental */
		#define HWRM_CFA_VFR_ALLOC (UINT32_C(0xfd))
		/* Experimental */
		#define HWRM_CFA_VFR_FREE (UINT32_C(0xfe))
		/* Experimental */
		#define HWRM_CFA_VF_PAIR_ALLOC (UINT32_C(0x100))
		/* Experimental */
		#define HWRM_CFA_VF_PAIR_FREE (UINT32_C(0x101))
		/* Experimental */
		#define HWRM_CFA_VF_PAIR_INFO (UINT32_C(0x102))
		/* Experimental */
		#define HWRM_CFA_FLOW_ALLOC (UINT32_C(0x103))
		/* Experimental */
		#define HWRM_CFA_FLOW_FREE (UINT32_C(0x104))
		/* Experimental */
		#define HWRM_CFA_FLOW_FLUSH (UINT32_C(0x105))
		/* Experimental */
		#define HWRM_CFA_FLOW_STATS (UINT32_C(0x106))
		/* Experimental */
		#define HWRM_CFA_FLOW_INFO (UINT32_C(0x107))
		/* Experimental */
		#define HWRM_CFA_DECAP_FILTER_ALLOC (UINT32_C(0x108))
		/* Experimental */
		#define HWRM_CFA_DECAP_FILTER_FREE (UINT32_C(0x109))
		#define HWRM_CFA_VLAN_ANTISPOOF_QCFG (UINT32_C(0x10a))
		/* Experimental */
		#define HWRM_SELFTEST_QLIST (UINT32_C(0x200))
		/* Experimental */
		#define HWRM_SELFTEST_EXEC (UINT32_C(0x201))
		/* Experimental */
		#define HWRM_SELFTEST_IRQ (UINT32_C(0x202))
		/* Experimental */
		#define HWRM_SELFTEST_RETREIVE_SERDES_DATA (UINT32_C(0x203))
		/* Experimental */
		#define HWRM_DBG_READ_DIRECT (UINT32_C(0xff10))
		/* Experimental */
		#define HWRM_DBG_READ_INDIRECT (UINT32_C(0xff11))
		/* Experimental */
		#define HWRM_DBG_WRITE_DIRECT (UINT32_C(0xff12))
		/* Experimental */
		#define HWRM_DBG_WRITE_INDIRECT (UINT32_C(0xff13))
		#define HWRM_DBG_DUMP (UINT32_C(0xff14))
		/* Experimental */
		#define HWRM_DBG_ERASE_NVM (UINT32_C(0xff15))
		shurdUnsubmitted Done Inline Actions Was this not generated from the hsi_struct_defs_external.h file? I thought that some of these commands were supposed to be confidential. shurd: Was this not generated from the hsi_struct_defs_external.h file? I thought that some of these…
		bhargava.marreddy_broadcom.comAuthorUnsubmitted Not Done Inline Actions Thanks, it is my mistake. used correct hsi_struct_defs_external.h file this time. bhargava.marreddy_broadcom.com: Thanks, it is my mistake. used correct hsi_struct_defs_external.h file this time.
		/* Experimental */
		#define HWRM_DBG_CFG (UINT32_C(0xff16))
		/* Experimental */
		#define HWRM_NVM_FACTORY_DEFAULTS (UINT32_C(0xffee))
		#define HWRM_NVM_VALIDATE_OPTION (UINT32_C(0xffef))
		#define HWRM_NVM_FLUSH (UINT32_C(0xfff0))
		#define HWRM_NVM_GET_VARIABLE (UINT32_C(0xfff1))
		#define HWRM_NVM_SET_VARIABLE (UINT32_C(0xfff2))
		#define HWRM_NVM_INSTALL_UPDATE (UINT32_C(0xfff3))
		#define HWRM_NVM_MODIFY (UINT32_C(0xfff4))
		#define HWRM_NVM_VERIFY_UPDATE (UINT32_C(0xfff5))
		#define HWRM_NVM_GET_DEV_INFO (UINT32_C(0xfff6))
		#define HWRM_NVM_ERASE_DIR_ENTRY (UINT32_C(0xfff7))
		#define HWRM_NVM_MOD_DIR_ENTRY (UINT32_C(0xfff8))
		#define HWRM_NVM_FIND_DIR_ENTRY (UINT32_C(0xfff9))
		#define HWRM_NVM_GET_DIR_ENTRIES (UINT32_C(0xfffa))
		#define HWRM_NVM_GET_DIR_INFO (UINT32_C(0xfffb))
		#define HWRM_NVM_RAW_DUMP (UINT32_C(0xfffc))
		#define HWRM_NVM_READ (UINT32_C(0xfffd))
		#define HWRM_NVM_WRITE (UINT32_C(0xfffe))
		#define HWRM_NVM_RAW_WRITE_BLK (UINT32_C(0xffff))
		uint16_t unused_0[3];
		} __attribute__((packed));

		#define GET_HWRM_ERROR_CODE(x) \
		((x) == 0xf ? "HWRM_ERROR": \
		((x) == 0xffff ? "CMD_NOT_SUPPORTED": \
		((x) == 0xfffe ? "UNKNOWN_ERR": \
		((x) == 0x4 ? "RESOURCE_ALLOC_ERROR": \
		((x) == 0x5 ? "INVALID_FLAGS": \
		((x) == 0x6 ? "INVALID_ENABLES": \
		((x) == 0x0 ? "SUCCESS": \
		((x) == 0x1 ? "FAIL": \
		((x) == 0x2 ? "INVALID_PARAMS": \
		((x) == 0x3 ? "RESOURCE_ACCESS_DENIED": \
		"Unknown error_code"))))))))))

		/* Return Codes (8 bytes) */

		struct ret_codes {
		uint16_t error_code;
		/* These are numbers assigned to return/error codes. */
		/* Request was successfully executed by the HWRM. */
		#define HWRM_ERR_CODE_SUCCESS (UINT32_C(0x0))
		/* THe HWRM failed to execute the request. */
		#define HWRM_ERR_CODE_FAIL (UINT32_C(0x1))
		/* The request contains invalid argument(s) or input parameters. */
		#define HWRM_ERR_CODE_INVALID_PARAMS (UINT32_C(0x2))
		/*
		* The requester is not allowed to access the requested
		* resource. This error code shall be provided in a response to
		* a request to query or modify an existing resource that is not
		* accessible by the requester.
		*/
		#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (UINT32_C(0x3))
		/*
		* The HWRM is unable to allocate the requested resource. This
		* code only applies to requests for HWRM resource allocations.
		*/
		#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (UINT32_C(0x4))
		/* Invalid combination of flags is specified in the request. */
		#define HWRM_ERR_CODE_INVALID_FLAGS (UINT32_C(0x5))
		/*
		* Invalid combination of enables fields is specified in the
		* request.
		*/
		#define HWRM_ERR_CODE_INVALID_ENABLES (UINT32_C(0x6))
		/* Generic HWRM execution error that represents an internal error. */
		#define HWRM_ERR_CODE_HWRM_ERROR (UINT32_C(0xf))
		/* Unknown error */
		#define HWRM_ERR_CODE_UNKNOWN_ERR (UINT32_C(0xfffe))
		/* Unsupported or invalid command */
		#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (UINT32_C(0xffff))
		uint16_t unused_0[3];
		} __attribute__((packed));

		/* Output (16 bytes) */

		struct hwrm_err_output {
		uint16_t error_code;
		/*
		* Pass/Fail or error type Note: receiver to verify the in parameters,
		* and fail the call with an error when appropriate
		*/
		uint16_t req_type;
		/* This field returns the type of original request. */
		uint16_t seq_id;
		/* This field provides original sequence number of the command. */
		uint16_t resp_len;
		/*
		* This field is the length of the response in bytes. The last byte of
		* the response is a valid flag that will read as '1' when the command
		* has been completely written to memory.
		*/
		uint32_t opaque_0;
		/* debug info for this error response. */
		uint16_t opaque_1;
		/* debug info for this error response. */
		uint8_t cmd_err;
		/*
		* In the case of an error response, command specific error code is
		* returned in this field.
		*/
		uint8_t valid;
		/*
		* This field is used in Output records to indicate that the output is
		* completely written to RAM. This field should be read as '1' to
		* indicate that the output has been completely written. When writing a
		* command completion or response to an internal processor, the order of
		* writes has to be such that this field is written last.
		*/
		} __attribute__((packed));

		/* Port Tx Statistics Formats (408 bytes) */

		struct tx_port_stats {
		uint64_t tx_64b_frames;
		/* Total Number of 64 Bytes frames transmitted */
		uint64_t tx_65b_127b_frames;
		/* Total Number of 65-127 Bytes frames transmitted */
		uint64_t tx_128b_255b_frames;
		/* Total Number of 128-255 Bytes frames transmitted */
		uint64_t tx_256b_511b_frames;
		/* Total Number of 256-511 Bytes frames transmitted */
		uint64_t tx_512b_1023b_frames;
		/* Total Number of 512-1023 Bytes frames transmitted */
		uint64_t tx_1024b_1518_frames;
		/* Total Number of 1024-1518 Bytes frames transmitted */
		uint64_t tx_good_vlan_frames;
		/*
		* Total Number of each good VLAN (exludes FCS errors) frame transmitted
		* which is 1519 to 1522 bytes in length inclusive (excluding framing
		* bits but including FCS bytes).
		*/
		uint64_t tx_1519b_2047_frames;
		/* Total Number of 1519-2047 Bytes frames transmitted */
		uint64_t tx_2048b_4095b_frames;
		/* Total Number of 2048-4095 Bytes frames transmitted */
		uint64_t tx_4096b_9216b_frames;
		/* Total Number of 4096-9216 Bytes frames transmitted */
		uint64_t tx_9217b_16383b_frames;
		/* Total Number of 9217-16383 Bytes frames transmitted */
		uint64_t tx_good_frames;
		/* Total Number of good frames transmitted */
		uint64_t tx_total_frames;
		/* Total Number of frames transmitted */
		uint64_t tx_ucast_frames;
		/* Total number of unicast frames transmitted */
		uint64_t tx_mcast_frames;
		/* Total number of multicast frames transmitted */
		uint64_t tx_bcast_frames;
		/* Total number of broadcast frames transmitted */
		uint64_t tx_pause_frames;
		/* Total number of PAUSE control frames transmitted */
		uint64_t tx_pfc_frames;
		/* Total number of PFC/per-priority PAUSE control frames transmitted */
		uint64_t tx_jabber_frames;
		/* Total number of jabber frames transmitted */
		uint64_t tx_fcs_err_frames;
		/* Total number of frames transmitted with FCS error */
		uint64_t tx_control_frames;
		/* Total number of control frames transmitted */
		uint64_t tx_oversz_frames;
		/* Total number of over-sized frames transmitted */
		uint64_t tx_single_dfrl_frames;
		/* Total number of frames with single deferral */
		uint64_t tx_multi_dfrl_frames;
		/* Total number of frames with multiple deferrals */
		uint64_t tx_single_coll_frames;
		/* Total number of frames with single collision */
		uint64_t tx_multi_coll_frames;
		/* Total number of frames with multiple collisions */
		uint64_t tx_late_coll_frames;
		/* Total number of frames with late collisions */
		uint64_t tx_excessive_coll_frames;
		/* Total number of frames with excessive collisions */
		uint64_t tx_frag_frames;
		/* Total number of fragmented frames transmitted */
		uint64_t tx_err;
		/* Total number of transmit errors */
		uint64_t tx_tagged_frames;
		/* Total number of single VLAN tagged frames transmitted */
		uint64_t tx_dbl_tagged_frames;
		/* Total number of double VLAN tagged frames transmitted */
		uint64_t tx_runt_frames;
		/* Total number of runt frames transmitted */
		uint64_t tx_fifo_underruns;
		/* Total number of TX FIFO under runs */
		uint64_t tx_pfc_ena_frames_pri0;
		/* Total number of PFC frames with PFC enabled bit for Pri 0 transmitted */
		uint64_t tx_pfc_ena_frames_pri1;
		/* Total number of PFC frames with PFC enabled bit for Pri 1 transmitted */
		uint64_t tx_pfc_ena_frames_pri2;
		/* Total number of PFC frames with PFC enabled bit for Pri 2 transmitted */
		uint64_t tx_pfc_ena_frames_pri3;
		/* Total number of PFC frames with PFC enabled bit for Pri 3 transmitted */
		uint64_t tx_pfc_ena_frames_pri4;
		/* Total number of PFC frames with PFC enabled bit for Pri 4 transmitted */
		uint64_t tx_pfc_ena_frames_pri5;
		/* Total number of PFC frames with PFC enabled bit for Pri 5 transmitted */
		uint64_t tx_pfc_ena_frames_pri6;
		/* Total number of PFC frames with PFC enabled bit for Pri 6 transmitted */
		uint64_t tx_pfc_ena_frames_pri7;
		/* Total number of PFC frames with PFC enabled bit for Pri 7 transmitted */
		uint64_t tx_eee_lpi_events;
		/* Total number of EEE LPI Events on TX */
		uint64_t tx_eee_lpi_duration;
		/* EEE LPI Duration Counter on TX */
		uint64_t tx_llfc_logical_msgs;
		/* Total number of Link Level Flow Control (LLFC) messages transmitted */
		uint64_t tx_hcfc_msgs;
		/* Total number of HCFC messages transmitted */
		uint64_t tx_total_collisions;
		/* Total number of TX collisions */
		uint64_t tx_bytes;
		/* Total number of transmitted bytes */
		uint64_t tx_xthol_frames;
		/* Total number of end-to-end HOL frames */
		uint64_t tx_stat_discard;
		/* Total Tx Drops per Port reported by STATS block */
		uint64_t tx_stat_error;
		/* Total Tx Error Drops per Port reported by STATS block */
		} __attribute__((packed));

		/* Port Rx Statistics Formats (528 bytes) */

		struct rx_port_stats {
		uint64_t rx_64b_frames;
		/* Total Number of 64 Bytes frames received */
		uint64_t rx_65b_127b_frames;
		/* Total Number of 65-127 Bytes frames received */
		uint64_t rx_128b_255b_frames;
		/* Total Number of 128-255 Bytes frames received */
		uint64_t rx_256b_511b_frames;
		/* Total Number of 256-511 Bytes frames received */
		uint64_t rx_512b_1023b_frames;
		/* Total Number of 512-1023 Bytes frames received */
		uint64_t rx_1024b_1518_frames;
		/* Total Number of 1024-1518 Bytes frames received */
		uint64_t rx_good_vlan_frames;
		/*
		* Total Number of each good VLAN (exludes FCS errors) frame received
		* which is 1519 to 1522 bytes in length inclusive (excluding framing
		* bits but including FCS bytes).
		*/
		uint64_t rx_1519b_2047b_frames;
		/* Total Number of 1519-2047 Bytes frames received */
		uint64_t rx_2048b_4095b_frames;
		/* Total Number of 2048-4095 Bytes frames received */
		uint64_t rx_4096b_9216b_frames;
		/* Total Number of 4096-9216 Bytes frames received */
		uint64_t rx_9217b_16383b_frames;
		/* Total Number of 9217-16383 Bytes frames received */
		uint64_t rx_total_frames;
		/* Total number of frames received */
		uint64_t rx_ucast_frames;
		/* Total number of unicast frames received */
		uint64_t rx_mcast_frames;
		/* Total number of multicast frames received */
		uint64_t rx_bcast_frames;
		/* Total number of broadcast frames received */
		uint64_t rx_fcs_err_frames;
		/* Total number of received frames with FCS error */
		uint64_t rx_ctrl_frames;
		/* Total number of control frames received */
		uint64_t rx_pause_frames;
		/* Total number of PAUSE frames received */
		uint64_t rx_pfc_frames;
		/* Total number of PFC frames received */
		uint64_t rx_unsupported_opcode_frames;
		/* Total number of frames received with an unsupported opcode */
		uint64_t rx_unsupported_da_pausepfc_frames;
		/*
		* Total number of frames received with an unsupported DA for pause and
		* PFC
		*/
		uint64_t rx_wrong_sa_frames;
		/* Total number of frames received with an unsupported SA */
		uint64_t rx_align_err_frames;
		/* Total number of received packets with alignment error */
		uint64_t rx_oor_len_frames;
		/* Total number of received frames with out-of-range length */
		uint64_t rx_code_err_frames;
		/* Total number of received frames with error termination */
		uint64_t rx_false_carrier_frames;
		/*
		* Total number of received frames with a false carrier is detected
		* during idle, as defined by RX_ER samples active and RXD is 0xE. The
		* event is reported along with the statistics generated on the next
		* received frame. Only one false carrier condition can be detected and
		* logged between frames. Carrier event, valid for 10M/100M speed modes
		* only.
		*/
		uint64_t rx_ovrsz_frames;
		/* Total number of over-sized frames received */
		uint64_t rx_jbr_frames;
		/* Total number of jabber packets received */
		uint64_t rx_mtu_err_frames;
		/* Total number of received frames with MTU error */
		uint64_t rx_match_crc_frames;
		/* Total number of received frames with CRC match */
		uint64_t rx_promiscuous_frames;
		/* Total number of frames received promiscuously */
		uint64_t rx_tagged_frames;
		/* Total number of received frames with one or two VLAN tags */
		uint64_t rx_double_tagged_frames;
		/* Total number of received frames with two VLAN tags */
		uint64_t rx_trunc_frames;
		/* Total number of truncated frames received */
		uint64_t rx_good_frames;
		/* Total number of good frames (without errors) received */
		uint64_t rx_pfc_xon2xoff_frames_pri0;
		/*
		* Total number of received PFC frames with transition from XON to XOFF
		* on Pri 0
		*/
		uint64_t rx_pfc_xon2xoff_frames_pri1;
		/*
		* Total number of received PFC frames with transition from XON to XOFF
		* on Pri 1
		*/
		uint64_t rx_pfc_xon2xoff_frames_pri2;
		/*
		* Total number of received PFC frames with transition from XON to XOFF
		* on Pri 2
		*/
		uint64_t rx_pfc_xon2xoff_frames_pri3;
		/*
		* Total number of received PFC frames with transition from XON to XOFF
		* on Pri 3
		*/
		uint64_t rx_pfc_xon2xoff_frames_pri4;
		/*
		* Total number of received PFC frames with transition from XON to XOFF
		* on Pri 4
		*/
		uint64_t rx_pfc_xon2xoff_frames_pri5;
		/*
		* Total number of received PFC frames with transition from XON to XOFF
		* on Pri 5
		*/
		uint64_t rx_pfc_xon2xoff_frames_pri6;
		/*
		* Total number of received PFC frames with transition from XON to XOFF
		* on Pri 6
		*/
		uint64_t rx_pfc_xon2xoff_frames_pri7;
		/*
		* Total number of received PFC frames with transition from XON to XOFF
		* on Pri 7
		*/
		uint64_t rx_pfc_ena_frames_pri0;
		/* Total number of received PFC frames with PFC enabled bit for Pri 0 */
		uint64_t rx_pfc_ena_frames_pri1;
		/* Total number of received PFC frames with PFC enabled bit for Pri 1 */
		uint64_t rx_pfc_ena_frames_pri2;
		/* Total number of received PFC frames with PFC enabled bit for Pri 2 */
		uint64_t rx_pfc_ena_frames_pri3;
		/* Total number of received PFC frames with PFC enabled bit for Pri 3 */
		uint64_t rx_pfc_ena_frames_pri4;
		/* Total number of received PFC frames with PFC enabled bit for Pri 4 */
		uint64_t rx_pfc_ena_frames_pri5;
		/* Total number of received PFC frames with PFC enabled bit for Pri 5 */
		uint64_t rx_pfc_ena_frames_pri6;
		/* Total number of received PFC frames with PFC enabled bit for Pri 6 */
		uint64_t rx_pfc_ena_frames_pri7;
		/* Total number of received PFC frames with PFC enabled bit for Pri 7 */
		uint64_t rx_sch_crc_err_frames;
		/* Total Number of frames received with SCH CRC error */
		uint64_t rx_undrsz_frames;
		/* Total Number of under-sized frames received */
		uint64_t rx_frag_frames;
		/* Total Number of fragmented frames received */
		uint64_t rx_eee_lpi_events;
		/* Total number of RX EEE LPI Events */
		uint64_t rx_eee_lpi_duration;
		/* EEE LPI Duration Counter on RX */
		uint64_t rx_llfc_physical_msgs;
		/*
		* Total number of physical type Link Level Flow Control (LLFC) messages
		* received
		*/
		uint64_t rx_llfc_logical_msgs;
		/*
		* Total number of logical type Link Level Flow Control (LLFC) messages
		* received
		*/
		uint64_t rx_llfc_msgs_with_crc_err;
		/*
		* Total number of logical type Link Level Flow Control (LLFC) messages
		* received with CRC error
		*/
		uint64_t rx_hcfc_msgs;
		/* Total number of HCFC messages received */
		uint64_t rx_hcfc_msgs_with_crc_err;
		/* Total number of HCFC messages received with CRC error */
		uint64_t rx_bytes;
		/* Total number of received bytes */
		uint64_t rx_runt_bytes;
		/* Total number of bytes received in runt frames */
		uint64_t rx_runt_frames;
		/* Total number of runt frames received */
		uint64_t rx_stat_discard;
		/* Total Rx Discards per Port reported by STATS block */
		uint64_t rx_stat_err;
		/* Total Rx Error Drops per Port reported by STATS block */
		} __attribute__((packed));

		/* Periodic Statistics Context DMA to host (160 bytes) */

		struct ctx_hw_stats {
		uint64_t rx_ucast_pkts;
		/* Number of received unicast packets */
		uint64_t rx_mcast_pkts;
		/* Number of received multicast packets */
		uint64_t rx_bcast_pkts;
		/* Number of received broadcast packets */
		uint64_t rx_discard_pkts;
		/* Number of discarded packets on received path */
		uint64_t rx_drop_pkts;
		/* Number of dropped packets on received path */
		uint64_t rx_ucast_bytes;
		/* Number of received bytes for unicast traffic */
		uint64_t rx_mcast_bytes;
		/* Number of received bytes for multicast traffic */
		uint64_t rx_bcast_bytes;
		/* Number of received bytes for broadcast traffic */
		uint64_t tx_ucast_pkts;
		/* Number of transmitted unicast packets */
		uint64_t tx_mcast_pkts;
		/* Number of transmitted multicast packets */
		uint64_t tx_bcast_pkts;
		/* Number of transmitted broadcast packets */
		uint64_t tx_discard_pkts;
		/* Number of discarded packets on transmit path */
		uint64_t tx_drop_pkts;
		/* Number of dropped packets on transmit path */
		uint64_t tx_ucast_bytes;
		/* Number of transmitted bytes for unicast traffic */
		uint64_t tx_mcast_bytes;
		/* Number of transmitted bytes for multicast traffic */
		uint64_t tx_bcast_bytes;
		/* Number of transmitted bytes for broadcast traffic */
		uint64_t tpa_pkts;
		/* Number of TPA packets */
		uint64_t tpa_bytes;
		/* Number of TPA bytes */
		uint64_t tpa_events;
		/* Number of TPA events */
		uint64_t tpa_aborts;
		/* Number of TPA aborts */
		} __attribute__((packed));

		/* Structure data header (16 bytes) */

		struct hwrm_struct_hdr {
		uint16_t struct_id;
		/* This value indicates the structured data ID. */
		/* LLDP configuration structured data ID. */
		#define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_CFG UINT32_C(0x41b)
		/* DCBX ETS configuration structured data ID. */
		#define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_ETS UINT32_C(0x41d)
		/* DCBX PFC configuration structured data ID. */
		#define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_PFC UINT32_C(0x41f)
		/* DCBX APP configuration structured data ID. */
		#define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_APP UINT32_C(0x421)
		/*
		* DCBX state configuration structured data ID for all DCBX
		* features.
		*/
		#define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE UINT32_C(0x422)
		/*
		* LLDP generic structured data ID. This is used with
		* GET_STRUCTURED_DATA only.
		*/
		#define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_GENERIC UINT32_C(0x424)
		/*
		* LLDP device structured data ID. This is used with
		* GET_STRUCTURED_DATA only.
		*/
		#define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_DEVICE UINT32_C(0x426)
		/* reserved for AFM usage. */
		#define HWRM_STRUCT_HDR_STRUCT_ID_AFM_OPAQUE UINT32_C(0x1)
		/* Port description. */
		#define HWRM_STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION UINT32_C(0xa)
		/* RSSv2 Configuration. */
		#define HWRM_STRUCT_HDR_STRUCT_ID_RSS_V2 UINT32_C(0x64)
		uint16_t len;
		/* This value indicates the length of structured data. */
		uint8_t version;
		/* This value indicates the version of structured data. */
		uint8_t count;
		/* This value indicates the number of structured data elements. */
		uint16_t subtype;
		/* This value indicates the subtype. */
		uint16_t next_offset;
		/*
		* This value indicates the count of 64-bit values that point to the
		* next header. A value of 0 means that this is the last element. The
		* value is a count of 64-bit words from the beginning of the current
		* header.
		*/
		/* This value indicates this is the last element */
		#define HWRM_STRUCT_HDR_NEXT_OFFSET_LAST UINT32_C(0x0)
		uint16_t unused_0[3];
		} __attribute__((packed));

		/* DCBX ETS configuration structure (1053) (32 bytes) */

		struct hwrm_struct_data_dcbx_ets {
		uint8_t destination;
		/*
		* This field indicates if this configuration is ETS recommendation or
		* ETS configuration. A value 1 means it is ETS configuration, A value
		* of 2 means it is a ETS recommendation.
		*/
		/* ETS configuration */
		#define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_CONFIGURATION UINT32_C(0x1)
		/* ETS recommendation */
		#define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION UINT32_C(0x2)
		uint8_t max_tcs;
		/* This value indicates maximum ETS TCs supported. */
		uint16_t unused_0;
		/* unused. */
		uint8_t pri0_to_tc_map;
		/* ETS priority 0 to TC map. */
		uint8_t pri1_to_tc_map;
		/* ETS priority 1 to TC map. */
		uint8_t pri2_to_tc_map;
		/* ETS priority 2 to TC map. */
		uint8_t pri3_to_tc_map;
		/* ETS priority 3 to TC map. */
		uint8_t pri4_to_tc_map;
		/* ETS priority 4 to TC map. */
		uint8_t pri5_to_tc_map;
		/* ETS priority 5 to TC map. */
		uint8_t pri6_to_tc_map;
		/* ETS priority 6 to TC map. */
		uint8_t pri7_to_tc_map;
		/* ETS priority 7 to TC map. */
		uint8_t tc0_to_bw_map;
		/* ETS TC 0 to bandwidth map. */
		uint8_t tc1_to_bw_map;
		/* ETS TC 1 to bandwidth map. */
		uint8_t tc2_to_bw_map;
		/* ETS TC 2 to bandwidth map. */
		uint8_t tc3_to_bw_map;
		/* ETS TC 3 to bandwidth map. */
		uint8_t tc4_to_bw_map;
		/* ETS TC 4 to bandwidth map. */
		uint8_t tc5_to_bw_map;
		/* ETS TC 5 to bandwidth map. */
		uint8_t tc6_to_bw_map;
		/* ETS TC 6 to bandwidth map. */
		uint8_t tc7_to_bw_map;
		/* ETS TC 7 to bandwidth map. */
		uint8_t tc0_to_tsa_map;
		/* ETS TC 0 to TSA map. */
		/* strict priority */
		#define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_SP UINT32_C(0x0)
		/* credit based shaper */
		#define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_CBS UINT32_C(0x1)
		/* ETS */
		#define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_ETS UINT32_C(0x2)
		/* vendor specific */
		#define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC UINT32_C(0xff)
		uint8_t tc1_to_tsa_map;
		/* ETS TC 1 to TSA map. */
		uint8_t tc2_to_tsa_map;
		/* ETS TC 2 to TSA map. */
		uint8_t tc3_to_tsa_map;
		/* ETS TC 3 to TSA map. */
		uint8_t tc4_to_tsa_map;
		/* ETS TC 4 to TSA map. */
		uint8_t tc5_to_tsa_map;
		/* ETS TC 5 to TSA map. */
		uint8_t tc6_to_tsa_map;
		/* ETS TC 6 to TSA map. */
		uint8_t tc7_to_tsa_map;
		/* ETS TC 7 to TSA map. */
		uint32_t unused_1;
		} __attribute__((packed));

		/* DCBX PFC configuration structure (1055) (8 bytes) */

		struct hwrm_struct_data_dcbx_pfc {
		uint8_t pfc_priority_bitmap;
		/*
		* This field indicates PFC priority bit map. A value of '0' indicates
		* PFC is disabled. A value of '1' indicates PFC is enabled on that
		* priority.
		*/
		uint8_t max_pfc_tcs;
		/*
		* This field indicates max PFC TCs supported. Each PFC TC will map to a
		* lossless CoS queue.
		*/
		uint8_t mbc;
		/*
		* This field indicates if MACSec bypass capability is enabled. A value
		* of '1' indicates MBC is enabled. A value of '0' indicates MBC is
		* disabled.
		*/
		uint8_t unused_0[5];
		} __attribute__((packed));

		/* DCBX Application configuration structure (1057) (8 bytes) */

		struct hwrm_struct_data_dcbx_app {
		uint16_t protocol_id; /* big endian */
		/*
		* This field indicates the protocol identifier. This should be
		* specified in big endian format.
		*/
		uint8_t protocol_selector;
		/*
		* This field indicates the protocol selector. The valid values are
		* mentioned below.
		*/
		/* ether type */
		#define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE UINT32_C(0x1)
		/* TCP port */
		#define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT UINT32_C(0x2)
		/* UDP port */
		#define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT UINT32_C(0x3)
		/* TCP & UDP port */
		#define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT UINT32_C(0x4)
		uint8_t priority;
		/* This field indicates application priority. */
		uint8_t valid;
		/* This field indicates this entry is valid. */
		uint8_t unused_0[3];
		} __attribute__((packed));

		/* DCBX feature states configuration structure (1058) (8 bytes) */

		struct hwrm_struct_data_dcbx_feature_state {
		uint8_t dcbx_mode;
		/* DCBX mode - IEEE or CEE. This is read only field. */
		/* DCBX disabled mode. */
		#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_DISABLED UINT32_C(0x0)
		/* DCBX IEEE mode. */
		#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_IEEE UINT32_C(0x1)
		/* DCBX CEE mode. */
		#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE UINT32_C(0x2)
		uint8_t ets_state;
		/* ETS TLV state. */
		uint8_t pfc_state;
		/* PFC TLV state. */
		uint8_t app_state;
		/* App TLV state. */
		/* Feature enable bit position. */
		#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ENABLE_BIT_POS UINT32_C(0x7)
		/* Feature willing bit position. */
		#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_WILLING_BIT_POS UINT32_C(0x6)
		/* Feature advertise bit position. */
		#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS UINT32_C(0x5)
		uint8_t unused_0[3];
		/* unused. */
		uint8_t resets;
		/*
		* This field is used to reset the DCBX configuration to factory
		* defaults.
		*/
		/* reset ETS configuration. */
		#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_ETS UINT32_C(0x1)
		/* reset PFC configuration. */
		#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_PFC UINT32_C(0x2)
		/* reset application configuration. */
		#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_APP UINT32_C(0x4)
		/* reset DCBX state configuration. */
		#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE UINT32_C(0x8)
		} __attribute__((packed));

		/* LLDP TLVs transmit configuration structure (1051) (8 bytes) */

		struct hwrm_struct_data_lldp {
		uint8_t admin_state;
		/* Port admin state */
		/* Disable both Tx and Rx */
		#define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_DISABLE UINT32_C(0x0)
		/* Enable Tx only */
		#define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_TX UINT32_C(0x1)
		/* Enable Rx only */
		#define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_RX UINT32_C(0x2)
		/* Enable both Tx and Rx */
		#define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE UINT32_C(0x3)
		uint8_t port_description_state;
		/* Port desciption TLV transmit state (enable(1)/disable(0)). */
		/* Disable */
		#define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_DISABLE UINT32_C(0x0)
		/* Enable */
		#define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE UINT32_C(0x1)
		uint8_t system_name_state;
		/* System name TLV transmit state (enable(1)/disable(0)). */
		/* Disable */
		#define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_DISABLE UINT32_C(0x0)
		/* Enable */
		#define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE UINT32_C(0x1)
		uint8_t system_desc_state;
		/* System desciption TLV transmit state (enable(1)/disable(0)). */
		/* Disable */
		#define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_DISABLE UINT32_C(0x0)
		/* Enable */
		#define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE UINT32_C(0x1)
		uint8_t system_cap_state;
		/* System capabilities TLV transmit state (enable(1)/disable(0)). */
		/* Disable */
		#define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_DISABLE UINT32_C(0x0)
		/* Enable */
		#define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE UINT32_C(0x1)
		uint8_t mgmt_addr_state;
		/* Management address TLV transmit state (enable(1)/disable(0)). */
		/* Disable */
		#define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_DISABLE UINT32_C(0x0)
		/* Enable */
		#define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE UINT32_C(0x1)
		uint8_t async_event_notification_state;
		/* Async event notification state (enable(1)/disable(0)). */
		/* Disable */
		#define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_DISABLE UINT32_C(0x0)
		/* Enable */
		#define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE UINT32_C(0x1)
		uint8_t unused_0;
		} __attribute__((packed));

		/* LLDP generic TLV configuration (1060) (16 bytes) */

		struct hwrm_struct_data_lldp_generic {
		uint8_t tlv_type;
		/* TLV type. */
		/* Chassis ID TLV */
		#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_CHASSIS UINT32_C(0x1)
		/* Port ID TLV */
		#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT UINT32_C(0x2)
		/* System name TLV */
		#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_NAME UINT32_C(0x3)
		/* System description TLV */
		#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_DESCRIPTION UINT32_C(0x4)
		/* Port name TLV */
		#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_NAME UINT32_C(0x5)
		/* Port description TLV */
		#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION UINT32_C(0x6)
		uint8_t subtype;
		/* TLV sub-type. */
		uint8_t length;
		/* Length. */
		uint8_t unused_0;
		/* unused. */
		uint32_t unused_1;
		uint32_t tlv_value[64];
		/* TLV value. */
		} __attribute__((packed));

		/* LLDP device TLV configuration (1062) (64 bytes) */

		struct hwrm_struct_data_lldp_device {
		uint16_t ttl;
		/* Time to Live. */
		uint8_t mgmt_addr_len;
		/* Management address length. */
		uint8_t mgmt_addr_type;
		/* Management address type. */
		uint32_t unused_0;
		uint32_t mgmt_addr[8];
		/* Management address. */
		uint32_t system_caps;
		/* System capabilities. */
		uint8_t intf_num_type;
		/* Interface number type. */
		uint8_t mgmt_addr_oid_length;
		/* Management address OID length. */
		uint8_t unused_1;
		uint8_t unused_2;
		uint32_t intf_num;
		/* Interface number. */
		uint32_t unused_3;
		uint32_t mgmt_addr_oid[32];
		/* Management address OID. */
		} __attribute__((packed));

		/* port description (10) (8 bytes) */

		struct hwrm_struct_data_port_description {
		uint8_t port_id;
		/*
		* Port #. Port number starts at 0 and anything greater than number of
		* ports minus 1 is an error.
		*/
		uint8_t unused_0[7];
		} __attribute__((packed));

		/* RSSv2 Configuration (100) (56 bytes) */

		struct hwrm_struct_data_rss_v2 {
		uint16_t flags;
		/* When this bit is '1', the hash type and hash key are included. */
		#define HWRM_STRUCT_DATA_RSS_V2_FLAGS_HASH_VALID UINT32_C(0x1)
		uint16_t rss_ctx_id;
		/* RSS Context index. */
		uint16_t num_ring_groups;
		/* Number ring group IDs. */
		uint16_t hash_type;
		/*
		* When this bit is '1', the RSS hash shall be computed over source and
		* destination IPv4 addresses of IPv4 packets.
		*/
		#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV4 UINT32_C(0x1)
		/*
		* When this bit is '1', the RSS hash shall be computed over
		* source/destination IPv4 addresses and source/destination ports of
		* TCP/IPv4 packets.
		*/
		#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
		/*
		* When this bit is '1', the RSS hash shall be computed over
		* source/destination IPv4 addresses and source/destination ports of
		* UDP/IPv4 packets.
		*/
		#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
		/*
		* When this bit is '1', the RSS hash shall be computed over source and
		* destination IPv4 addresses of IPv6 packets.
		*/
		#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV6 UINT32_C(0x8)
		/*
		* When this bit is '1', the RSS hash shall be computed over
		* source/destination IPv6 addresses and source/destination ports of
		* TCP/IPv6 packets.
		*/
		#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
		/*
		* When this bit is '1', the RSS hash shall be computed over
		* source/destination IPv6 addresses and source/destination ports of
		* UDP/IPv6 packets.
		*/
		#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
		uint32_t hash_key[10];
		/* Hash key. This field is optional. */
		uint32_t ring_group_ids[64];
		/* Hash key. This field is optional. */
		} __attribute__((packed));

	#endif /* _HSI_STRUCT_DEF_EXTERNAL_H_ */	#endif /* _HSI_STRUCT_DEF_EXTERNAL_H_ */
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