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sys/arm/include/sysreg.h
| Context not available. | |||||
| #define CP15_HSTR(rr) p15, 4, rr, c1, c1, 3 /* Hyp System Trap Register */ | #define CP15_HSTR(rr) p15, 4, rr, c1, c1, 3 /* Hyp System Trap Register */ | ||||
| #define CP15_HSCTLR(rr) p15, 4, rr, c1, c0, 0 /* Hyp System Control Register */ | #define CP15_HSCTLR(rr) p15, 4, rr, c1, c0, 0 /* Hyp System Control Register */ | ||||
| #define CP15_HDCR(rr) p15, 4, rr, c1, c1, 1 /* Hyp Debug Configuration Register */ | #define CP15_HDCR(rr) p15, 4, rr, c1, c1, 1 /* Hyp Debug Configuration Register */ | ||||
| #define CP15_VPIDR(rr) p15, 4, rr, c0, c0, 0 /* Virtualization Processor ID Register */ | |||||
| #define CP15_VMPIDR(rr) p15, 4, rr, c0, c0, 5 /* Virtualization Multiprocessor ID Register */ | |||||
mmel: Please, keep the list sorted - here and below.
And yes, the whole hyp. related block is… | |||||
| #define CP15_ID_ISAR0(rr) p15, 0, rr, c0, c2, 0 /* Instruction Set Attribute Register 0 */ | #define CP15_ID_ISAR0(rr) p15, 0, rr, c0, c2, 0 /* Instruction Set Attribute Register 0 */ | ||||
| #define CP15_ID_ISAR1(rr) p15, 0, rr, c0, c2, 1 /* Instruction Set Attribute Register 1 */ | #define CP15_ID_ISAR1(rr) p15, 0, rr, c0, c2, 1 /* Instruction Set Attribute Register 1 */ | ||||
| Context not available. | |||||
| #define CP15_TTBR1(rr) p15, 0, rr, c2, c0, 1 /* Translation Table Base Register 1 */ | #define CP15_TTBR1(rr) p15, 0, rr, c2, c0, 1 /* Translation Table Base Register 1 */ | ||||
| #define CP15_TTBCR(rr) p15, 0, rr, c2, c0, 2 /* Translation Table Base Control Register */ | #define CP15_TTBCR(rr) p15, 0, rr, c2, c0, 2 /* Translation Table Base Control Register */ | ||||
| #define CP15_HTCR(rr) p15, 4, rr, c2, c0, 2 /* Hyp Translation Control Register */ | |||||
| #define CP15_VTCR(rr) p15, 4, rr, c2, c1, 2 /* Virtualization Translation Control Register */ | |||||
| /* | /* | ||||
| * CP15 C3 registers | * CP15 C3 registers | ||||
| */ | */ | ||||
| Context not available. | |||||
| * CP15 C5 registers | * CP15 C5 registers | ||||
| */ | */ | ||||
| #define CP15_DFSR(rr) p15, 0, rr, c5, c0, 0 /* Data Fault Status Register */ | #define CP15_DFSR(rr) p15, 0, rr, c5, c0, 0 /* Data Fault Status Register */ | ||||
| #define CP15_HSR(rr) p15, 4, rr, c5, c2, 0 /* Hyp Syndrome Register */ | |||||
| #if __ARM_ARCH >= 6 | #if __ARM_ARCH >= 6 | ||||
| /* From ARMv6: */ | /* From ARMv6: */ | ||||
| Context not available. | |||||
| * CP15 C6 registers | * CP15 C6 registers | ||||
| */ | */ | ||||
| #define CP15_DFAR(rr) p15, 0, rr, c6, c0, 0 /* Data Fault Address Register */ | #define CP15_DFAR(rr) p15, 0, rr, c6, c0, 0 /* Data Fault Address Register */ | ||||
| #define CP15_HDFAR(rr) p15, 4, rr, c6, c0, 0 /* Hyp Data Fault Address Register */ | |||||
| #define CP15_HIFAR(rr) p15, 4, rr, c6, c0, 2 /* Hyp Instruction Fault Address Register */ | |||||
| #define CP15_HPFAR(rr) p15, 4, rr, c6, c0, 4 /* Hyp IPA Fault Address Register */ | |||||
| #if __ARM_ARCH >= 6 | #if __ARM_ARCH >= 6 | ||||
| /* From ARMv6k: */ | /* From ARMv6k: */ | ||||
| Context not available. | |||||
| #define CP15_TLBIMVA(rr) p15, 0, rr, c8, c7, 1 /* Invalidate unified TLB by MVA */ | #define CP15_TLBIMVA(rr) p15, 0, rr, c8, c7, 1 /* Invalidate unified TLB by MVA */ | ||||
| #define CP15_TLBIASID(rr) p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */ | #define CP15_TLBIASID(rr) p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */ | ||||
| #define CP15_TLBIALLH(rr) p15, 4, rr, c8, c7, 0 /* Invalidate Entire Hyp Unified TLB */ | |||||
| #if __ARM_ARCH >= 6 | #if __ARM_ARCH >= 6 | ||||
| /* From ARMv6: */ | /* From ARMv6: */ | ||||
| #define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */ | #define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */ | ||||
| Context not available. | |||||
| #define CP15_TPIDRURW(rr) p15, 0, rr, c13, c0, 2 /* User Read/Write Thread ID Register */ | #define CP15_TPIDRURW(rr) p15, 0, rr, c13, c0, 2 /* User Read/Write Thread ID Register */ | ||||
| #define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */ | #define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */ | ||||
| #define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */ | #define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */ | ||||
| #define CP15_HTPIDR(rr) p15, 4, rr, c13, c0, 2 /* Hyp Software Thread ID Register */ | |||||
| /* | /* | ||||
| * CP15 C14 registers | * CP15 C14 registers | ||||
| Context not available. | |||||
| #define CP15_CNTVOFF(rq, rr) p15, 4, rq, rr, c14 /* Virtual Offset Register */ | #define CP15_CNTVOFF(rq, rr) p15, 4, rq, rr, c14 /* Virtual Offset Register */ | ||||
| #define CP15_CNTHP_CVAL(rq, rr) p15, 6, rq, rr, c14 /* PL2 Physical Timer Compare Value Register */ | #define CP15_CNTHP_CVAL(rq, rr) p15, 6, rq, rr, c14 /* PL2 Physical Timer Compare Value Register */ | ||||
| #define CP15_VTTBR(rq, rr) p15, 6, rq, rr, c2 /* Virtualization Translation Table Base Register */ | |||||
| #define CP15_HTTBR(rq, rr) p15, 4, rq, rr, c2 /* Hyp Translation Table Base Register */ | |||||
| #define CP15_TTBR02(rq, rr) p15, 0, rq, rr, c2 /* Translation Table Base Register 0 */ | |||||
| #define CP15_TTBR12(rq, rr) p15, 1, rq, rr, c2 /* Translation Table Base Register 1 */ | |||||
mmelUnsubmitted Not Done Inline ActionsI'm only curious here - why a '2' suffix and do you really need LPAE version of TTBR registers? mmel: I'm only curious here - why a '2' suffix and do you really need LPAE version of TTBR registers?
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mihaiAuthorUnsubmitted Not Done Inline ActionsOn hyp-mode LPAE is the only supported page table format. mihai: On hyp-mode LPAE is the only supported page table format. | |||||
mihaiAuthorUnsubmitted Not Done Inline ActionsIt's 2 because is the 64bit version (2 registers). CP15_TTBR0/1 already exists for 32bits. I would have the same name. Please provide another naming convention if this is not ok. mihai: It's 2 because is the 64bit version (2 registers). CP15_TTBR0/1 already exists for 32bits. I… | |||||
Not Done Inline ActionsRather, I would prefer <foo>_LPAE or something like. But this is only my "soft" personal preference. mmel: Rather, I would prefer <foo>_LPAE or something like. But this is only my "soft" personal… | |||||
| #define CP15_PAR2(rq, rr) p15, 0, rq, rr, c7 /* Physical Address Register */ | |||||
| /* | /* | ||||
| * CP15 C15 registers | * CP15 C15 registers | ||||
| */ | */ | ||||
| Context not available. | |||||
Please, keep the list sorted - here and below.
And yes, the whole hyp. related block is misordered - It should be at the end of C0 section.