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head/sys/amd64/amd64/initcpu.c
| Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines | |||||
| #include <machine/specialreg.h> | #include <machine/specialreg.h> | ||||
| #include <vm/vm.h> | #include <vm/vm.h> | ||||
| #include <vm/pmap.h> | #include <vm/pmap.h> | ||||
| static int hw_instruction_sse; | static int hw_instruction_sse; | ||||
| SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, | SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, | ||||
| &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); | &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); | ||||
| static int lower_sharedpage_init; | |||||
| int hw_lower_amd64_sharedpage; | |||||
| SYSCTL_INT(_hw, OID_AUTO, lower_amd64_sharedpage, CTLFLAG_RDTUN, | |||||
| &hw_lower_amd64_sharedpage, 0, | |||||
| "Lower sharedpage to work around Ryzen issue with executing code near the top of user memory"); | |||||
| /* | /* | ||||
| * -1: automatic (default) | * -1: automatic (default) | ||||
| * 0: keep enable CLFLUSH | * 0: keep enable CLFLUSH | ||||
| * 1: force disable CLFLUSH | * 1: force disable CLFLUSH | ||||
| */ | */ | ||||
| static int hw_clflush_disable = -1; | static int hw_clflush_disable = -1; | ||||
| static void | static void | ||||
| ▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines | init_amd(void) | ||||
| * See Revision Guide for AMD Family 16h Models 00h-0Fh Processors, | * See Revision Guide for AMD Family 16h Models 00h-0Fh Processors, | ||||
| * revision 3.04 or later, publication 51810. | * revision 3.04 or later, publication 51810. | ||||
| */ | */ | ||||
| if (CPUID_TO_FAMILY(cpu_id) == 0x16 && CPUID_TO_MODEL(cpu_id) <= 0xf) { | if (CPUID_TO_FAMILY(cpu_id) == 0x16 && CPUID_TO_MODEL(cpu_id) <= 0xf) { | ||||
| if ((cpu_feature2 & CPUID2_HV) == 0) { | if ((cpu_feature2 & CPUID2_HV) == 0) { | ||||
| msr = rdmsr(0xc0011020); | msr = rdmsr(0xc0011020); | ||||
| msr |= (uint64_t)1 << 15; | msr |= (uint64_t)1 << 15; | ||||
| wrmsr(0xc0011020, msr); | wrmsr(0xc0011020, msr); | ||||
| } | |||||
| } | |||||
| /* | |||||
| * Work around a problem on Ryzen that is triggered by executing | |||||
| * code near the top of user memory, in our case the signal | |||||
| * trampoline code in the shared page on amd64. | |||||
| * | |||||
| * This function is executed once for the BSP before tunables take | |||||
| * effect so the value determined here can be overridden by the | |||||
| * tunable. This function is then executed again for each AP and | |||||
| * also on resume. Set a flag the first time so that value set by | |||||
| * the tunable is not overwritten. | |||||
| * | |||||
| * The stepping and/or microcode versions should be checked after | |||||
| * this issue is fixed by AMD so that we don't use this mode if not | |||||
| * needed. | |||||
| */ | |||||
| if (lower_sharedpage_init == 0) { | |||||
| lower_sharedpage_init = 1; | |||||
| if (CPUID_TO_FAMILY(cpu_id) == 0x17) { | |||||
| hw_lower_amd64_sharedpage = 1; | |||||
| } | } | ||||
| } | } | ||||
| } | } | ||||
| /* | /* | ||||
| * Initialize special VIA features | * Initialize special VIA features | ||||
| */ | */ | ||||
| static void | static void | ||||
| ▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines | |||||