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Differential D11727 Diff 31200 sys/dev/ixgbe/ixgbe_common.c

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sys/dev/ixgbe/ixgbe_common.c

Show First 20 Lines • Show All 216 Lines • ▼ Show 20 Linesbool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
default: default:
break; break;
} }
if (!supported) if (!supported)
ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
"Device %x does not support flow control autoneg", "Device %x does not support flow control autoneg",
hw->device_id); hw->device_id);
return supported; return supported;
} }
/** /**
* ixgbe_setup_fc_generic - Set up flow control * ixgbe_setup_fc_generic - Set up flow control
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* *
* Called at init time to set up flow control. * Called at init time to set up flow control.
▲ Show 20 Lines • Show All 1,762 Lines • ▼ Show 20 Lines for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
IXGBE_EEPROM_OPCODE_BITS); IXGBE_EEPROM_OPCODE_BITS);
spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
break; break;
usec_delay(5); usec_delay(5);
ixgbe_standby_eeprom(hw); ixgbe_standby_eeprom(hw);
}; }
/* /*
* On some parts, SPI write time could vary from 0-20mSec on 3.3V * On some parts, SPI write time could vary from 0-20mSec on 3.3V
* devices (and only 0-5mSec on 5V devices) * devices (and only 0-5mSec on 5V devices)
*/ */
if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
DEBUGOUT("SPI EEPROM Status error\n"); DEBUGOUT("SPI EEPROM Status error\n");
status = IXGBE_ERR_EEPROM; status = IXGBE_ERR_EEPROM;
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines for (i = 0; i < count; i++) {
ixgbe_raise_eeprom_clk(hw, &eec); ixgbe_raise_eeprom_clk(hw, &eec);
ixgbe_lower_eeprom_clk(hw, &eec); ixgbe_lower_eeprom_clk(hw, &eec);
/* /*
* Shift mask to signify next bit of data to shift in to the * Shift mask to signify next bit of data to shift in to the
* EEPROM * EEPROM
*/ */
mask = mask >> 1; mask = mask >> 1;
}; }
/* We leave the "DI" bit set to "0" when we leave this routine. */ /* We leave the "DI" bit set to "0" when we leave this routine. */
eec &= ~IXGBE_EEC_DI; eec &= ~IXGBE_EEC_DI;
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_FLUSH(hw);
} }
/** /**
▲ Show 20 Lines • Show All 1,414 Lines • ▼ Show 20 Liness32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
s32 ret_val = IXGBE_SUCCESS; s32 ret_val = IXGBE_SUCCESS;
bool locked = FALSE; bool locked = FALSE;
DEBUGFUNC("ixgbe_blink_led_stop_generic"); DEBUGFUNC("ixgbe_blink_led_stop_generic");
if (index > 3) if (index > 3)
return IXGBE_ERR_PARAM; return IXGBE_ERR_PARAM;
ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
if (ret_val != IXGBE_SUCCESS) if (ret_val != IXGBE_SUCCESS)
goto out; goto out;
autoc_reg &= ~IXGBE_AUTOC_FLU; autoc_reg &= ~IXGBE_AUTOC_FLU;
autoc_reg |= IXGBE_AUTOC_AN_RESTART; autoc_reg |= IXGBE_AUTOC_AN_RESTART;
ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Lines
/** /**
* ixgbe_insert_mac_addr_generic - Find a RAR for this mac address * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @addr: Address to put into receive address register * @addr: Address to put into receive address register
* @vmdq: VMDq pool to assign * @vmdq: VMDq pool to assign
* *
* Puts an ethernet address into a receive address register, or * Puts an ethernet address into a receive address register, or
* finds the rar that it is aleady in; adds to the pool list * finds the rar that it is already in; adds to the pool list
**/ **/
s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
{ {
static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
u32 first_empty_rar = NO_EMPTY_RAR_FOUND; u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
u32 rar; u32 rar;
u32 rar_low, rar_high; u32 rar_low, rar_high;
u32 addr_low, addr_high; u32 addr_low, addr_high;
▲ Show 20 Lines • Show All 394 Lines • ▼ Show 20 Liness32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
DEBUGFUNC("ixgbe_clear_vfta_generic"); DEBUGFUNC("ixgbe_clear_vfta_generic");
for (offset = 0; offset < hw->mac.vft_size; offset++) for (offset = 0; offset < hw->mac.vft_size; offset++)
IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
} }
return IXGBE_SUCCESS; return IXGBE_SUCCESS;
} }
/** /**
* ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
▲ Show 20 Lines • Show All 1,247 Lines • Show Last 20 Lines