Differential D11546 Diff 30647 head/sys/arm/ti/omap4/omap4_l2cache.c

Changeset View

Standalone View

head/sys/arm/ti/omap4/omap4_l2cache.c

Show All 26 Lines
#include <sys/types.h>		#include <sys/types.h>
#include <sys/param.h>		#include <sys/param.h>
#include <sys/systm.h>		#include <sys/systm.h>
#include <sys/bus.h>		#include <sys/bus.h>
#include <sys/rman.h>		#include <sys/rman.h>
#include <sys/lock.h>		#include <sys/lock.h>
#include <sys/mutex.h>		#include <sys/mutex.h>

#include <arm/ti/ti_smc.h>
#include <arm/ti/omap4/omap4_smc.h>
#include <machine/bus.h>		#include <machine/bus.h>
#include <machine/pl310.h>		#include <machine/pl310.h>
		#include <machine/platformvar.h>

		#include <arm/ti/ti_smc.h>
		#include <arm/ti/omap4/omap4_machdep.h>
		#include <arm/ti/omap4/omap4_smc.h>

		#include "platform_pl310_if.h"

void		void
platform_pl310_init(struct pl310_softc *sc)		omap4_pl310_init(platform_t plat, struct pl310_softc *sc)
{		{
uint32_t aux, prefetch;		uint32_t aux, prefetch;

aux = pl310_read4(sc, PL310_AUX_CTRL);		aux = pl310_read4(sc, PL310_AUX_CTRL);
prefetch = pl310_read4(sc, PL310_PREFETCH_CTRL);		prefetch = pl310_read4(sc, PL310_PREFETCH_CTRL);

/*		/*
* Disable instruction prefetch		* Disable instruction prefetch
Show All 15 Lines	omap4_pl310_init(platform_t plat, struct pl310_softc *sc)
* and experiment with performance		* and experiment with performance
*/		*/

ti_smc0(aux, 0, WRITE_AUXCTRL_REG);		ti_smc0(aux, 0, WRITE_AUXCTRL_REG);
ti_smc0(prefetch, 0, WRITE_PREFETCH_CTRL_REG);		ti_smc0(prefetch, 0, WRITE_PREFETCH_CTRL_REG);
}		}

void		void
platform_pl310_write_ctrl(struct pl310_softc *sc, uint32_t val)		omap4_pl310_write_ctrl(platform_t plat, struct pl310_softc *sc, uint32_t val)
{		{

ti_smc0(val, 0, L2CACHE_WRITE_CTRL_REG);		ti_smc0(val, 0, L2CACHE_WRITE_CTRL_REG);
}		}

void		void
platform_pl310_write_debug(struct pl310_softc *sc, uint32_t val)		omap4_pl310_write_debug(platform_t plat, struct pl310_softc *sc, uint32_t val)
{		{

ti_smc0(val, 0, L2CACHE_WRITE_DEBUG_REG);		ti_smc0(val, 0, L2CACHE_WRITE_DEBUG_REG);
}		}