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www/node/files/patch-deps_v8_src_arm_cpu-arm.cc
| --- deps/v8/src/arm/cpu-arm.cc.orig 2016-10-19 22:02:03 UTC | --- deps/v8/src/arm/cpu-arm.cc.orig 2017-06-15 11:55:20 UTC | ||||
| +++ deps/v8/src/arm/cpu-arm.cc | +++ deps/v8/src/arm/cpu-arm.cc | ||||
| @@ -7,6 +7,9 @@ | @@ -7,6 +7,9 @@ | ||||
| #ifdef __QNXNTO__ | #ifdef __QNXNTO__ | ||||
| #include <sys/mman.h> // for cache flushing. | #include <sys/mman.h> // for cache flushing. | ||||
| #undef MAP_TYPE | #undef MAP_TYPE | ||||
| +#elif defined(__FreeBSD__) | +#elif defined(__FreeBSD__) | ||||
| +#include <sys/types.h> | +#include <sys/types.h> | ||||
| +#include <machine/sysarch.h> // for cache flushing. | +#include <machine/sysarch.h> // for cache flushing. | ||||
| #else | #else | ||||
| #include <sys/syscall.h> // for cache flushing. | #include <sys/syscall.h> // for cache flushing. | ||||
| #endif | #endif | ||||
| @@ -24,6 +27,9 @@ void CpuFeatures::FlushICache(void* star | @@ -24,6 +27,9 @@ void CpuFeatures::FlushICache(void* start, size_t size | ||||
| #if !defined(USE_SIMULATOR) | #if !defined(USE_SIMULATOR) | ||||
| #if V8_OS_QNX | #if V8_OS_QNX | ||||
| msync(start, size, MS_SYNC | MS_INVALIDATE_ICACHE); | msync(start, size, MS_SYNC | MS_INVALIDATE_ICACHE); | ||||
| +#elif defined(__FreeBSD__) | +#elif defined(__FreeBSD__) | ||||
| + struct arm_sync_icache_args args = { .addr = (uintptr_t)start, .len = size }; | + struct arm_sync_icache_args args = { .addr = (uintptr_t)start, .len = size }; | ||||
| + sysarch(ARM_SYNC_ICACHE, (void *)&args); | + sysarch(ARM_SYNC_ICACHE, (void *)&args); | ||||
| #else | #else | ||||
| register uint32_t beg asm("r0") = reinterpret_cast<uint32_t>(start); | register uint32_t beg asm("r0") = reinterpret_cast<uint32_t>(start); | ||||
| register uint32_t end asm("r1") = beg + size; | register uint32_t end asm("r1") = beg + size; | ||||