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sys/dev/ixgbe/ixgbe_phy.h
| /****************************************************************************** | /****************************************************************************** | ||||
| Copyright (c) 2001-2015, Intel Corporation | Copyright (c) 2001-2017, Intel Corporation | ||||
| All rights reserved. | All rights reserved. | ||||
| Redistribution and use in source and binary forms, with or without | Redistribution and use in source and binary forms, with or without | ||||
| modification, are permitted provided that the following conditions are met: | modification, are permitted provided that the following conditions are met: | ||||
| 1. Redistributions of source code must retain the above copyright notice, | 1. Redistributions of source code must retain the above copyright notice, | ||||
| this list of conditions and the following disclaimer. | this list of conditions and the following disclaimer. | ||||
| 2. Redistributions in binary form must reproduce the above copyright | 2. Redistributions in binary form must reproduce the above copyright | ||||
| notice, this list of conditions and the following disclaimer in the | notice, this list of conditions and the following disclaimer in the | ||||
| documentation and/or other materials provided with the distribution. | documentation and/or other materials provided with the distribution. | ||||
| 3. Neither the name of the Intel Corporation nor the names of its | 3. Neither the name of the Intel Corporation nor the names of its | ||||
| contributors may be used to endorse or promote products derived from | contributors may be used to endorse or promote products derived from | ||||
| this software without specific prior written permission. | this software without specific prior written permission. | ||||
| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||||
| AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||||
| IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||||
| ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | ||||
| LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||||
| CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||||
| SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | ||||
| INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | ||||
| CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | ||||
| ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ||||
| POSSIBILITY OF SUCH DAMAGE. | POSSIBILITY OF SUCH DAMAGE. | ||||
| ******************************************************************************/ | ******************************************************************************/ | ||||
| /*$FreeBSD$*/ | /*$FreeBSD$*/ | ||||
| #ifndef _IXGBE_PHY_H_ | #ifndef _IXGBE_PHY_H_ | ||||
| #define _IXGBE_PHY_H_ | #define _IXGBE_PHY_H_ | ||||
| ▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines | |||||
| #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 | #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 | ||||
| #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 | #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 | ||||
| #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 | #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 | ||||
| #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 | #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 | ||||
| #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 | #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 | ||||
| #define IXGBE_CS4227 0xBE /* CS4227 address */ | #define IXGBE_CS4227 0xBE /* CS4227 address */ | ||||
| #define IXGBE_CS4227_GLOBAL_ID_LSB 0 | #define IXGBE_CS4227_GLOBAL_ID_LSB 0 | ||||
| #define IXGBE_CS4227_GLOBAL_ID_MSB 1 | |||||
| #define IXGBE_CS4227_SCRATCH 2 | #define IXGBE_CS4227_SCRATCH 2 | ||||
| #define IXGBE_CS4227_GLOBAL_ID_VALUE 0x03E5 | #define IXGBE_CS4227_GLOBAL_ID_VALUE 0x03E5 | ||||
| #define IXGBE_CS4227_EFUSE_PDF_SKU 0x19F | |||||
| #define IXGBE_CS4223_SKU_ID 0x0010 /* Quad port */ | |||||
| #define IXGBE_CS4227_SKU_ID 0x0014 /* Dual port */ | |||||
| #define IXGBE_CS4227_RESET_PENDING 0x1357 | #define IXGBE_CS4227_RESET_PENDING 0x1357 | ||||
| #define IXGBE_CS4227_RESET_COMPLETE 0x5AA5 | #define IXGBE_CS4227_RESET_COMPLETE 0x5AA5 | ||||
| #define IXGBE_CS4227_RETRIES 15 | #define IXGBE_CS4227_RETRIES 15 | ||||
| #define IXGBE_CS4227_EFUSE_STATUS 0x0181 | #define IXGBE_CS4227_EFUSE_STATUS 0x0181 | ||||
| #define IXGBE_CS4227_LINE_SPARE22_MSB 0x12AD /* Reg to program speed */ | #define IXGBE_CS4227_LINE_SPARE22_MSB 0x12AD /* Reg to program speed */ | ||||
| #define IXGBE_CS4227_LINE_SPARE24_LSB 0x12B0 /* Reg to program EDC */ | #define IXGBE_CS4227_LINE_SPARE24_LSB 0x12B0 /* Reg to program EDC */ | ||||
| #define IXGBE_CS4227_HOST_SPARE22_MSB 0x1AAD /* Reg to program speed */ | #define IXGBE_CS4227_HOST_SPARE22_MSB 0x1AAD /* Reg to program speed */ | ||||
| #define IXGBE_CS4227_HOST_SPARE24_LSB 0x1AB0 /* Reg to program EDC */ | #define IXGBE_CS4227_HOST_SPARE24_LSB 0x1AB0 /* Reg to program EDC */ | ||||
| ▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines | s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, | ||||
| u16 *firmware_version); | u16 *firmware_version); | ||||
| s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, | s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, | ||||
| u16 *firmware_version); | u16 *firmware_version); | ||||
| s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); | s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); | ||||
| s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on); | s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on); | ||||
| s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw); | s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw); | ||||
| s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); | s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); | ||||
| s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw); | u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw); | ||||
| s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw); | s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw); | ||||
| s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, | s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, | ||||
| u16 *list_offset, | u16 *list_offset, | ||||
| u16 *data_offset); | u16 *data_offset); | ||||
| s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); | s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); | ||||
| s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, | s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, | ||||
| u8 dev_addr, u8 *data); | u8 dev_addr, u8 *data); | ||||
| s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, | s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, | ||||
| u8 dev_addr, u8 *data); | u8 dev_addr, u8 *data); | ||||
| s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, | s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, | ||||
| u8 dev_addr, u8 data); | u8 dev_addr, u8 data); | ||||
| s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, | s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, | ||||
| u8 dev_addr, u8 data); | u8 dev_addr, u8 data); | ||||
| s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, | s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, | ||||
| u8 *eeprom_data); | u8 *eeprom_data); | ||||
| s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, | s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, | ||||
| u8 eeprom_data); | u8 eeprom_data); | ||||
| void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); | void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); | ||||
| s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg, | |||||
| u16 *val, bool lock); | |||||
| s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg, | |||||
| u16 val, bool lock); | |||||
| #endif /* _IXGBE_PHY_H_ */ | #endif /* _IXGBE_PHY_H_ */ | ||||