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sys/arm/mv/mv_common.c
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static void decode_win_eth_dump(u_long base); | static void decode_win_eth_dump(u_long base); | ||||
static void decode_win_neta_dump(u_long base); | static void decode_win_neta_dump(u_long base); | ||||
static void decode_win_idma_dump(u_long base); | static void decode_win_idma_dump(u_long base); | ||||
static void decode_win_xor_dump(u_long base); | static void decode_win_xor_dump(u_long base); | ||||
static void decode_win_ahci_dump(u_long base); | static void decode_win_ahci_dump(u_long base); | ||||
static void decode_win_sdhci_dump(u_long); | static void decode_win_sdhci_dump(u_long); | ||||
static void decode_win_pcie_dump(u_long); | static void decode_win_pcie_dump(u_long); | ||||
static void l2cache_drainwb_coherent(void); | |||||
static int fdt_get_ranges(const char *, void *, int, int *, int *); | static int fdt_get_ranges(const char *, void *, int, int *, int *); | ||||
#ifdef SOC_MV_ARMADA38X | #ifdef SOC_MV_ARMADA38X | ||||
int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, | int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, | ||||
int *trig, int *pol); | int *trig, int *pol); | ||||
#endif | #endif | ||||
static int win_cpu_from_dt(void); | static int win_cpu_from_dt(void); | ||||
static int fdt_win_setup(void); | static int fdt_win_setup(void); | ||||
static uint32_t dev_mask = 0; | static uint32_t dev_mask = 0; | ||||
static int cpu_wins_no = 0; | static int cpu_wins_no = 0; | ||||
static int eth_port = 0; | static int eth_port = 0; | ||||
static int usb_port = 0; | static int usb_port = 0; | ||||
static boolean_t plat_dma_coherent = false; | |||||
static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; | static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; | ||||
const struct decode_win *cpu_wins = cpu_win_tbl; | const struct decode_win *cpu_wins = cpu_win_tbl; | ||||
typedef void (*decode_win_setup_t)(u_long); | typedef void (*decode_win_setup_t)(u_long); | ||||
typedef void (*dump_win_t)(u_long); | typedef void (*dump_win_t)(u_long); | ||||
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{ | { | ||||
if (boothowto & RB_KDB) | if (boothowto & RB_KDB) | ||||
kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); | kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); | ||||
} | } | ||||
SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); | SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); | ||||
#endif | #endif | ||||
static void l2cache_drainwb_coherent(void) | |||||
{ | |||||
/* No-op for coherent platforms */ | |||||
} | |||||
int | int | ||||
soc_decode_win(void) | soc_decode_win(void) | ||||
{ | { | ||||
uint32_t dev, rev; | uint32_t dev, rev; | ||||
int mask, err; | int mask, err; | ||||
phandle_t node; | |||||
mask = 0; | mask = 0; | ||||
TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); | TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); | ||||
if (mask != 0) | if (mask != 0) | ||||
pm_disable_device(mask); | pm_disable_device(mask); | ||||
/* Retrieve data about physical addresses from device tree. */ | /* Retrieve data about physical addresses from device tree. */ | ||||
if ((err = win_cpu_from_dt()) != 0) | if ((err = win_cpu_from_dt()) != 0) | ||||
return (err); | return (err); | ||||
/* Retrieve our ID: some windows facilities vary between SoC models */ | /* Retrieve our ID: some windows facilities vary between SoC models */ | ||||
soc_id(&dev, &rev); | soc_id(&dev, &rev); | ||||
/* Retrieve information about DMA coherency from device tree */ | |||||
node = OF_finddevice("/soc"); | |||||
if ((node > 0) && OF_hasprop(node, "dma-coherent")) { | |||||
plat_dma_coherent = true; | |||||
cpufuncs.cf_l2cache_drain_writebuf = l2cache_drainwb_coherent; | |||||
} | |||||
#ifdef SOC_MV_ARMADAXP | #ifdef SOC_MV_ARMADAXP | ||||
if ((err = decode_win_sdram_fixup()) != 0) | if ((err = decode_win_sdram_fixup()) != 0) | ||||
return(err); | return(err); | ||||
#endif | #endif | ||||
if (!decode_win_cpu_valid() || !decode_win_usb_valid() || | if (!decode_win_cpu_valid() || !decode_win_usb_valid() || | ||||
!decode_win_eth_valid() || !decode_win_idma_valid() || | !decode_win_eth_valid() || !decode_win_idma_valid() || | ||||
!decode_win_pcie_valid() || !decode_win_sata_valid() || | !decode_win_pcie_valid() || !decode_win_sata_valid() || | ||||
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{ | { | ||||
return ((ddr_sz_read(i) | 0x00ffffff) + 1); | return ((ddr_sz_read(i) | 0x00ffffff) + 1); | ||||
} | } | ||||
uint32_t | uint32_t | ||||
ddr_attr(int i) | ddr_attr(int i) | ||||
{ | { | ||||
uint32_t dev, rev; | uint32_t dev, rev, attr; | ||||
soc_id(&dev, &rev); | soc_id(&dev, &rev); | ||||
if (dev == MV_DEV_88RC8180) | if (dev == MV_DEV_88RC8180) | ||||
return ((ddr_sz_read(i) & 0xf0) >> 4); | return ((ddr_sz_read(i) & 0xf0) >> 4); | ||||
if (dev == MV_DEV_88F6781) | if (dev == MV_DEV_88F6781) | ||||
return (0); | return (0); | ||||
return (i == 0 ? 0xe : | attr = (i == 0 ? 0xe : | ||||
(i == 1 ? 0xd : | (i == 1 ? 0xd : | ||||
(i == 2 ? 0xb : | (i == 2 ? 0xb : | ||||
(i == 3 ? 0x7 : 0xff)))); | (i == 3 ? 0x7 : 0xff)))); | ||||
if (plat_dma_coherent) | |||||
attr |= 0x10; | |||||
return (attr); | |||||
} | } | ||||
uint32_t | uint32_t | ||||
ddr_target(int i) | ddr_target(int i) | ||||
{ | { | ||||
uint32_t dev, rev; | uint32_t dev, rev; | ||||
soc_id(&dev, &rev); | soc_id(&dev, &rev); | ||||
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