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head/sys/arm/mv/mpic.c
Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines | |||||
#include <sys/cpuset.h> | #include <sys/cpuset.h> | ||||
#include <sys/ktr.h> | #include <sys/ktr.h> | ||||
#include <sys/kdb.h> | #include <sys/kdb.h> | ||||
#include <sys/module.h> | #include <sys/module.h> | ||||
#include <sys/lock.h> | #include <sys/lock.h> | ||||
#include <sys/mutex.h> | #include <sys/mutex.h> | ||||
#include <sys/rman.h> | #include <sys/rman.h> | ||||
#include <sys/proc.h> | #include <sys/proc.h> | ||||
#include <sys/smp.h> | |||||
#include <machine/bus.h> | #include <machine/bus.h> | ||||
#include <machine/intr.h> | #include <machine/intr.h> | ||||
#include <machine/smp.h> | #include <machine/smp.h> | ||||
#include <arm/mv/mvvar.h> | #include <arm/mv/mvvar.h> | ||||
#include <arm/mv/mvreg.h> | #include <arm/mv/mvreg.h> | ||||
#include <dev/ofw/ofw_bus.h> | #include <dev/ofw/ofw_bus.h> | ||||
#include <dev/ofw/ofw_bus_subr.h> | #include <dev/ofw/ofw_bus_subr.h> | ||||
#include <dev/fdt/fdt_common.h> | #include <dev/fdt/fdt_common.h> | ||||
#ifdef INTRNG | #ifdef INTRNG | ||||
#include "pic_if.h" | #include "pic_if.h" | ||||
#endif | #endif | ||||
#ifdef DEBUG | #ifdef DEBUG | ||||
#define debugf(fmt, args...) do { printf("%s(): ", __func__); \ | #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ | ||||
printf(fmt,##args); } while (0) | printf(fmt,##args); } while (0) | ||||
#else | #else | ||||
#define debugf(fmt, args...) | #define debugf(fmt, args...) | ||||
#endif | #endif | ||||
#define MPIC_INT_LOCAL 3 | |||||
#define MPIC_INT_ERR 4 | #define MPIC_INT_ERR 4 | ||||
#define MPIC_INT_MSI 96 | #define MPIC_INT_MSI 96 | ||||
#define MPIC_IRQ_MASK 0x3ff | #define MPIC_IRQ_MASK 0x3ff | ||||
#define MPIC_CTRL 0x0 | #define MPIC_CTRL 0x0 | ||||
#define MPIC_SOFT_INT 0x4 | #define MPIC_SOFT_INT 0x4 | ||||
#define MPIC_SOFT_INT_DRBL1 (1 << 5) | #define MPIC_SOFT_INT_DRBL1 (1 << 5) | ||||
#define MPIC_ERR_CAUSE 0x20 | #define MPIC_ERR_CAUSE 0x20 | ||||
#define MPIC_ISE 0x30 | #define MPIC_ISE 0x30 | ||||
#define MPIC_ICE 0x34 | #define MPIC_ICE 0x34 | ||||
#define MPIC_INT_CTL(irq) (0x100 + (irq)*4) | #define MPIC_INT_CTL(irq) (0x100 + (irq)*4) | ||||
#define MPIC_INT_IRQ_FIQ_MASK(cpuid) (0x101 << (cpuid)) | #define MPIC_INT_IRQ_FIQ_MASK(cpuid) (0x101 << (cpuid)) | ||||
#define MPIC_CTRL_NIRQS(ctrl) (((ctrl) >> 2) & 0x3ff) | #define MPIC_CTRL_NIRQS(ctrl) (((ctrl) >> 2) & 0x3ff) | ||||
#define MPIC_IN_DRBL 0x08 | #define MPIC_IN_DRBL 0x08 | ||||
#define MPIC_IN_DRBL_MASK 0x0c | #define MPIC_IN_DRBL_MASK 0x0c | ||||
#define MPIC_PPI_CAUSE 0x10 | #define MPIC_PPI_CAUSE 0x10 | ||||
#define MPIC_CTP 0x40 | #define MPIC_CTP 0x40 | ||||
#define MPIC_IIACK 0x44 | #define MPIC_IIACK 0x44 | ||||
#define MPIC_ISM 0x48 | #define MPIC_ISM 0x48 | ||||
#define MPIC_ICM 0x4c | #define MPIC_ICM 0x4c | ||||
#define MPIC_ERR_MASK 0xe50 | #define MPIC_ERR_MASK 0x50 | ||||
#define MPIC_LOCAL_MASK 0x54 | |||||
#define MPIC_CPU(n) (n) * 0x100 | |||||
#define MPIC_PPI 32 | #define MPIC_PPI 32 | ||||
#ifdef INTRNG | #ifdef INTRNG | ||||
struct mv_mpic_irqsrc { | struct mv_mpic_irqsrc { | ||||
struct intr_irqsrc mmi_isrc; | struct intr_irqsrc mmi_isrc; | ||||
u_int mmi_irq; | u_int mmi_irq; | ||||
}; | }; | ||||
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines | |||||
#endif | #endif | ||||
static int | static int | ||||
mv_mpic_attach(device_t dev) | mv_mpic_attach(device_t dev) | ||||
{ | { | ||||
struct mv_mpic_softc *sc; | struct mv_mpic_softc *sc; | ||||
int error; | int error; | ||||
uint32_t val; | uint32_t val; | ||||
int cpu; | |||||
sc = (struct mv_mpic_softc *)device_get_softc(dev); | sc = (struct mv_mpic_softc *)device_get_softc(dev); | ||||
if (mv_mpic_sc != NULL) | if (mv_mpic_sc != NULL) | ||||
return (ENXIO); | return (ENXIO); | ||||
mv_mpic_sc = sc; | mv_mpic_sc = sc; | ||||
sc->sc_dev = dev; | sc->sc_dev = dev; | ||||
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines | if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) { | ||||
device_printf(dev, "could not register PIC\n"); | device_printf(dev, "could not register PIC\n"); | ||||
bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); | bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); | ||||
return (ENXIO); | return (ENXIO); | ||||
} | } | ||||
#endif | #endif | ||||
mpic_unmask_msi(); | mpic_unmask_msi(); | ||||
/* Unmask CPU performance counters overflow irq */ | |||||
for (cpu = 0; cpu < mp_ncpus; cpu++) | |||||
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CPU(cpu) + MPIC_LOCAL_MASK, | |||||
(1 << cpu) | MPIC_CPU_READ(mv_mpic_sc, | |||||
MPIC_CPU(cpu) + MPIC_LOCAL_MASK)); | |||||
return (0); | return (0); | ||||
} | } | ||||
#ifdef INTRNG | #ifdef INTRNG | ||||
static int | static int | ||||
mpic_intr(void *arg) | mpic_intr(void *arg) | ||||
{ | { | ||||
struct mv_mpic_softc *sc; | struct mv_mpic_softc *sc; | ||||
▲ Show 20 Lines • Show All 189 Lines • ▼ Show 20 Lines | mpic_irq_is_percpu(uintptr_t nb) | ||||
return FALSE; | return FALSE; | ||||
} | } | ||||
static void | static void | ||||
mpic_unmask_irq(uintptr_t nb) | mpic_unmask_irq(uintptr_t nb) | ||||
{ | { | ||||
#ifdef SMP | |||||
int cpu; | |||||
if (nb == MPIC_INT_LOCAL) { | |||||
for (cpu = 0; cpu < mp_ncpus; cpu++) | |||||
MPIC_CPU_WRITE(mv_mpic_sc, | |||||
MPIC_CPU(cpu) + MPIC_ICM, nb); | |||||
return; | |||||
} | |||||
#endif | |||||
if (mpic_irq_is_percpu(nb)) | if (mpic_irq_is_percpu(nb)) | ||||
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); | MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); | ||||
else if (nb < ERR_IRQ) | else if (nb < ERR_IRQ) | ||||
MPIC_WRITE(mv_mpic_sc, MPIC_ISE, nb); | MPIC_WRITE(mv_mpic_sc, MPIC_ISE, nb); | ||||
else if (nb < MSI_IRQ) | else if (nb < MSI_IRQ) | ||||
mpic_unmask_irq_err(nb); | mpic_unmask_irq_err(nb); | ||||
if (nb == 0) | if (nb == 0) | ||||
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff); | MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff); | ||||
} | } | ||||
static void | static void | ||||
mpic_mask_irq(uintptr_t nb) | mpic_mask_irq(uintptr_t nb) | ||||
{ | { | ||||
#ifdef SMP | |||||
int cpu; | |||||
if (nb == MPIC_INT_LOCAL) { | |||||
for (cpu = 0; cpu < mp_ncpus; cpu++) | |||||
MPIC_CPU_WRITE(mv_mpic_sc, | |||||
MPIC_CPU(cpu) + MPIC_ISM, nb); | |||||
return; | |||||
} | |||||
#endif | |||||
if (mpic_irq_is_percpu(nb)) | if (mpic_irq_is_percpu(nb)) | ||||
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); | MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); | ||||
else if (nb < ERR_IRQ) | else if (nb < ERR_IRQ) | ||||
MPIC_WRITE(mv_mpic_sc, MPIC_ICE, nb); | MPIC_WRITE(mv_mpic_sc, MPIC_ICE, nb); | ||||
else if (nb < MSI_IRQ) | else if (nb < MSI_IRQ) | ||||
mpic_mask_irq_err(nb); | mpic_mask_irq_err(nb); | ||||
} | } | ||||
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