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sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
| Show First 20 Lines • Show All 368 Lines • ▼ Show 20 Lines | bhnd_pwrctl_slowclk_freq(struct bhnd_pwrctl_softc *sc, bool max_freq) | ||||
| if (PWRCTL_QUIRK(sc, PCICLK_CTL)) { | if (PWRCTL_QUIRK(sc, PCICLK_CTL)) { | ||||
| if (slowclk == BHND_CLKSRC_PCI) | if (slowclk == BHND_CLKSRC_PCI) | ||||
| div = 64; | div = 64; | ||||
| else | else | ||||
| div = 32; | div = 32; | ||||
| } else if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) { | } else if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) { | ||||
| div = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL); | div = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL); | ||||
| div = CHIPC_GET_BITS(div, CHIPC_SCC_CD); | div = CHIPC_GET_BITS(div, CHIPC_SCC_CD); | ||||
| div *= 4; | div = 4 * (div + 1); | ||||
| } else if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) { | } else if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) { | ||||
| if (max_freq) { | if (max_freq) { | ||||
| div = 1; | div = 1; | ||||
| } else { | } else { | ||||
| div = bhnd_bus_read_4(sc->res, CHIPC_SYS_CLK_CTL); | div = bhnd_bus_read_4(sc->res, CHIPC_SYS_CLK_CTL); | ||||
| div = CHIPC_GET_BITS(div, CHIPC_SYCC_CD); | div = CHIPC_GET_BITS(div, CHIPC_SYCC_CD); | ||||
| div = 4 * (div + 1); | div = 4 * (div + 1); | ||||
| } | } | ||||
| ▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines | bhnd_pwrctl_setclk(struct bhnd_pwrctl_softc *sc, bhnd_clock clock) | ||||
| /* Is dynamic clock control supported? */ | /* Is dynamic clock control supported? */ | ||||
| if (PWRCTL_QUIRK(sc, FIXED_CLK)) | if (PWRCTL_QUIRK(sc, FIXED_CLK)) | ||||
| return (ENODEV); | return (ENODEV); | ||||
| /* Chips with ccrev 10 are EOL and they don't have SYCC_HR used below */ | /* Chips with ccrev 10 are EOL and they don't have SYCC_HR used below */ | ||||
| if (bhnd_get_hwrev(sc->chipc_dev) == 10) | if (bhnd_get_hwrev(sc->chipc_dev) == 10) | ||||
| return (ENODEV); | return (ENODEV); | ||||
| if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) | |||||
| scc = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL); | scc = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL); | ||||
| else | |||||
| scc = bhnd_bus_read_4(sc->res, CHIPC_SYS_CLK_CTL); | |||||
| switch (clock) { | switch (clock) { | ||||
| case BHND_CLOCK_HT: | case BHND_CLOCK_HT: | ||||
| /* fast (pll) clock */ | /* fast (pll) clock */ | ||||
| if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) { | if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) { | ||||
| scc &= ~(CHIPC_SCC_XC | CHIPC_SCC_FS | CHIPC_SCC_IP); | scc &= ~(CHIPC_SCC_XC | CHIPC_SCC_FS | CHIPC_SCC_IP); | ||||
| scc |= CHIPC_SCC_IP; | scc |= CHIPC_SCC_IP; | ||||
| /* force xtal back on before clearing SCC_DYN_XTAL.. */ | /* force xtal back on before clearing SCC_DYN_XTAL.. */ | ||||
| bhnd_pwrctl_ungate_clock(sc->chipc_dev, BHND_CLOCK_HT); | bhnd_pwrctl_ungate_clock(sc->chipc_dev, BHND_CLOCK_HT); | ||||
| } else if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) { | } else if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) { | ||||
| scc |= CHIPC_SYCC_HR; | scc |= CHIPC_SYCC_HR; | ||||
| } else { | } else { | ||||
| return (ENODEV); | return (ENODEV); | ||||
| } | } | ||||
| if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) | |||||
| bhnd_bus_write_4(sc->res, CHIPC_PLL_SLOWCLK_CTL, scc); | bhnd_bus_write_4(sc->res, CHIPC_PLL_SLOWCLK_CTL, scc); | ||||
| else | |||||
| bhnd_bus_write_4(sc->res, CHIPC_SYS_CLK_CTL, scc); | |||||
| DELAY(CHIPC_PLL_DELAY); | DELAY(CHIPC_PLL_DELAY); | ||||
| break; | break; | ||||
| case BHND_CLOCK_DYN: | case BHND_CLOCK_DYN: | ||||
| /* enable dynamic clock control */ | /* enable dynamic clock control */ | ||||
| if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) { | if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) { | ||||
| scc &= ~(CHIPC_SCC_FS | CHIPC_SCC_IP | CHIPC_SCC_XC); | scc &= ~(CHIPC_SCC_FS | CHIPC_SCC_IP | CHIPC_SCC_XC); | ||||
| Show All 27 Lines | |||||