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sys/dev/bhnd/cores/chipc/chipcreg.h
| Show First 20 Lines • Show All 274 Lines • ▼ Show 20 Lines | #define CHIPC_CST_SPROM_OTP_SEL_R23_MASK 0x000000c0 /**< chipstatus OTP/SPROM SEL value (revs 23-31) | ||||
| */ | */ | ||||
| #define CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 6 | #define CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 6 | ||||
| /* PLL type */ | /* PLL type */ | ||||
| #define CHIPC_PLL_NONE 0x0 | #define CHIPC_PLL_NONE 0x0 | ||||
| #define CHIPC_PLL_TYPE1 0x2 /* 48MHz base, 3 dividers */ | #define CHIPC_PLL_TYPE1 0x2 /* 48MHz base, 3 dividers */ | ||||
| #define CHIPC_PLL_TYPE2 0x4 /* 48MHz, 4 dividers */ | #define CHIPC_PLL_TYPE2 0x4 /* 48MHz, 4 dividers */ | ||||
| #define CHIPC_PLL_TYPE3 0x6 /* 25MHz, 2 dividers */ | #define CHIPC_PLL_TYPE3 0x6 /* 25MHz, 2 dividers */ | ||||
| #define CHIPC_PLL_TYPE4 0x8 /* 48MHz, 4 dividers */ | #define CHIPC_PLL_TYPE4 0x1 /* 48MHz, 4 dividers */ | ||||
| #define CHIPC_PLL_TYPE5 0x3 /* 25MHz, 4 dividers */ | #define CHIPC_PLL_TYPE5 0x3 /* 25MHz, 4 dividers */ | ||||
| #define CHIPC_PLL_TYPE6 0x5 /* 100/200 or 120/240 only */ | #define CHIPC_PLL_TYPE6 0x5 /* 100/200 or 120/240 only */ | ||||
| #define CHIPC_PLL_TYPE7 0x7 /* 25MHz, 4 dividers */ | #define CHIPC_PLL_TYPE7 0x7 /* 25MHz, 4 dividers */ | ||||
| /* dynamic clock control defines */ | /* dynamic clock control defines */ | ||||
| #define CHIPC_LPOMINFREQ 25000 /* low power oscillator min */ | #define CHIPC_LPOMINFREQ 25000 /* low power oscillator min */ | ||||
| #define CHIPC_LPOMAXFREQ 43000 /* low power oscillator max */ | #define CHIPC_LPOMAXFREQ 43000 /* low power oscillator max */ | ||||
| #define CHIPC_XTALMINFREQ 19800000 /* 20 MHz - 1% */ | #define CHIPC_XTALMINFREQ 19800000 /* 20 MHz - 1% */ | ||||
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