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head/sys/dev/ixgbe/ixgbe_vf.c
/****************************************************************************** | /****************************************************************************** | ||||
Copyright (c) 2001-2013, Intel Corporation | Copyright (c) 2001-2014, Intel Corporation | ||||
All rights reserved. | All rights reserved. | ||||
Redistribution and use in source and binary forms, with or without | Redistribution and use in source and binary forms, with or without | ||||
Context not available. | |||||
return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
} | } | ||||
/* ixgbe_virt_clr_reg - Set register to default (power on) state. | |||||
* @hw: pointer to hardware structure | |||||
*/ | |||||
static void ixgbe_virt_clr_reg(struct ixgbe_hw *hw) | |||||
{ | |||||
int i; | |||||
u32 vfsrrctl; | |||||
u32 vfdca_rxctrl; | |||||
u32 vfdca_txctrl; | |||||
/* VRSRRCTL default values (BSIZEPACKET = 2048, BSIZEHEADER = 256) */ | |||||
vfsrrctl = 0x100 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; | |||||
vfsrrctl |= 0x800 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |||||
/* DCA_RXCTRL default value */ | |||||
vfdca_rxctrl = IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |||||
IXGBE_DCA_RXCTRL_DATA_WRO_EN | | |||||
IXGBE_DCA_RXCTRL_HEAD_WRO_EN; | |||||
/* DCA_TXCTRL default value */ | |||||
vfdca_txctrl = IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |||||
IXGBE_DCA_TXCTRL_DESC_WRO_EN | | |||||
IXGBE_DCA_TXCTRL_DATA_RRO_EN; | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0); | |||||
for (i = 0; i < 7; i++) { | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0); | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0); | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), 0); | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), vfsrrctl); | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0); | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0); | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), 0); | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(i), 0); | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(i), 0); | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(i), vfdca_rxctrl); | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i), vfdca_txctrl); | |||||
} | |||||
IXGBE_WRITE_FLUSH(hw); | |||||
} | |||||
/** | /** | ||||
* ixgbe_start_hw_vf - Prepare hardware for Tx/Rx | * ixgbe_start_hw_vf - Prepare hardware for Tx/Rx | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
Context not available. | |||||
struct ixgbe_mbx_info *mbx = &hw->mbx; | struct ixgbe_mbx_info *mbx = &hw->mbx; | ||||
u32 timeout = IXGBE_VF_INIT_TIMEOUT; | u32 timeout = IXGBE_VF_INIT_TIMEOUT; | ||||
s32 ret_val = IXGBE_ERR_INVALID_MAC_ADDR; | s32 ret_val = IXGBE_ERR_INVALID_MAC_ADDR; | ||||
u32 ctrl, msgbuf[IXGBE_VF_PERMADDR_MSG_LEN]; | u32 msgbuf[IXGBE_VF_PERMADDR_MSG_LEN]; | ||||
u8 *addr = (u8 *)(&msgbuf[1]); | u8 *addr = (u8 *)(&msgbuf[1]); | ||||
DEBUGFUNC("ixgbevf_reset_hw_vf"); | DEBUGFUNC("ixgbevf_reset_hw_vf"); | ||||
Context not available. | |||||
DEBUGOUT("Issuing a function level reset to MAC\n"); | DEBUGOUT("Issuing a function level reset to MAC\n"); | ||||
ctrl = IXGBE_VFREAD_REG(hw, IXGBE_VFCTRL) | IXGBE_CTRL_RST; | IXGBE_VFWRITE_REG(hw, IXGBE_VFCTRL, IXGBE_CTRL_RST); | ||||
IXGBE_VFWRITE_REG(hw, IXGBE_VFCTRL, ctrl); | |||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
msec_delay(50); | msec_delay(50); | ||||
Context not available. | |||||
if (!timeout) | if (!timeout) | ||||
return IXGBE_ERR_RESET_FAILED; | return IXGBE_ERR_RESET_FAILED; | ||||
/* Reset VF registers to initial values */ | |||||
ixgbe_virt_clr_reg(hw); | |||||
/* mailbox timeout can now become active */ | /* mailbox timeout can now become active */ | ||||
mbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT; | mbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT; | ||||
Context not available. | |||||
reg_val &= ~IXGBE_RXDCTL_ENABLE; | reg_val &= ~IXGBE_RXDCTL_ENABLE; | ||||
IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val); | IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val); | ||||
} | } | ||||
/* Clear packet split and pool config */ | |||||
IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0); | |||||
/* flush all queues disables */ | /* flush all queues disables */ | ||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
Context not available. | |||||
if (!(links_reg & IXGBE_LINKS_UP)) | if (!(links_reg & IXGBE_LINKS_UP)) | ||||
goto out; | goto out; | ||||
/* for SFP+ modules and DA cables on 82599 it can take up to 500usecs | |||||
* before the link status is correct | |||||
*/ | |||||
if (mac->type == ixgbe_mac_82599_vf) { | |||||
int i; | |||||
for (i = 0; i < 5; i++) { | |||||
usec_delay(100); | |||||
links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); | |||||
if (!(links_reg & IXGBE_LINKS_UP)) | |||||
goto out; | |||||
} | |||||
} | |||||
switch (links_reg & IXGBE_LINKS_SPEED_82599) { | switch (links_reg & IXGBE_LINKS_SPEED_82599) { | ||||
case IXGBE_LINKS_SPEED_10G_82599: | case IXGBE_LINKS_SPEED_10G_82599: | ||||
*speed = IXGBE_LINK_SPEED_10GB_FULL; | *speed = IXGBE_LINK_SPEED_10GB_FULL; | ||||
Context not available. |