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Differential D1580 Diff 3299 head/sys/dev/ixgbe/ixgbe_api.c

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head/sys/dev/ixgbe/ixgbe_api.c

/****************************************************************************** /******************************************************************************
Copyright (c) 2001-2013, Intel Corporation Copyright (c) 2001-2014, Intel Corporation
All rights reserved. All rights reserved.
Redistribution and use in source and binary forms, with or without Redistribution and use in source and binary forms, with or without
Context not available.
case ixgbe_mac_82599EB: case ixgbe_mac_82599EB:
status = ixgbe_init_ops_82599(hw); status = ixgbe_init_ops_82599(hw);
break; break;
case ixgbe_mac_X540:
status = ixgbe_init_ops_X540(hw);
break;
case ixgbe_mac_X550:
status = ixgbe_init_ops_X550(hw);
break;
case ixgbe_mac_X550EM_x:
case ixgbe_mac_X550EM_a:
status = ixgbe_init_ops_X550EM(hw);
break;
case ixgbe_mac_82599_vf: case ixgbe_mac_82599_vf:
case ixgbe_mac_X540_vf: case ixgbe_mac_X540_vf:
case ixgbe_mac_X550_vf:
case ixgbe_mac_X550EM_x_vf:
case ixgbe_mac_X550EM_a_vf:
status = ixgbe_init_ops_vf(hw); status = ixgbe_init_ops_vf(hw);
break; break;
case ixgbe_mac_X540:
status = ixgbe_init_ops_X540(hw);
break;
default: default:
status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
break; break;
Context not available.
case IXGBE_DEV_ID_82599_SFP_EM: case IXGBE_DEV_ID_82599_SFP_EM:
case IXGBE_DEV_ID_82599_SFP_SF2: case IXGBE_DEV_ID_82599_SFP_SF2:
case IXGBE_DEV_ID_82599_SFP_SF_QP: case IXGBE_DEV_ID_82599_SFP_SF_QP:
case IXGBE_DEV_ID_82599_QSFP_SF_QP:
case IXGBE_DEV_ID_82599EN_SFP: case IXGBE_DEV_ID_82599EN_SFP:
case IXGBE_DEV_ID_82599_CX4: case IXGBE_DEV_ID_82599_CX4:
case IXGBE_DEV_ID_82599_BYPASS: case IXGBE_DEV_ID_82599_BYPASS:
Context not available.
hw->mac.type = ixgbe_mac_X540_vf; hw->mac.type = ixgbe_mac_X540_vf;
break; break;
case IXGBE_DEV_ID_X540T: case IXGBE_DEV_ID_X540T:
case IXGBE_DEV_ID_X540T1:
case IXGBE_DEV_ID_X540_BYPASS: case IXGBE_DEV_ID_X540_BYPASS:
hw->mac.type = ixgbe_mac_X540; hw->mac.type = ixgbe_mac_X540;
break; break;
case IXGBE_DEV_ID_X550T:
hw->mac.type = ixgbe_mac_X550;
break;
case IXGBE_DEV_ID_X550EM_X_KX4:
case IXGBE_DEV_ID_X550EM_X_KR:
case IXGBE_DEV_ID_X550EM_X_10G_T:
case IXGBE_DEV_ID_X550EM_X_1G_T:
case IXGBE_DEV_ID_X550EM_X_SFP:
hw->mac.type = ixgbe_mac_X550EM_x;
break;
case IXGBE_DEV_ID_X550EM_A_KR:
hw->mac.type = ixgbe_mac_X550EM_a;
break;
case IXGBE_DEV_ID_X550_VF:
case IXGBE_DEV_ID_X550_VF_HV:
hw->mac.type = ixgbe_mac_X550_vf;
break;
case IXGBE_DEV_ID_X550EM_X_VF:
case IXGBE_DEV_ID_X550EM_X_VF_HV:
hw->mac.type = ixgbe_mac_X550EM_x_vf;
break;
case IXGBE_DEV_ID_X550EM_A_VF:
case IXGBE_DEV_ID_X550EM_A_VF_HV:
hw->mac.type = ixgbe_mac_X550EM_a_vf;
break;
default: default:
ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
Context not available.
} }
/** /**
* ixgbe_setup_internal_phy - Configure integrated PHY
* @hw: pointer to hardware structure
*
* Reconfigure the integrated PHY in order to enable talk to the external PHY.
* Returns success if not implemented, since nothing needs to be done in this
* case.
*/
s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw),
IXGBE_SUCCESS);
}
/**
* ixgbe_check_phy_link - Determine link and speed status * ixgbe_check_phy_link - Determine link and speed status
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* *
Context not available.
} }
/** /**
* ixgbe_set_phy_power - Control the phy power state
* @hw: pointer to hardware structure
* @on: TRUE for on, FALSE for off
*/
s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on)
{
return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_check_link - Get link and speed status * ixgbe_check_link - Get link and speed status
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* *
Context not available.
} }
/** /**
* ixgbe_setup_mac_link - Set link speed
* @hw: pointer to hardware structure
* @speed: new link speed
*
* Configures link settings. Restarts the link.
* Performs autonegotiation if needed.
**/
s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
bool autoneg_wait_to_complete)
{
return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed,
autoneg_wait_to_complete),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_get_link_capabilities - Returns link capabilities * ixgbe_get_link_capabilities - Returns link capabilities
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* *
Context not available.
} }
/** /**
* ixgbe_setup_fc - Set up flow control
* @hw: pointer to hardware structure
*
* Called at init time to set up flow control.
**/
s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_set_fw_drv_ver - Try to send the driver version number FW * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @maj: driver major number to be sent to firmware * @maj: driver major number to be sent to firmware
Context not available.
/**
* ixgbe_dmac_config - Configure DMA Coalescing registers.
* @hw: pointer to hardware structure
*
* Configure DMA coalescing. If enabling dmac, dmac is activated.
* When disabling dmac, dmac enable dmac bit is cleared.
**/
s32 ixgbe_dmac_config(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/** /**
* ixgbe_dmac_update_tcs - Configure DMA Coalescing registers.
* @hw: pointer to hardware structure
*
* Disables dmac, updates per TC settings, and then enable dmac.
**/
s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_dmac_config_tcs - Configure DMA Coalescing registers.
* @hw: pointer to hardware structure
*
* Configure DMA coalescing threshold per TC and set high priority bit for
* FCOE TC. The dmac enable bit must be cleared before configuring.
**/
s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_setup_eee - Enable/disable EEE support
* @hw: pointer to the HW structure
* @enable_eee: boolean flag to enable EEE
*
* Enable/disable EEE based on enable_ee flag.
* Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
* are modified.
*
**/
s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee)
{
return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_set_source_address_pruning - Enable/Disable source address pruning
* @hw: pointer to hardware structure
* @enbale: enable or disable source address pruning
* @pool: Rx pool - Rx pool to toggle source address pruning
**/
void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
unsigned int pool)
{
if (hw->mac.ops.set_source_address_pruning)
hw->mac.ops.set_source_address_pruning(hw, enable, pool);
}
/**
* ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing
* @hw: pointer to hardware structure
* @enable: enable or disable switch for Ethertype anti-spoofing
* @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
*
**/
void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
{
if (hw->mac.ops.set_ethertype_anti_spoofing)
hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf);
}
/**
* ixgbe_read_iosf_sb_reg - Read 32 bit PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read
* @device_type: type of device you want to communicate with
* @phy_data: Pointer to read data from PHY register
*
* Reads a value from a specified PHY register
**/
s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u32 *phy_data)
{
return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr,
device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband
* @hw: pointer to hardware structure
* @reg_addr: 32 bit PHY register to write
* @device_type: type of device you want to communicate with
* @phy_data: Data to write to the PHY register
*
* Writes a value to specified PHY register
**/
s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u32 phy_data)
{
return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr,
device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_disable_mdd - Disable malicious driver detection
* @hw: pointer to hardware structure
*
**/
void ixgbe_disable_mdd(struct ixgbe_hw *hw)
{
if (hw->mac.ops.disable_mdd)
hw->mac.ops.disable_mdd(hw);
}
/**
* ixgbe_enable_mdd - Enable malicious driver detection
* @hw: pointer to hardware structure
*
**/
void ixgbe_enable_mdd(struct ixgbe_hw *hw)
{
if (hw->mac.ops.enable_mdd)
hw->mac.ops.enable_mdd(hw);
}
/**
* ixgbe_mdd_event - Handle malicious driver detection event
* @hw: pointer to hardware structure
* @vf_bitmap: vf bitmap of malicious vfs
*
**/
void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap)
{
if (hw->mac.ops.mdd_event)
hw->mac.ops.mdd_event(hw, vf_bitmap);
}
/**
* ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver
* detection event
* @hw: pointer to hardware structure
* @vf: vf index
*
**/
void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf)
{
if (hw->mac.ops.restore_mdd_vf)
hw->mac.ops.restore_mdd_vf(hw, vf);
}
/**
* ixgbe_enter_lplu - Transition to low power states
* @hw: pointer to hardware structure
*
* Configures Low Power Link Up on transition to low power states
* (from D0 to non-D0).
**/
s32 ixgbe_enter_lplu(struct ixgbe_hw *hw)
{
return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_read_analog_reg8 - Reads 8 bit analog register * ixgbe_read_analog_reg8 - Reads 8 bit analog register
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @reg: analog register to read * @reg: analog register to read
Context not available.
* ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @byte_offset: byte offset to read * @byte_offset: byte offset to read
* @dev_addr: I2C bus address to read from
* @data: value read * @data: value read
* *
* Performs byte read operation to SFP module's EEPROM over I2C interface. * Performs byte read operation to SFP module's EEPROM over I2C interface.
Context not available.
} }
/** /**
* ixgbe_read_i2c_combined - Perform I2C read combined operation
* @hw: pointer to the hardware structure
* @addr: I2C bus address to read from
* @reg: I2C device register to read from
* @val: pointer to location to receive read value
*
* Returns an error code on error.
*/
s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
{
return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr,
reg, val), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_write_i2c_byte - Writes 8 bit word over I2C * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @byte_offset: byte offset to write * @byte_offset: byte offset to write
* @dev_addr: I2C bus address to write to
* @data: value to write * @data: value to write
* *
* Performs byte write operation to SFP module's EEPROM over I2C interface * Performs byte write operation to SFP module's EEPROM over I2C interface
Context not available.
} }
/** /**
* ixgbe_write_i2c_combined - Perform I2C write combined operation
* @hw: pointer to the hardware structure
* @addr: I2C bus address to write to
* @reg: I2C device register to write to
* @val: value to write
*
* Returns an error code on error.
*/
s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
{
return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr,
reg, val), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @byte_offset: EEPROM byte offset to write * @byte_offset: EEPROM byte offset to write
Context not available.
* Acquires the SWFW semaphore through SW_FW_SYNC register for the specified * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
* function (CSR, PHY0, PHY1, EEPROM, Flash) * function (CSR, PHY0, PHY1, EEPROM, Flash)
**/ **/
s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
{ {
return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
(hw, mask), IXGBE_NOT_IMPLEMENTED); (hw, mask), IXGBE_NOT_IMPLEMENTED);
Context not available.
* Releases the SWFW semaphore through SW_FW_SYNC register for the specified * Releases the SWFW semaphore through SW_FW_SYNC register for the specified
* function (CSR, PHY0, PHY1, EEPROM, Flash) * function (CSR, PHY0, PHY1, EEPROM, Flash)
**/ **/
void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
{ {
if (hw->mac.ops.release_swfw_sync) if (hw->mac.ops.release_swfw_sync)
hw->mac.ops.release_swfw_sync(hw, mask); hw->mac.ops.release_swfw_sync(hw, mask);
} }
void ixgbe_disable_rx(struct ixgbe_hw *hw)
{
if (hw->mac.ops.disable_rx)
hw->mac.ops.disable_rx(hw);
}
void ixgbe_enable_rx(struct ixgbe_hw *hw)
{
if (hw->mac.ops.enable_rx)
hw->mac.ops.enable_rx(hw);
}
/**
* ixgbe_set_rate_select_speed - Set module link speed
* @hw: pointer to hardware structure
* @speed: link speed to set
*
* Set module link speed via the rate select.
*/
void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)
{
if (hw->mac.ops.set_rate_select_speed)
hw->mac.ops.set_rate_select_speed(hw, speed);
}
Context not available.