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Differential D1580 Diff 3299 head/sys/dev/ixgbe/ixgbe_82599.c

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head/sys/dev/ixgbe/ixgbe_82599.c

/****************************************************************************** /******************************************************************************
Copyright (c) 2001-2013, Intel Corporation Copyright (c) 2001-2014, Intel Corporation
All rights reserved. All rights reserved.
Redistribution and use in source and binary forms, with or without Redistribution and use in source and binary forms, with or without
Context not available.
#include "ixgbe_common.h" #include "ixgbe_common.h"
#include "ixgbe_phy.h" #include "ixgbe_phy.h"
#define IXGBE_82599_MAX_TX_QUEUES 128
#define IXGBE_82599_MAX_RX_QUEUES 128
#define IXGBE_82599_RAR_ENTRIES 128
#define IXGBE_82599_MC_TBL_SIZE 128
#define IXGBE_82599_VFT_TBL_SIZE 128
#define IXGBE_82599_RX_PB_SIZE 512
static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
ixgbe_link_speed speed, ixgbe_link_speed speed,
bool autoneg_wait_to_complete); bool autoneg_wait_to_complete);
Context not available.
u16 offset, u16 *data); u16 offset, u16 *data);
static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data); u16 words, u16 *data);
static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data);
static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data);
static bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
{
u32 fwsm, manc, factps;
fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
return FALSE;
manc = IXGBE_READ_REG(hw, IXGBE_MANC);
if (!(manc & IXGBE_MANC_RCV_TCO_EN))
return FALSE;
factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
if (factps & IXGBE_FACTPS_MNGCG)
return FALSE;
return TRUE;
}
void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
{ {
struct ixgbe_mac_info *mac = &hw->mac; struct ixgbe_mac_info *mac = &hw->mac;
Context not available.
* and MNG not enabled * and MNG not enabled
*/ */
if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
!hw->mng_fw_enabled) { !ixgbe_mng_enabled(hw)) {
mac->ops.disable_tx_laser = mac->ops.disable_tx_laser =
&ixgbe_disable_tx_laser_multispeed_fiber; ixgbe_disable_tx_laser_multispeed_fiber;
mac->ops.enable_tx_laser = mac->ops.enable_tx_laser =
&ixgbe_enable_tx_laser_multispeed_fiber; ixgbe_enable_tx_laser_multispeed_fiber;
mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber;
} else { } else {
mac->ops.disable_tx_laser = NULL; mac->ops.disable_tx_laser = NULL;
Context not available.
if (hw->phy.multispeed_fiber) { if (hw->phy.multispeed_fiber) {
/* Set up dual speed SFP+ support */ /* Set up dual speed SFP+ support */
mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599;
mac->ops.set_rate_select_speed =
ixgbe_set_hard_rate_select_speed;
if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed)
mac->ops.set_rate_select_speed =
ixgbe_set_soft_rate_select_speed;
} else { } else {
if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
(hw->phy.smart_speed == ixgbe_smart_speed_auto || (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
hw->phy.smart_speed == ixgbe_smart_speed_on) && hw->phy.smart_speed == ixgbe_smart_speed_on) &&
!ixgbe_verify_lesm_fw_enabled_82599(hw)) { !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed;
} else { } else {
mac->ops.setup_link = &ixgbe_setup_mac_link_82599; mac->ops.setup_link = ixgbe_setup_mac_link_82599;
} }
} }
} }
Context not available.
struct ixgbe_mac_info *mac = &hw->mac; struct ixgbe_mac_info *mac = &hw->mac;
struct ixgbe_phy_info *phy = &hw->phy; struct ixgbe_phy_info *phy = &hw->phy;
s32 ret_val = IXGBE_SUCCESS; s32 ret_val = IXGBE_SUCCESS;
u32 esdp;
DEBUGFUNC("ixgbe_init_phy_ops_82599"); DEBUGFUNC("ixgbe_init_phy_ops_82599");
if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
/* Store flag indicating I2C bus access control unit. */
hw->phy.qsfp_shared_i2c_bus = TRUE;
/* Initialize access to QSFP+ I2C bus */
esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
esdp |= IXGBE_ESDP_SDP0_DIR;
esdp &= ~IXGBE_ESDP_SDP1_DIR;
esdp &= ~IXGBE_ESDP_SDP0;
esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
IXGBE_WRITE_FLUSH(hw);
phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599;
phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599;
}
/* Identify the PHY or SFP module */ /* Identify the PHY or SFP module */
ret_val = phy->ops.identify(hw); ret_val = phy->ops.identify(hw);
if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
Context not available.
/* If copper media, overwrite with copper function pointers */ /* If copper media, overwrite with copper function pointers */
if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
mac->ops.setup_link = &ixgbe_setup_copper_link_82599; mac->ops.setup_link = ixgbe_setup_copper_link_82599;
mac->ops.get_link_capabilities = mac->ops.get_link_capabilities =
&ixgbe_get_copper_link_capabilities_generic; ixgbe_get_copper_link_capabilities_generic;
} }
/* Set necessary function pointers based on phy type */ /* Set necessary function pointers based on PHY type */
switch (hw->phy.type) { switch (hw->phy.type) {
case ixgbe_phy_tn: case ixgbe_phy_tn:
phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
phy->ops.check_link = &ixgbe_check_phy_link_tnx; phy->ops.check_link = ixgbe_check_phy_link_tnx;
phy->ops.get_firmware_version = phy->ops.get_firmware_version =
&ixgbe_get_phy_firmware_version_tnx; ixgbe_get_phy_firmware_version_tnx;
break; break;
default: default:
break; break;
Context not available.
{ {
s32 ret_val = IXGBE_SUCCESS; s32 ret_val = IXGBE_SUCCESS;
u16 list_offset, data_offset, data_value; u16 list_offset, data_offset, data_value;
bool got_lock = FALSE;
DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
Context not available.
/* Release the semaphore */ /* Release the semaphore */
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
/* Delay obtaining semaphore again to allow FW access */ /* Delay obtaining semaphore again to allow FW access
* prot_autoc_write uses the semaphore too.
*/
msec_delay(hw->eeprom.semaphore_delay); msec_delay(hw->eeprom.semaphore_delay);
/* Need SW/FW semaphore around AUTOC writes if LESM on,
* likewise reset_pipeline requires lock as it also writes
* AUTOC.
*/
if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
ret_val = hw->mac.ops.acquire_swfw_sync(hw,
IXGBE_GSSR_MAC_CSR_SM);
if (ret_val != IXGBE_SUCCESS) {
ret_val = IXGBE_ERR_SWFW_SYNC;
goto setup_sfp_out;
}
got_lock = TRUE;
}
/* Restart DSP and set SFI mode */ /* Restart DSP and set SFI mode */
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((hw->mac.orig_autoc) | ret_val = hw->mac.ops.prot_autoc_write(hw,
IXGBE_AUTOC_LMS_10G_SERIAL)); hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); FALSE);
ret_val = ixgbe_reset_pipeline_82599(hw);
if (got_lock) {
hw->mac.ops.release_swfw_sync(hw,
IXGBE_GSSR_MAC_CSR_SM);
got_lock = FALSE;
}
if (ret_val) { if (ret_val) {
DEBUGOUT("sfp module setup not complete\n"); DEBUGOUT("sfp module setup not complete\n");
ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
Context not available.
} }
/** /**
* prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
* @hw: pointer to hardware structure
* @locked: Return the if we locked for this read.
* @reg_val: Value we read from AUTOC
*
* For this part (82599) we need to wrap read-modify-writes with a possible
* FW/SW lock. It is assumed this lock will be freed with the next
* prot_autoc_write_82599().
*/
s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
{
s32 ret_val;
*locked = FALSE;
/* If LESM is on then we need to hold the SW/FW semaphore. */
if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
ret_val = hw->mac.ops.acquire_swfw_sync(hw,
IXGBE_GSSR_MAC_CSR_SM);
if (ret_val != IXGBE_SUCCESS)
return IXGBE_ERR_SWFW_SYNC;
*locked = TRUE;
}
*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
return IXGBE_SUCCESS;
}
/**
* prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
* @hw: pointer to hardware structure
* @reg_val: value to write to AUTOC
* @locked: bool to indicate whether the SW/FW lock was already taken by
* previous proc_autoc_read_82599.
*
* This part (82599) may need to hold the SW/FW lock around all writes to
* AUTOC. Likewise after a write we need to do a pipeline reset.
*/
s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
{
s32 ret_val = IXGBE_SUCCESS;
/* Blocked by MNG FW so bail */
if (ixgbe_check_reset_blocked(hw))
goto out;
/* We only need to get the lock if:
* - We didn't do it already (in the read part of a read-modify-write)
* - LESM is enabled.
*/
if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
ret_val = hw->mac.ops.acquire_swfw_sync(hw,
IXGBE_GSSR_MAC_CSR_SM);
if (ret_val != IXGBE_SUCCESS)
return IXGBE_ERR_SWFW_SYNC;
locked = TRUE;
}
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
ret_val = ixgbe_reset_pipeline_82599(hw);
out:
/* Free the SW/FW semaphore as we either grabbed it here or
* already had it when this function was called.
*/
if (locked)
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
return ret_val;
}
/**
* ixgbe_init_ops_82599 - Inits func ptrs and MAC type * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* *
Context not available.
ret_val = ixgbe_init_ops_generic(hw); ret_val = ixgbe_init_ops_generic(hw);
/* PHY */ /* PHY */
phy->ops.identify = &ixgbe_identify_phy_82599; phy->ops.identify = ixgbe_identify_phy_82599;
phy->ops.init = &ixgbe_init_phy_ops_82599; phy->ops.init = ixgbe_init_phy_ops_82599;
/* MAC */ /* MAC */
mac->ops.reset_hw = &ixgbe_reset_hw_82599; mac->ops.reset_hw = ixgbe_reset_hw_82599;
mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
mac->ops.get_media_type = &ixgbe_get_media_type_82599; mac->ops.get_media_type = ixgbe_get_media_type_82599;
mac->ops.get_supported_physical_layer = mac->ops.get_supported_physical_layer =
&ixgbe_get_supported_physical_layer_82599; ixgbe_get_supported_physical_layer_82599;
mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599; mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599;
mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599; mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599;
mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599; mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599;
mac->ops.start_hw = &ixgbe_start_hw_82599; mac->ops.start_hw = ixgbe_start_hw_82599;
mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
mac->ops.prot_autoc_read = prot_autoc_read_82599;
mac->ops.prot_autoc_write = prot_autoc_write_82599;
/* RAR, Multicast, VLAN */ /* RAR, Multicast, VLAN */
mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic; mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
mac->rar_highwater = 1; mac->rar_highwater = 1;
mac->ops.set_vfta = &ixgbe_set_vfta_generic; mac->ops.set_vfta = ixgbe_set_vfta_generic;
mac->ops.set_vlvf = &ixgbe_set_vlvf_generic; mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599; mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599;
mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
/* Link */ /* Link */
mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599; mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599;
mac->ops.check_link = &ixgbe_check_mac_link_generic; mac->ops.check_link = ixgbe_check_mac_link_generic;
mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic; mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
ixgbe_init_mac_link_ops_82599(hw); ixgbe_init_mac_link_ops_82599(hw);
mac->mcft_size = 128; mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
mac->vft_size = 128; mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
mac->num_rar_entries = 128; mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
mac->rx_pb_size = 512; mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
mac->max_tx_queues = 128; mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
mac->max_rx_queues = 128; mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
Context not available.
hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
/* EEPROM */ /* EEPROM */
eeprom->ops.read = &ixgbe_read_eeprom_82599; eeprom->ops.read = ixgbe_read_eeprom_82599;
eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599; eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599;
/* Manageability interface */ /* Manageability interface */
mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic; mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic; mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
/* Cache if MNG FW is up */
hw->mng_fw_enabled = ixgbe_mng_enabled(hw);
return ret_val; return ret_val;
} }
Context not available.
if (hw->phy.multispeed_fiber) { if (hw->phy.multispeed_fiber) {
*speed |= IXGBE_LINK_SPEED_10GB_FULL | *speed |= IXGBE_LINK_SPEED_10GB_FULL |
IXGBE_LINK_SPEED_1GB_FULL; IXGBE_LINK_SPEED_1GB_FULL;
*autoneg = TRUE;
/* QSFP must not enable full auto-negotiation
* Limited autoneg is enabled at 1G
*/
if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
*autoneg = FALSE;
else
*autoneg = TRUE;
} }
out: out:
Context not available.
case IXGBE_DEV_ID_82599_T3_LOM: case IXGBE_DEV_ID_82599_T3_LOM:
media_type = ixgbe_media_type_copper; media_type = ixgbe_media_type_copper;
break; break;
case IXGBE_DEV_ID_82599_QSFP_SF_QP:
media_type = ixgbe_media_type_fiber_qsfp;
break;
case IXGBE_DEV_ID_82599_BYPASS: case IXGBE_DEV_ID_82599_BYPASS:
media_type = ixgbe_media_type_fiber_fixed; media_type = ixgbe_media_type_fiber_fixed;
hw->phy.multispeed_fiber = TRUE; hw->phy.multispeed_fiber = TRUE;
Context not available.
DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599"); DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
if (!hw->mng_fw_enabled && !hw->wol_enabled && if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&
ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
Context not available.
{ {
u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
/* Disable tx laser; allow 100us to go dark per spec */ /* Blocked by MNG FW so bail */
if (ixgbe_check_reset_blocked(hw))
return;
/* Disable Tx laser; allow 100us to go dark per spec */
esdp_reg |= IXGBE_ESDP_SDP3; esdp_reg |= IXGBE_ESDP_SDP3;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_FLUSH(hw);
Context not available.
{ {
u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
/* Enable tx laser; allow 100ms to light up */ /* Enable Tx laser; allow 100ms to light up */
esdp_reg &= ~IXGBE_ESDP_SDP3; esdp_reg &= ~IXGBE_ESDP_SDP3;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_FLUSH(hw);
Context not available.
* When the driver changes the link speeds that it can support, * When the driver changes the link speeds that it can support,
* it sets autotry_restart to TRUE to indicate that we need to * it sets autotry_restart to TRUE to indicate that we need to
* initiate a new autotry session with the link partner. To do * initiate a new autotry session with the link partner. To do
* so, we set the speed then disable and re-enable the tx laser, to * so, we set the speed then disable and re-enable the Tx laser, to
* alert the link partner that it also needs to restart autotry on its * alert the link partner that it also needs to restart autotry on its
* end. This is consistent with TRUE clause 37 autoneg, which also * end. This is consistent with TRUE clause 37 autoneg, which also
* involves a loss of signal. * involves a loss of signal.
Context not available.
{ {
DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
/* Blocked by MNG FW so bail */
if (ixgbe_check_reset_blocked(hw))
return;
if (hw->mac.autotry_restart) { if (hw->mac.autotry_restart) {
ixgbe_disable_tx_laser_multispeed_fiber(hw); ixgbe_disable_tx_laser_multispeed_fiber(hw);
ixgbe_enable_tx_laser_multispeed_fiber(hw); ixgbe_enable_tx_laser_multispeed_fiber(hw);
Context not available.
} }
/** /**
* ixgbe_set_fiber_fixed_speed - Set module link speed for fixed fiber * ixgbe_set_hard_rate_select_speed - Set module link speed
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @speed: link speed to set * @speed: link speed to set
* *
* We set the module speed differently for fixed fiber. For other * Set module link speed via RS0/RS1 rate select pins.
* multi-speed devices we don't have an error value so here if we
* detect an error we just log it and exit.
*/ */
static void ixgbe_set_fiber_fixed_speed(struct ixgbe_hw *hw, void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,
ixgbe_link_speed speed) ixgbe_link_speed speed)
{ {
s32 status; u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
u8 rs, eeprom_data;
switch (speed) { switch (speed) {
case IXGBE_LINK_SPEED_10GB_FULL: case IXGBE_LINK_SPEED_10GB_FULL:
/* one bit mask same as setting on */ esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
break; break;
case IXGBE_LINK_SPEED_1GB_FULL: case IXGBE_LINK_SPEED_1GB_FULL:
rs = IXGBE_SFF_SOFT_RS_SELECT_1G; esdp_reg &= ~IXGBE_ESDP_SDP5;
esdp_reg |= IXGBE_ESDP_SDP5_DIR;
break; break;
default: default:
DEBUGOUT("Invalid fixed module speed\n"); DEBUGOUT("Invalid fixed module speed\n");
Context not available.
return; return;
} }
/* Set RS0 */ IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, IXGBE_WRITE_FLUSH(hw);
IXGBE_I2C_EEPROM_DEV_ADDR2,
&eeprom_data);
if (status) {
DEBUGOUT("Failed to read Rx Rate Select RS0\n");
goto out;
}
eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
IXGBE_I2C_EEPROM_DEV_ADDR2,
eeprom_data);
if (status) {
DEBUGOUT("Failed to write Rx Rate Select RS0\n");
goto out;
}
/* Set RS1 */
status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
IXGBE_I2C_EEPROM_DEV_ADDR2,
&eeprom_data);
if (status) {
DEBUGOUT("Failed to read Rx Rate Select RS1\n");
goto out;
}
eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
IXGBE_I2C_EEPROM_DEV_ADDR2,
eeprom_data);
if (status) {
DEBUGOUT("Failed to write Rx Rate Select RS1\n");
goto out;
}
out:
return;
} }
/** /**
* ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg_wait_to_complete: TRUE when waiting for completion is needed
*
* Set the link speed in the AUTOC register and restarts link.
**/
s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
ixgbe_link_speed speed,
bool autoneg_wait_to_complete)
{
s32 status = IXGBE_SUCCESS;
ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
u32 speedcnt = 0;
u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
u32 i = 0;
bool autoneg, link_up = FALSE;
DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
/* Mask off requested but non-supported speeds */
status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
if (status != IXGBE_SUCCESS)
return status;
speed &= link_speed;
/*
* Try each speed one by one, highest priority first. We do this in
* software because 10gb fiber doesn't support speed autonegotiation.
*/
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
speedcnt++;
highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
/* If we already have link at this speed, just jump out */
status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
if (status != IXGBE_SUCCESS)
return status;
if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
goto out;
/* Set the module link speed */
if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
ixgbe_set_fiber_fixed_speed(hw,
IXGBE_LINK_SPEED_10GB_FULL);
} else {
esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
IXGBE_WRITE_FLUSH(hw);
}
/* Allow module to change analog characteristics (1G->10G) */
msec_delay(40);
status = ixgbe_setup_mac_link_82599(hw,
IXGBE_LINK_SPEED_10GB_FULL,
autoneg_wait_to_complete);
if (status != IXGBE_SUCCESS)
return status;
/* Flap the tx laser if it has not already been done */
ixgbe_flap_tx_laser(hw);
/*
* Wait for the controller to acquire link. Per IEEE 802.3ap,
* Section 73.10.2, we may have to wait up to 500ms if KR is
* attempted. 82599 uses the same timing for 10g SFI.
*/
for (i = 0; i < 5; i++) {
/* Wait for the link partner to also set speed */
msec_delay(100);
/* If we have link, just jump out */
status = ixgbe_check_link(hw, &link_speed,
&link_up, FALSE);
if (status != IXGBE_SUCCESS)
return status;
if (link_up)
goto out;
}
}
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
speedcnt++;
if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
/* If we already have link at this speed, just jump out */
status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
if (status != IXGBE_SUCCESS)
return status;
if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
goto out;
/* Set the module link speed */
if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
ixgbe_set_fiber_fixed_speed(hw,
IXGBE_LINK_SPEED_1GB_FULL);
} else {
esdp_reg &= ~IXGBE_ESDP_SDP5;
esdp_reg |= IXGBE_ESDP_SDP5_DIR;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
IXGBE_WRITE_FLUSH(hw);
}
/* Allow module to change analog characteristics (10G->1G) */
msec_delay(40);
status = ixgbe_setup_mac_link_82599(hw,
IXGBE_LINK_SPEED_1GB_FULL,
autoneg_wait_to_complete);
if (status != IXGBE_SUCCESS)
return status;
/* Flap the tx laser if it has not already been done */
ixgbe_flap_tx_laser(hw);
/* Wait for the link partner to also set speed */
msec_delay(100);
/* If we have link, just jump out */
status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
if (status != IXGBE_SUCCESS)
return status;
if (link_up)
goto out;
}
/*
* We didn't get link. Configure back to the highest speed we tried,
* (if there was more than one). We call ourselves back with just the
* single highest speed that the user requested.
*/
if (speedcnt > 1)
status = ixgbe_setup_mac_link_multispeed_fiber(hw,
highest_link_speed, autoneg_wait_to_complete);
out:
/* Set autoneg_advertised value based on input link speed */
hw->phy.autoneg_advertised = 0;
if (speed & IXGBE_LINK_SPEED_10GB_FULL)
hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
if (speed & IXGBE_LINK_SPEED_1GB_FULL)
hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
return status;
}
/**
* ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @speed: new link speed * @speed: new link speed
Context not available.
{ {
bool autoneg = FALSE; bool autoneg = FALSE;
s32 status = IXGBE_SUCCESS; s32 status = IXGBE_SUCCESS;
u32 autoc, pma_pmd_1g, link_mode, start_autoc; u32 pma_pmd_1g, link_mode;
u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
u32 orig_autoc = 0; /* holds the cached value of AUTOC register */
u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */
u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
u32 orig_autoc = 0;
u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
u32 links_reg; u32 links_reg;
u32 i; u32 i;
ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
bool got_lock = FALSE;
DEBUGFUNC("ixgbe_setup_mac_link_82599"); DEBUGFUNC("ixgbe_setup_mac_link_82599");
Context not available.
/* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
if (hw->mac.orig_link_settings_stored) if (hw->mac.orig_link_settings_stored)
autoc = hw->mac.orig_autoc; orig_autoc = hw->mac.orig_autoc;
else else
autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); orig_autoc = autoc;
orig_autoc = autoc;
start_autoc = hw->mac.cached_autoc;
link_mode = autoc & IXGBE_AUTOC_LMS_MASK; link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
Context not available.
if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
(pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
autoc &= ~IXGBE_AUTOC_LMS_MASK; autoc &= ~IXGBE_AUTOC_LMS_MASK;
if (autoneg) if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)
autoc |= IXGBE_AUTOC_LMS_1G_AN; autoc |= IXGBE_AUTOC_LMS_1G_AN;
else else
autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
Context not available.
} }
} }
if (autoc != start_autoc) { if (autoc != current_autoc) {
/* Need SW/FW semaphore around AUTOC writes if LESM is on,
* likewise reset_pipeline requires us to hold this lock as
* it also writes to AUTOC.
*/
if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
status = hw->mac.ops.acquire_swfw_sync(hw,
IXGBE_GSSR_MAC_CSR_SM);
if (status != IXGBE_SUCCESS) {
status = IXGBE_ERR_SWFW_SYNC;
goto out;
}
got_lock = TRUE;
}
/* Restart link */ /* Restart link */
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); status = hw->mac.ops.prot_autoc_write(hw, autoc, FALSE);
hw->mac.cached_autoc = autoc; if (status != IXGBE_SUCCESS)
ixgbe_reset_pipeline_82599(hw); goto out;
if (got_lock) {
hw->mac.ops.release_swfw_sync(hw,
IXGBE_GSSR_MAC_CSR_SM);
got_lock = FALSE;
}
/* Only poll for autoneg to complete if specified to do so */ /* Only poll for autoneg to complete if specified to do so */
if (autoneg_wait_to_complete) { if (autoneg_wait_to_complete) {
if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
Context not available.
{ {
ixgbe_link_speed link_speed; ixgbe_link_speed link_speed;
s32 status; s32 status;
u32 ctrl, i, autoc2; u32 ctrl = 0;
u32 i, autoc, autoc2;
u32 curr_lms; u32 curr_lms;
bool link_up = FALSE; bool link_up = FALSE;
Context not available.
hw->phy.ops.reset(hw); hw->phy.ops.reset(hw);
/* remember AUTOC from before we reset */ /* remember AUTOC from before we reset */
if (hw->mac.cached_autoc) curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
curr_lms = hw->mac.cached_autoc & IXGBE_AUTOC_LMS_MASK;
else
curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) &
IXGBE_AUTOC_LMS_MASK;
mac_reset_top: mac_reset_top:
/* /*
Context not available.
IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_FLUSH(hw);
/* Poll for reset bit to self-clear indicating reset is complete */ /* Poll for reset bit to self-clear meaning reset is complete */
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
usec_delay(1); usec_delay(1);
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
Context not available.
/* /*
* Double resets are required for recovery from certain error * Double resets are required for recovery from certain error
* conditions. Between resets, it is necessary to stall to allow time * conditions. Between resets, it is necessary to stall to
* for any pending HW events to complete. * allow time for any pending HW events to complete.
*/ */
if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
Context not available.
* stored off yet. Otherwise restore the stored original * stored off yet. Otherwise restore the stored original
* values since the reset operation sets back to defaults. * values since the reset operation sets back to defaults.
*/ */
hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
/* Enable link if disabled in NVM */ /* Enable link if disabled in NVM */
Context not available.
} }
if (hw->mac.orig_link_settings_stored == FALSE) { if (hw->mac.orig_link_settings_stored == FALSE) {
hw->mac.orig_autoc = hw->mac.cached_autoc; hw->mac.orig_autoc = autoc;
hw->mac.orig_autoc2 = autoc2; hw->mac.orig_autoc2 = autoc2;
hw->mac.orig_link_settings_stored = TRUE; hw->mac.orig_link_settings_stored = TRUE;
} else { } else {
Context not available.
* Likewise if we support WoL we don't want change the * Likewise if we support WoL we don't want change the
* LMS state. * LMS state.
*/ */
if ((hw->phy.multispeed_fiber && hw->mng_fw_enabled) || if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
hw->wol_enabled) hw->wol_enabled)
hw->mac.orig_autoc = hw->mac.orig_autoc =
(hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
curr_lms; curr_lms;
if (hw->mac.cached_autoc != hw->mac.orig_autoc) { if (autoc != hw->mac.orig_autoc) {
/* Need SW/FW semaphore around AUTOC writes if LESM is status = hw->mac.ops.prot_autoc_write(hw,
* on, likewise reset_pipeline requires us to hold hw->mac.orig_autoc,
* this lock as it also writes to AUTOC. FALSE);
*/ if (status != IXGBE_SUCCESS)
bool got_lock = FALSE; goto reset_hw_out;
if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
status = hw->mac.ops.acquire_swfw_sync(hw,
IXGBE_GSSR_MAC_CSR_SM);
if (status != IXGBE_SUCCESS) {
status = IXGBE_ERR_SWFW_SYNC;
goto reset_hw_out;
}
got_lock = TRUE;
}
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
hw->mac.cached_autoc = hw->mac.orig_autoc;
ixgbe_reset_pipeline_82599(hw);
if (got_lock)
hw->mac.ops.release_swfw_sync(hw,
IXGBE_GSSR_MAC_CSR_SM);
} }
if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
Context not available.
} }
/** /**
* ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
* @hw: pointer to hardware structure
* @fdircmd: current value of FDIRCMD register
*/
static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)
{
int i;
for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
*fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
return IXGBE_SUCCESS;
usec_delay(10);
}
return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
}
/**
* ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
**/ **/
s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
{ {
s32 err;
int i; int i;
u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
u32 fdircmd;
fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
DEBUGFUNC("ixgbe_reinit_fdir_tables_82599"); DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
Context not available.
* Before starting reinitialization process, * Before starting reinitialization process,
* FDIRCMD.CMD must be zero. * FDIRCMD.CMD must be zero.
*/ */
for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & if (err) {
IXGBE_FDIRCMD_CMD_MASK)) DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
break; return err;
usec_delay(10);
} }
if (i >= IXGBE_FDIRCMD_CMD_POLL) {
DEBUGOUT("Flow Director previous command isn't complete, "
"aborting table re-initialization.\n");
return IXGBE_ERR_FDIR_REINIT_FAILED;
}
IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_FLUSH(hw);
Context not available.
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @fdirctrl: value to write to flow director control register, initially * @fdirctrl: value to write to flow director control register, initially
* contains just the value of the Rx packet buffer allocation * contains just the value of the Rx packet buffer allocation
* @cloud_mode: TRUE - cloud mode, FALSE - other mode
**/ **/
s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
bool cloud_mode)
{ {
DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
Context not available.
(0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
(4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
if (cloud_mode)
fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
/* write hashes and fdirctrl register, poll for completion */ /* write hashes and fdirctrl register, poll for completion */
ixgbe_fdir_enable_82599(hw, fdirctrl); ixgbe_fdir_enable_82599(hw, fdirctrl);
Context not available.
bucket_hash ^= hi_hash_dword >> n; \ bucket_hash ^= hi_hash_dword >> n; \
else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
sig_hash ^= hi_hash_dword << (16 - n); \ sig_hash ^= hi_hash_dword << (16 - n); \
} while (0); } while (0)
/** /**
* ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
Context not available.
* @stream: input bitstream to compute the hash on * @stream: input bitstream to compute the hash on
* *
* This function is almost identical to the function above but contains * This function is almost identical to the function above but contains
* several optomizations such as unwinding all of the loops, letting the * several optimizations such as unwinding all of the loops, letting the
* compiler work out all of the conditional ifs since the keys are static * compiler work out all of the conditional ifs since the keys are static
* defines, and computing two keys at once since the hashed dword stream * defines, and computing two keys at once since the hashed dword stream
* will be the same for both keys. * will be the same for both keys.
Context not available.
/* /*
* apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
* delay this because bit 0 of the stream should not be processed * delay this because bit 0 of the stream should not be processed
* so we do not add the vlan until after bit 0 was processed * so we do not add the VLAN until after bit 0 was processed
*/ */
lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
Context not available.
* @input: unique input dword * @input: unique input dword
* @common: compressed common input dword * @common: compressed common input dword
* @queue: queue index to direct traffic to * @queue: queue index to direct traffic to
*
* Note that the tunnel bit in input must not be set when the hardware
* tunneling support does not exist.
**/ **/
s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
union ixgbe_atr_hash_dword input, union ixgbe_atr_hash_dword input,
Context not available.
union ixgbe_atr_hash_dword common, union ixgbe_atr_hash_dword common,
u8 queue) u8 queue)
{ {
u64 fdirhashcmd; u64 fdirhashcmd;
u32 fdircmd; u8 flow_type;
bool tunnel;
u32 fdircmd;
s32 err;
DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
Context not available.
/* /*
* Get the flow_type in order to program FDIRCMD properly * Get the flow_type in order to program FDIRCMD properly
* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
* fifth is FDIRCMD.TUNNEL_FILTER
*/ */
switch (input.formatted.flow_type) { tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK);
flow_type = input.formatted.flow_type &
(IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
switch (flow_type) {
case IXGBE_ATR_FLOW_TYPE_TCPV4: case IXGBE_ATR_FLOW_TYPE_TCPV4:
case IXGBE_ATR_FLOW_TYPE_UDPV4: case IXGBE_ATR_FLOW_TYPE_UDPV4:
case IXGBE_ATR_FLOW_TYPE_SCTPV4: case IXGBE_ATR_FLOW_TYPE_SCTPV4:
Context not available.
/* configure FDIRCMD register */ /* configure FDIRCMD register */
fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
if (tunnel)
fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
/* /*
* The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
Context not available.
fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
if (err) {
DEBUGOUT("Flow Director command did not complete!\n");
return err;
}
DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
return IXGBE_SUCCESS; return IXGBE_SUCCESS;
Context not available.
bucket_hash ^= lo_hash_dword >> n; \ bucket_hash ^= lo_hash_dword >> n; \
if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
bucket_hash ^= hi_hash_dword >> n; \ bucket_hash ^= hi_hash_dword >> n; \
} while (0); } while (0)
/** /**
* ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
Context not available.
* @atr_input: input bitstream to compute the hash on * @atr_input: input bitstream to compute the hash on
* @input_mask: mask for the input bitstream * @input_mask: mask for the input bitstream
* *
* This function serves two main purposes. First it applys the input_mask * This function serves two main purposes. First it applies the input_mask
* to the atr_input resulting in a cleaned up atr_input data stream. * to the atr_input resulting in a cleaned up atr_input data stream.
* Secondly it computes the hash and stores it in the bkt_hash field at * Secondly it computes the hash and stores it in the bkt_hash field at
* the end of the input byte stream. This way it will be available for * the end of the input byte stream. This way it will be available for
Context not available.
u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
u32 bucket_hash = 0; u32 bucket_hash = 0;
u32 hi_dword = 0;
u32 i = 0;
/* Apply masks to input data */ /* Apply masks to input data */
input->dword_stream[0] &= input_mask->dword_stream[0]; for (i = 0; i < 14; i++)
input->dword_stream[1] &= input_mask->dword_stream[1]; input->dword_stream[i] &= input_mask->dword_stream[i];
input->dword_stream[2] &= input_mask->dword_stream[2];
input->dword_stream[3] &= input_mask->dword_stream[3];
input->dword_stream[4] &= input_mask->dword_stream[4];
input->dword_stream[5] &= input_mask->dword_stream[5];
input->dword_stream[6] &= input_mask->dword_stream[6];
input->dword_stream[7] &= input_mask->dword_stream[7];
input->dword_stream[8] &= input_mask->dword_stream[8];
input->dword_stream[9] &= input_mask->dword_stream[9];
input->dword_stream[10] &= input_mask->dword_stream[10];
/* record the flow_vm_vlan bits as they are a key part to the hash */ /* record the flow_vm_vlan bits as they are a key part to the hash */
flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]); flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
/* generate common hash dword */ /* generate common hash dword */
hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^ for (i = 1; i <= 13; i++)
input->dword_stream[2] ^ hi_dword ^= input->dword_stream[i];
input->dword_stream[3] ^ hi_hash_dword = IXGBE_NTOHL(hi_dword);
input->dword_stream[4] ^
input->dword_stream[5] ^
input->dword_stream[6] ^
input->dword_stream[7] ^
input->dword_stream[8] ^
input->dword_stream[9] ^
input->dword_stream[10]);
/* low dword is word swapped version of common */ /* low dword is word swapped version of common */
lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
Context not available.
/* /*
* apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
* delay this because bit 0 of the stream should not be processed * delay this because bit 0 of the stream should not be processed
* so we do not add the vlan until after bit 0 was processed * so we do not add the VLAN until after bit 0 was processed
*/ */
lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
/* Process remaining 30 bit of the key */ /* Process remaining 30 bit of the key */
IXGBE_COMPUTE_BKT_HASH_ITERATION(1); for (i = 1; i <= 15; i++)
IXGBE_COMPUTE_BKT_HASH_ITERATION(2); IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
/* /*
* Limit hash to 13 bits since max bucket count is 8K. * Limit hash to 13 bits since max bucket count is 8K.
Context not available.
} }
/** /**
* ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
* @input_mask: mask to be bit swapped * @input_mask: mask to be bit swapped
* *
* The source and destination port masks for flow director are bit swapped * The source and destination port masks for flow director are bit swapped
Context not available.
IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8)) IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
union ixgbe_atr_input *input_mask) union ixgbe_atr_input *input_mask, bool cloud_mode)
{ {
/* mask IPv6 since it is currently not supported */ /* mask IPv6 since it is currently not supported */
u32 fdirm = IXGBE_FDIRM_DIPv6; u32 fdirm = IXGBE_FDIRM_DIPv6;
u32 fdirtcpm; u32 fdirtcpm;
u32 fdirip6m;
DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599"); DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
/* /*
Context not available.
return IXGBE_ERR_CONFIG; return IXGBE_ERR_CONFIG;
} }
if (cloud_mode) {
fdirm |= IXGBE_FDIRM_L3P;
fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
switch (input_mask->formatted.inner_mac[0] & 0xFF) {
case 0x00:
/* Mask inner MAC, fall through */
fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC;
case 0xFF:
break;
default:
DEBUGOUT(" Error on inner_mac byte mask\n");
return IXGBE_ERR_CONFIG;
}
switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) {
case 0x0:
/* Mask vxlan id */
fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI;
break;
case 0x00FFFFFF:
fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
break;
case 0xFFFFFFFF:
break;
default:
DEBUGOUT(" Error on TNI/VNI byte mask\n");
return IXGBE_ERR_CONFIG;
}
switch (input_mask->formatted.tunnel_type & 0xFFFF) {
case 0x0:
/* Mask turnnel type, fall through */
fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
case 0xFFFF:
break;
default:
DEBUGOUT(" Error on tunnel type byte mask\n");
return IXGBE_ERR_CONFIG;
}
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
/* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and
* FDIRDIP4M in cloud mode to allow L3/L3 packets to
* tunnel.
*/
IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
}
/* Now mask VM pool and destination IPv6 - bits 5 and 2 */ /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
/* store the TCP/UDP port masks, bit reversed from port layout */ if (!cloud_mode) {
fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); /* store the TCP/UDP port masks, bit reversed from port
* layout */
fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
/* write both the same so that UDP and TCP use the same mask */ /* write both the same so that UDP and TCP use the same mask */
IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
/* also use it for SCTP */
switch (hw->mac.type) {
case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x:
case ixgbe_mac_X550EM_a:
IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
break;
default:
break;
}
/* store source and destination IP masks (big-enian) */ /* store source and destination IP masks (big-enian) */
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
~input_mask->formatted.src_ip[0]); ~input_mask->formatted.src_ip[0]);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
~input_mask->formatted.dst_ip[0]); ~input_mask->formatted.dst_ip[0]);
}
return IXGBE_SUCCESS; return IXGBE_SUCCESS;
} }
s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
union ixgbe_atr_input *input, union ixgbe_atr_input *input,
u16 soft_id, u8 queue) u16 soft_id, u8 queue, bool cloud_mode)
{ {
u32 fdirport, fdirvlan, fdirhash, fdircmd; u32 fdirport, fdirvlan, fdirhash, fdircmd;
u32 addr_low, addr_high;
u32 cloud_type = 0;
s32 err;
DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599"); DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
if (!cloud_mode) {
/* currently IPv6 is not supported, must be programmed with 0 */
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
input->formatted.src_ip[0]);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
input->formatted.src_ip[1]);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
input->formatted.src_ip[2]);
/* currently IPv6 is not supported, must be programmed with 0 */ /* record the source address (big-endian) */
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA,
input->formatted.src_ip[0]); input->formatted.src_ip[0]);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
input->formatted.src_ip[1]);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
input->formatted.src_ip[2]);
/* record the source address (big-endian) */ /* record the first 32 bits of the destination address
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); * (big-endian) */
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA,
input->formatted.dst_ip[0]);
/* record the first 32 bits of the destination address (big-endian) */ /* record source and destination port (little-endian)*/
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); fdirport = IXGBE_NTOHS(input->formatted.dst_port);
fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
fdirport |= IXGBE_NTOHS(input->formatted.src_port);
IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
}
/* record source and destination port (little-endian)*/ /* record VLAN (little-endian) and flex_bytes(big-endian) */
fdirport = IXGBE_NTOHS(input->formatted.dst_port);
fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
fdirport |= IXGBE_NTOHS(input->formatted.src_port);
IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
/* record vlan (little-endian) and flex_bytes(big-endian) */
fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id); fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
if (cloud_mode) {
if (input->formatted.tunnel_type != 0)
cloud_type = 0x80000000;
addr_low = ((u32)input->formatted.inner_mac[0] |
((u32)input->formatted.inner_mac[1] << 8) |
((u32)input->formatted.inner_mac[2] << 16) |
((u32)input->formatted.inner_mac[3] << 24));
addr_high = ((u32)input->formatted.inner_mac[4] |
((u32)input->formatted.inner_mac[5] << 8));
cloud_type |= addr_high;
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);
}
/* configure FDIRHASH register */ /* configure FDIRHASH register */
fdirhash = input->formatted.bkt_hash; fdirhash = input->formatted.bkt_hash;
fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
Context not available.
IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
if (queue == IXGBE_FDIR_DROP_QUEUE) if (queue == IXGBE_FDIR_DROP_QUEUE)
fdircmd |= IXGBE_FDIRCMD_DROP; fdircmd |= IXGBE_FDIRCMD_DROP;
if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
if (err) {
DEBUGOUT("Flow Director command did not complete!\n");
return err;
}
return IXGBE_SUCCESS; return IXGBE_SUCCESS;
} }
Context not available.
u16 soft_id) u16 soft_id)
{ {
u32 fdirhash; u32 fdirhash;
u32 fdircmd = 0; u32 fdircmd;
u32 retry_count; s32 err;
s32 err = IXGBE_SUCCESS;
/* configure FDIRHASH register */ /* configure FDIRHASH register */
fdirhash = input->formatted.bkt_hash; fdirhash = input->formatted.bkt_hash;
Context not available.
/* Query if filter is present */ /* Query if filter is present */
IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
for (retry_count = 10; retry_count; retry_count--) { err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
/* allow 10us for query to process */ if (err) {
usec_delay(10); DEBUGOUT("Flow Director command did not complete!\n");
/* verify query completed successfully */ return err;
fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
break;
} }
if (!retry_count)
err = IXGBE_ERR_FDIR_REINIT_FAILED;
/* if filter exists in hardware then remove it */ /* if filter exists in hardware then remove it */
if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
Context not available.
IXGBE_FDIRCMD_CMD_REMOVE_FLOW); IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
} }
return err; return IXGBE_SUCCESS;
} }
/** /**
Context not available.
s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
union ixgbe_atr_input *input, union ixgbe_atr_input *input,
union ixgbe_atr_input *input_mask, union ixgbe_atr_input *input_mask,
u16 soft_id, u8 queue) u16 soft_id, u8 queue, bool cloud_mode)
{ {
s32 err = IXGBE_ERR_CONFIG; s32 err = IXGBE_ERR_CONFIG;
Context not available.
*/ */
switch (input->formatted.flow_type) { switch (input->formatted.flow_type) {
case IXGBE_ATR_FLOW_TYPE_IPV4: case IXGBE_ATR_FLOW_TYPE_IPV4:
case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK; input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
if (input->formatted.dst_port || input->formatted.src_port) { if (input->formatted.dst_port || input->formatted.src_port) {
DEBUGOUT(" Error on src/dst port\n"); DEBUGOUT(" Error on src/dst port\n");
Context not available.
} }
break; break;
case IXGBE_ATR_FLOW_TYPE_SCTPV4: case IXGBE_ATR_FLOW_TYPE_SCTPV4:
case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
if (input->formatted.dst_port || input->formatted.src_port) { if (input->formatted.dst_port || input->formatted.src_port) {
DEBUGOUT(" Error on src/dst port\n"); DEBUGOUT(" Error on src/dst port\n");
return IXGBE_ERR_CONFIG; return IXGBE_ERR_CONFIG;
} }
case IXGBE_ATR_FLOW_TYPE_TCPV4: case IXGBE_ATR_FLOW_TYPE_TCPV4:
case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
case IXGBE_ATR_FLOW_TYPE_UDPV4: case IXGBE_ATR_FLOW_TYPE_UDPV4:
case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
IXGBE_ATR_L4TYPE_MASK; IXGBE_ATR_L4TYPE_MASK;
break; break;
Context not available.
} }
/* program input mask into the HW */ /* program input mask into the HW */
err = ixgbe_fdir_set_input_mask_82599(hw, input_mask); err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
if (err) if (err)
return err; return err;
Context not available.
/* program filters to filter memory */ /* program filters to filter memory */
return ixgbe_fdir_write_perfect_filter_82599(hw, input, return ixgbe_fdir_write_perfect_filter_82599(hw, input,
soft_id, queue); soft_id, queue, cloud_mode);
} }
/** /**
Context not available.
**/ **/
s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
{ {
s32 status = IXGBE_ERR_PHY_ADDR_INVALID; s32 status;
DEBUGFUNC("ixgbe_identify_phy_82599"); DEBUGFUNC("ixgbe_identify_phy_82599");
Context not available.
if (status != IXGBE_SUCCESS) { if (status != IXGBE_SUCCESS) {
/* 82599 10GBASE-T requires an external PHY */ /* 82599 10GBASE-T requires an external PHY */
if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
goto out; return status;
else else
status = ixgbe_identify_module_generic(hw); status = ixgbe_identify_module_generic(hw);
} }
Context not available.
/* Set PHY type none if no PHY detected */ /* Set PHY type none if no PHY detected */
if (hw->phy.type == ixgbe_phy_unknown) { if (hw->phy.type == ixgbe_phy_unknown) {
hw->phy.type = ixgbe_phy_none; hw->phy.type = ixgbe_phy_none;
status = IXGBE_SUCCESS; return IXGBE_SUCCESS;
} }
/* Return error if SFP module has been detected but is not supported */ /* Return error if SFP module has been detected but is not supported */
if (hw->phy.type == ixgbe_phy_sfp_unsupported) if (hw->phy.type == ixgbe_phy_sfp_unsupported)
status = IXGBE_ERR_SFP_NOT_SUPPORTED; return IXGBE_ERR_SFP_NOT_SUPPORTED;
out:
return status; return status;
} }
Context not available.
u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
u16 ext_ability = 0; u16 ext_ability = 0;
u8 comp_codes_10g = 0;
u8 comp_codes_1g = 0;
DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
Context not available.
/* SFP check must be done last since DA modules are sometimes used to /* SFP check must be done last since DA modules are sometimes used to
* test KR mode - we need to id KR mode correctly before SFP module. * test KR mode - we need to id KR mode correctly before SFP module.
* Call identify_sfp because the pluggable module may have changed */ * Call identify_sfp because the pluggable module may have changed */
hw->phy.ops.identify_sfp(hw); physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
goto out;
switch (hw->phy.type) {
case ixgbe_phy_sfp_passive_tyco:
case ixgbe_phy_sfp_passive_unknown:
physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
break;
case ixgbe_phy_sfp_ftl_active:
case ixgbe_phy_sfp_active_unknown:
physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
break;
case ixgbe_phy_sfp_avago:
case ixgbe_phy_sfp_ftl:
case ixgbe_phy_sfp_intel:
case ixgbe_phy_sfp_unknown:
hw->phy.ops.read_i2c_eeprom(hw,
IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
hw->phy.ops.read_i2c_eeprom(hw,
IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
break;
default:
break;
}
out: out:
return physical_layer; return physical_layer;
} }
Context not available.
hw->mac.ops.disable_sec_rx_path(hw); hw->mac.ops.disable_sec_rx_path(hw);
IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); if (regval & IXGBE_RXCTRL_RXEN)
ixgbe_enable_rx(hw);
else
ixgbe_disable_rx(hw);
hw->mac.ops.enable_sec_rx_path(hw); hw->mac.ops.enable_sec_rx_path(hw);
Context not available.
} }
/** /**
* ixgbe_verify_fw_version_82599 - verify fw version for 82599 * ixgbe_verify_fw_version_82599 - verify FW version for 82599
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* *
* Verifies that installed the firmware version is 0.6 or higher * Verifies that installed the firmware version is 0.6 or higher
Context not available.
(fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
goto out; goto out;
/* get the lesm state word */ /* get the LESM state word */
status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
IXGBE_FW_LESM_STATE_1), IXGBE_FW_LESM_STATE_1),
&fw_lesm_state); &fw_lesm_state);
Context not available.
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* *
* Reset pipeline by asserting Restart_AN together with LMS change to ensure * Reset pipeline by asserting Restart_AN together with LMS change to ensure
* full pipeline reset * full pipeline reset. This function assumes the SW/FW lock is held.
**/ **/
s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
{ {
Context not available.
IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_FLUSH(hw);
} }
autoc_reg = hw->mac.cached_autoc; autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
autoc_reg |= IXGBE_AUTOC_AN_RESTART; autoc_reg |= IXGBE_AUTOC_AN_RESTART;
/* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN); IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
/* Wait for AN to leave state 0 */ /* Wait for AN to leave state 0 */
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
msec_delay(4); msec_delay(4);
Context not available.
} }
/**
* ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
* @data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface at
* a specified device address.
**/
static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)
{
u32 esdp;
s32 status;
s32 timeout = 200;
DEBUGFUNC("ixgbe_read_i2c_byte_82599");
if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
/* Acquire I2C bus ownership. */
esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
esdp |= IXGBE_ESDP_SDP0;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
IXGBE_WRITE_FLUSH(hw);
while (timeout) {
esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
if (esdp & IXGBE_ESDP_SDP1)
break;
msec_delay(5);
timeout--;
}
if (!timeout) {
DEBUGOUT("Driver can't access resource,"
" acquiring I2C bus timeout.\n");
status = IXGBE_ERR_I2C;
goto release_i2c_access;
}
}
status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
release_i2c_access:
if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
/* Release I2C bus ownership. */
esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
esdp &= ~IXGBE_ESDP_SDP0;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
IXGBE_WRITE_FLUSH(hw);
}
return status;
}
/**
* ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to write
* @data: value to write
*
* Performs byte write operation to SFP module's EEPROM over I2C interface at
* a specified device address.
**/
static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data)
{
u32 esdp;
s32 status;
s32 timeout = 200;
DEBUGFUNC("ixgbe_write_i2c_byte_82599");
if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
/* Acquire I2C bus ownership. */
esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
esdp |= IXGBE_ESDP_SDP0;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
IXGBE_WRITE_FLUSH(hw);
while (timeout) {
esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
if (esdp & IXGBE_ESDP_SDP1)
break;
msec_delay(5);
timeout--;
}
if (!timeout) {
DEBUGOUT("Driver can't access resource,"
" acquiring I2C bus timeout.\n");
status = IXGBE_ERR_I2C;
goto release_i2c_access;
}
}
status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
release_i2c_access:
if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
/* Release I2C bus ownership. */
esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
esdp &= ~IXGBE_ESDP_SDP0;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
IXGBE_WRITE_FLUSH(hw);
}
return status;
}
Context not available.