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Differential D10336 Diff 27331 sys/mips/mediatek/mtk_soc.c

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sys/mips/mediatek/mtk_soc.c

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#include <mips/mediatek/mtk_soc.h> #include <mips/mediatek/mtk_soc.h>
static uint32_t mtk_soc_socid = MTK_SOC_UNKNOWN; static uint32_t mtk_soc_socid = MTK_SOC_UNKNOWN;
static uint32_t mtk_soc_uartclk = 0; static uint32_t mtk_soc_uartclk = 0;
static uint32_t mtk_soc_cpuclk = MTK_CPU_CLK_880MHZ; static uint32_t mtk_soc_cpuclk = MTK_CPU_CLK_880MHZ;
static uint32_t mtk_soc_timerclk = MTK_CPU_CLK_880MHZ / 2; static uint32_t mtk_soc_timerclk = MTK_CPU_CLK_880MHZ / 2;
static const struct ofw_compat_data compat_data[] = { static const struct ofw_compat_data compat_data[] = {
{ "ralink,rt2880-soc", MTK_SOC_RT2880 },
{ "ralink,rt3050-soc", MTK_SOC_RT3050 }, { "ralink,rt3050-soc", MTK_SOC_RT3050 },
{ "ralink,rt3052-soc", MTK_SOC_RT3052 }, { "ralink,rt3052-soc", MTK_SOC_RT3052 },
{ "ralink,rt3350-soc", MTK_SOC_RT3350 }, { "ralink,rt3350-soc", MTK_SOC_RT3350 },
{ "ralink,rt3352-soc", MTK_SOC_RT3352 }, { "ralink,rt3352-soc", MTK_SOC_RT3352 },
{ "ralink,rt3662-soc", MTK_SOC_RT3662 }, { "ralink,rt3662-soc", MTK_SOC_RT3662 },
{ "ralink,rt3883-soc", MTK_SOC_RT3883 }, { "ralink,rt3883-soc", MTK_SOC_RT3883 },
{ "ralink,rt5350-soc", MTK_SOC_RT5350 }, { "ralink,rt5350-soc", MTK_SOC_RT5350 },
{ "ralink,mtk7620a-soc", MTK_SOC_MT7620A }, { "ralink,mtk7620a-soc", MTK_SOC_MT7620A },
{ "ralink,mt7620a-soc", MTK_SOC_MT7620A }, { "ralink,mt7620a-soc", MTK_SOC_MT7620A },
{ "ralink,mtk7620n-soc", MTK_SOC_MT7620N }, { "ralink,mtk7620n-soc", MTK_SOC_MT7620N },
{ "ralink,mt7620n-soc", MTK_SOC_MT7620N }, { "ralink,mt7620n-soc", MTK_SOC_MT7620N },
{ "mediatek,mtk7621-soc", MTK_SOC_MT7621 }, { "mediatek,mtk7621-soc", MTK_SOC_MT7621 },
{ "mediatek,mt7621-soc", MTK_SOC_MT7621 }, { "mediatek,mt7621-soc", MTK_SOC_MT7621 },
{ "ralink,mt7621-soc", MTK_SOC_MT7621 }, { "ralink,mt7621-soc", MTK_SOC_MT7621 },
{ "ralink,mtk7621-soc", MTK_SOC_MT7621 }, { "ralink,mtk7621-soc", MTK_SOC_MT7621 },
{ "ralink,mtk7628an-soc", MTK_SOC_MT7628 }, { "ralink,mtk7628an-soc", MTK_SOC_MT7628 },
{ "mediatek,mt7628an-soc", MTK_SOC_MT7628 }, { "mediatek,mt7628an-soc", MTK_SOC_MT7628 },
{ "ralink,mtk7688-soc", MTK_SOC_MT7688 }, { "ralink,mtk7688-soc", MTK_SOC_MT7688 },
/* Sentinel */ /* Sentinel */
{ NULL, MTK_SOC_UNKNOWN }, { NULL, MTK_SOC_UNKNOWN },
}; };
static uint32_t static uint32_t
mtk_detect_cpuclk_rt2880(bus_space_tag_t bst, bus_space_handle_t bsh)
{
uint32_t val;
val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
val >>= RT2880_CPU_CLKSEL_OFF;
val &= RT2880_CPU_CLKSEL_MSK;
switch (val) {
case 0:
return (MTK_CPU_CLK_250MHZ);
case 1:
return (MTK_CPU_CLK_266MHZ);
case 2:
return (MTK_CPU_CLK_280MHZ);
case 3:
return (MTK_CPU_CLK_300MHZ);
}
/* Never reached */
return (0);
}
static uint32_t
mtk_detect_cpuclk_rt305x(bus_space_tag_t bst, bus_space_handle_t bsh) mtk_detect_cpuclk_rt305x(bus_space_tag_t bst, bus_space_handle_t bsh)
{ {
uint32_t val; uint32_t val;
val = bus_space_read_4(bst, bsh, SYSCTL_CHIPID0_3); val = bus_space_read_4(bst, bsh, SYSCTL_CHIPID0_3);
if (val == RT3350_CHIPID0_3) if (val == RT3350_CHIPID0_3)
return (MTK_CPU_CLK_320MHZ); return (MTK_CPU_CLK_320MHZ);
▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Linesmtk_soc_try_early_detect(void)
} }
if (mtk_soc_socid == MTK_SOC_UNKNOWN) { if (mtk_soc_socid == MTK_SOC_UNKNOWN) {
/* We don't know the SoC, so we don't know how to get clocks */ /* We don't know the SoC, so we don't know how to get clocks */
return; return;
} }
bst = fdtbus_bs_tag; bst = fdtbus_bs_tag;
if (mtk_soc_socid == MTK_SOC_MT7621) if (mtk_soc_socid == MTK_SOC_RT2880)
base = MTK_RT2880_BASE;
else if (mtk_soc_socid == MTK_SOC_MT7621)
base = MTK_MT7621_BASE; base = MTK_MT7621_BASE;
else else
base = MTK_DEFAULT_BASE; base = MTK_DEFAULT_BASE;
if (bus_space_map(bst, base, MTK_DEFAULT_SIZE, 0, &bsh)) if (bus_space_map(bst, base, MTK_DEFAULT_SIZE, 0, &bsh))
return; return;
/* First, figure out the CPU clock */ /* First, figure out the CPU clock */
switch (mtk_soc_socid) { switch (mtk_soc_socid) {
case MTK_SOC_RT2880:
mtk_soc_cpuclk = mtk_detect_cpuclk_rt2880(bst, bsh);
break;
case MTK_SOC_RT3050: /* fallthrough */ case MTK_SOC_RT3050: /* fallthrough */
case MTK_SOC_RT3052: case MTK_SOC_RT3052:
case MTK_SOC_RT3350: case MTK_SOC_RT3350:
mtk_soc_cpuclk = mtk_detect_cpuclk_rt305x(bst, bsh); mtk_soc_cpuclk = mtk_detect_cpuclk_rt305x(bst, bsh);
break; break;
case MTK_SOC_RT3352: case MTK_SOC_RT3352:
mtk_soc_cpuclk = mtk_detect_cpuclk_rt3352(bst, bsh); mtk_soc_cpuclk = mtk_detect_cpuclk_rt3352(bst, bsh);
break; break;
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines#endif
/* /*
* We use the MIPS ticker for the rest for now, so * We use the MIPS ticker for the rest for now, so
* the CPU clock is divided by 2 * the CPU clock is divided by 2
*/ */
mtk_soc_timerclk = mtk_soc_cpuclk / 2; mtk_soc_timerclk = mtk_soc_cpuclk / 2;
} }
switch (mtk_soc_socid) { switch (mtk_soc_socid) {
case MTK_SOC_RT2880:
mtk_soc_uartclk = mtk_soc_cpuclk / MTK_UARTDIV_2;
break;
case MTK_SOC_RT3350: /* fallthrough */ case MTK_SOC_RT3350: /* fallthrough */
case MTK_SOC_RT3050: /* fallthrough */ case MTK_SOC_RT3050: /* fallthrough */
case MTK_SOC_RT3052: case MTK_SOC_RT3052:
/* UART clock is CPU clock / 3 */ /* UART clock is CPU clock / 3 */
mtk_soc_uartclk = mtk_soc_cpuclk / MTK_UARTDIV_3; mtk_soc_uartclk = mtk_soc_cpuclk / MTK_UARTDIV_3;
break; break;
case MTK_SOC_RT3352: /* fallthrough */ case MTK_SOC_RT3352: /* fallthrough */
case MTK_SOC_RT3662: /* fallthrough */ case MTK_SOC_RT3662: /* fallthrough */
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