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sys/dev/ixgbe/ixgbe_x540.c
/****************************************************************************** | /****************************************************************************** | ||||
Copyright (c) 2001-2015, Intel Corporation | Copyright (c) 2001-2017, Intel Corporation | ||||
All rights reserved. | All rights reserved. | ||||
Redistribution and use in source and binary forms, with or without | Redistribution and use in source and binary forms, with or without | ||||
modification, are permitted provided that the following conditions are met: | modification, are permitted provided that the following conditions are met: | ||||
1. Redistributions of source code must retain the above copyright notice, | 1. Redistributions of source code must retain the above copyright notice, | ||||
this list of conditions and the following disclaimer. | this list of conditions and the following disclaimer. | ||||
2. Redistributions in binary form must reproduce the above copyright | 2. Redistributions in binary form must reproduce the above copyright | ||||
notice, this list of conditions and the following disclaimer in the | notice, this list of conditions and the following disclaimer in the | ||||
documentation and/or other materials provided with the distribution. | documentation and/or other materials provided with the distribution. | ||||
3. Neither the name of the Intel Corporation nor the names of its | 3. Neither the name of the Intel Corporation nor the names of its | ||||
contributors may be used to endorse or promote products derived from | contributors may be used to endorse or promote products derived from | ||||
this software without specific prior written permission. | this software without specific prior written permission. | ||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | ||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | ||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | ||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | ||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ||||
POSSIBILITY OF SUCH DAMAGE. | POSSIBILITY OF SUCH DAMAGE. | ||||
******************************************************************************/ | ******************************************************************************/ | ||||
/*$FreeBSD$*/ | /*$FreeBSD$*/ | ||||
#include "ixgbe_x540.h" | #include "ixgbe_x540.h" | ||||
#include "ixgbe_type.h" | #include "ixgbe_type.h" | ||||
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines | s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) | ||||
mac->ops.start_hw = ixgbe_start_hw_X540; | mac->ops.start_hw = ixgbe_start_hw_X540; | ||||
mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; | mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; | ||||
mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; | mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; | ||||
mac->ops.get_device_caps = ixgbe_get_device_caps_generic; | mac->ops.get_device_caps = ixgbe_get_device_caps_generic; | ||||
mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; | mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; | ||||
mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; | mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; | ||||
mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540; | mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540; | ||||
mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540; | mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540; | ||||
mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540; | |||||
mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; | mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; | ||||
mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; | mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; | ||||
/* RAR, Multicast, VLAN */ | /* RAR, Multicast, VLAN */ | ||||
mac->ops.set_vmdq = ixgbe_set_vmdq_generic; | mac->ops.set_vmdq = ixgbe_set_vmdq_generic; | ||||
mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; | mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; | ||||
mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; | mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; | ||||
mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; | mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; | ||||
mac->rar_highwater = 1; | mac->rar_highwater = 1; | ||||
mac->ops.set_vfta = ixgbe_set_vfta_generic; | mac->ops.set_vfta = ixgbe_set_vfta_generic; | ||||
mac->ops.set_vlvf = ixgbe_set_vlvf_generic; | mac->ops.set_vlvf = ixgbe_set_vlvf_generic; | ||||
mac->ops.clear_vfta = ixgbe_clear_vfta_generic; | mac->ops.clear_vfta = ixgbe_clear_vfta_generic; | ||||
mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; | mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; | ||||
mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; | mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; | ||||
mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; | mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; | ||||
/* Link */ | /* Link */ | ||||
mac->ops.get_link_capabilities = | mac->ops.get_link_capabilities = | ||||
ixgbe_get_copper_link_capabilities_generic; | ixgbe_get_copper_link_capabilities_generic; | ||||
mac->ops.setup_link = ixgbe_setup_mac_link_X540; | mac->ops.setup_link = ixgbe_setup_mac_link_X540; | ||||
mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; | mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; | ||||
mac->ops.check_link = ixgbe_check_mac_link_generic; | mac->ops.check_link = ixgbe_check_mac_link_generic; | ||||
mac->ops.bypass_rw = ixgbe_bypass_rw_generic; | |||||
mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; | |||||
mac->ops.bypass_set = ixgbe_bypass_set_generic; | |||||
mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; | |||||
mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; | mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; | ||||
mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; | mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; | ||||
mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; | mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; | ||||
mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; | mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; | ||||
mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; | mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; | ||||
mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; | mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; | ||||
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines | mac_reset_top: | ||||
hw->mac.num_rar_entries = 128; | hw->mac.num_rar_entries = 128; | ||||
hw->mac.ops.init_rx_addrs(hw); | hw->mac.ops.init_rx_addrs(hw); | ||||
/* Store the permanent SAN mac address */ | /* Store the permanent SAN mac address */ | ||||
hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); | hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); | ||||
/* Add the SAN MAC address to the RAR only if it's a valid address */ | /* Add the SAN MAC address to the RAR only if it's a valid address */ | ||||
if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { | if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { | ||||
hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, | |||||
hw->mac.san_addr, 0, IXGBE_RAH_AV); | |||||
/* Save the SAN MAC RAR index */ | /* Save the SAN MAC RAR index */ | ||||
hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; | hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; | ||||
hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, | |||||
hw->mac.san_addr, 0, IXGBE_RAH_AV); | |||||
/* clear VMDq pool/queue selection for this RAR */ | |||||
hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, | |||||
IXGBE_CLEAR_VMDQ_ALL); | |||||
/* Reserve the last RAR for the SAN MAC address */ | /* Reserve the last RAR for the SAN MAC address */ | ||||
hw->mac.num_rar_entries--; | hw->mac.num_rar_entries--; | ||||
} | } | ||||
/* Store the alternative WWNN/WWPN prefix */ | /* Store the alternative WWNN/WWPN prefix */ | ||||
hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, | hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, | ||||
&hw->mac.wwpn_prefix); | &hw->mac.wwpn_prefix); | ||||
Show All 26 Lines | |||||
} | } | ||||
/** | /** | ||||
* ixgbe_get_supported_physical_layer_X540 - Returns physical layer type | * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* | * | ||||
* Determines physical layer capabilities of the current configuration. | * Determines physical layer capabilities of the current configuration. | ||||
**/ | **/ | ||||
u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) | u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) | ||||
{ | { | ||||
u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | ||||
u16 ext_ability = 0; | u16 ext_ability = 0; | ||||
DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); | DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); | ||||
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, | ||||
IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); | IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); | ||||
if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) | if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) | ||||
physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; | ||||
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines | |||||
**/ | **/ | ||||
s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) | s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) | ||||
{ | { | ||||
u16 i, j; | u16 i, j; | ||||
u16 checksum = 0; | u16 checksum = 0; | ||||
u16 length = 0; | u16 length = 0; | ||||
u16 pointer = 0; | u16 pointer = 0; | ||||
u16 word = 0; | u16 word = 0; | ||||
u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM; | |||||
u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; | u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; | ||||
/* Do not use hw->eeprom.ops.read because we do not want to take | /* Do not use hw->eeprom.ops.read because we do not want to take | ||||
* the synchronization semaphores here. Instead use | * the synchronization semaphores here. Instead use | ||||
* ixgbe_read_eerd_generic | * ixgbe_read_eerd_generic | ||||
*/ | */ | ||||
DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); | DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); | ||||
/* Include 0x0-0x3F in the checksum */ | /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the | ||||
for (i = 0; i <= checksum_last_word; i++) { | * checksum itself | ||||
*/ | |||||
for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { | |||||
if (ixgbe_read_eerd_generic(hw, i, &word)) { | if (ixgbe_read_eerd_generic(hw, i, &word)) { | ||||
DEBUGOUT("EEPROM read failed\n"); | DEBUGOUT("EEPROM read failed\n"); | ||||
return IXGBE_ERR_EEPROM; | return IXGBE_ERR_EEPROM; | ||||
} | } | ||||
if (i != IXGBE_EEPROM_CHECKSUM) | |||||
checksum += word; | checksum += word; | ||||
} | } | ||||
/* Include all data from pointers 0x3, 0x6-0xE. This excludes the | /* Include all data from pointers 0x3, 0x6-0xE. This excludes the | ||||
* FW, PHY module, and PCIe Expansion/Option ROM pointers. | * FW, PHY module, and PCIe Expansion/Option ROM pointers. | ||||
*/ | */ | ||||
for (i = ptr_start; i < IXGBE_FW_PTR; i++) { | for (i = ptr_start; i < IXGBE_FW_PTR; i++) { | ||||
if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) | if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) | ||||
continue; | continue; | ||||
▲ Show 20 Lines • Show All 250 Lines • ▼ Show 20 Lines | if (mask & IXGBE_GSSR_SW_MNG_SM) | ||||
swmask |= IXGBE_GSSR_SW_MNG_SM; | swmask |= IXGBE_GSSR_SW_MNG_SM; | ||||
swmask |= swi2c_mask; | swmask |= swi2c_mask; | ||||
fwmask |= swi2c_mask << 2; | fwmask |= swi2c_mask << 2; | ||||
for (i = 0; i < timeout; i++) { | for (i = 0; i < timeout; i++) { | ||||
/* SW NVM semaphore bit is used for access to all | /* SW NVM semaphore bit is used for access to all | ||||
* SW_FW_SYNC bits (not just NVM) | * SW_FW_SYNC bits (not just NVM) | ||||
*/ | */ | ||||
if (ixgbe_get_swfw_sync_semaphore(hw)) | if (ixgbe_get_swfw_sync_semaphore(hw)) { | ||||
DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n"); | |||||
return IXGBE_ERR_SWFW_SYNC; | return IXGBE_ERR_SWFW_SYNC; | ||||
} | |||||
swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); | ||||
if (!(swfw_sync & (fwmask | swmask | hwmask))) { | if (!(swfw_sync & (fwmask | swmask | hwmask))) { | ||||
swfw_sync |= swmask; | swfw_sync |= swmask; | ||||
IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), | ||||
swfw_sync); | swfw_sync); | ||||
ixgbe_release_swfw_sync_semaphore(hw); | ixgbe_release_swfw_sync_semaphore(hw); | ||||
msec_delay(5); | |||||
return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
} | } | ||||
/* Firmware currently using resource (fwmask), hardware | /* Firmware currently using resource (fwmask), hardware | ||||
* currently using resource (hwmask), or other software | * currently using resource (hwmask), or other software | ||||
* thread currently using resource (swmask) | * thread currently using resource (swmask) | ||||
*/ | */ | ||||
ixgbe_release_swfw_sync_semaphore(hw); | ixgbe_release_swfw_sync_semaphore(hw); | ||||
msec_delay(5); | msec_delay(5); | ||||
} | } | ||||
/* Failed to get SW only semaphore */ | /* Failed to get SW only semaphore */ | ||||
if (swmask == IXGBE_GSSR_SW_MNG_SM) { | if (swmask == IXGBE_GSSR_SW_MNG_SM) { | ||||
ERROR_REPORT1(IXGBE_ERROR_POLLING, | ERROR_REPORT1(IXGBE_ERROR_POLLING, | ||||
"Failed to get SW only semaphore"); | "Failed to get SW only semaphore"); | ||||
return IXGBE_ERR_SWFW_SYNC; | return IXGBE_ERR_SWFW_SYNC; | ||||
} | } | ||||
/* If the resource is not released by the FW/HW the SW can assume that | /* If the resource is not released by the FW/HW the SW can assume that | ||||
* the FW/HW malfunctions. In that case the SW should set the SW bit(s) | * the FW/HW malfunctions. In that case the SW should set the SW bit(s) | ||||
* of the requested resource(s) while ignoring the corresponding FW/HW | * of the requested resource(s) while ignoring the corresponding FW/HW | ||||
* bits in the SW_FW_SYNC register. | * bits in the SW_FW_SYNC register. | ||||
*/ | */ | ||||
if (ixgbe_get_swfw_sync_semaphore(hw)) | if (ixgbe_get_swfw_sync_semaphore(hw)) { | ||||
DEBUGOUT("Failed to get NVM sempahore and register semaphore while forcefully ignoring FW sempahore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n"); | |||||
return IXGBE_ERR_SWFW_SYNC; | return IXGBE_ERR_SWFW_SYNC; | ||||
} | |||||
swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); | ||||
if (swfw_sync & (fwmask | hwmask)) { | if (swfw_sync & (fwmask | hwmask)) { | ||||
swfw_sync |= swmask; | swfw_sync |= swmask; | ||||
IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); | ||||
ixgbe_release_swfw_sync_semaphore(hw); | ixgbe_release_swfw_sync_semaphore(hw); | ||||
msec_delay(5); | msec_delay(5); | ||||
return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
} | } | ||||
Show All 36 Lines | if (mask & IXGBE_GSSR_I2C_MASK) | ||||
swmask |= mask & IXGBE_GSSR_I2C_MASK; | swmask |= mask & IXGBE_GSSR_I2C_MASK; | ||||
ixgbe_get_swfw_sync_semaphore(hw); | ixgbe_get_swfw_sync_semaphore(hw); | ||||
swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); | ||||
swfw_sync &= ~swmask; | swfw_sync &= ~swmask; | ||||
IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); | ||||
ixgbe_release_swfw_sync_semaphore(hw); | ixgbe_release_swfw_sync_semaphore(hw); | ||||
msec_delay(5); | msec_delay(2); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_get_swfw_sync_semaphore - Get hardware semaphore | * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* | * | ||||
* Sets the hardware semaphores so SW/FW can gain control of shared resources | * Sets the hardware semaphores so SW/FW can gain control of shared resources | ||||
**/ | **/ | ||||
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines | static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) | ||||
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); | ||||
swsm &= ~IXGBE_SWSM_SMBI; | swsm &= ~IXGBE_SWSM_SMBI; | ||||
IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); | IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); | ||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_init_swfw_sync_X540 - Release hardware semaphore | |||||
* @hw: pointer to hardware structure | |||||
* | |||||
* This function reset hardware semaphore bits for a semaphore that may | |||||
* have be left locked due to a catastrophic failure. | |||||
**/ | |||||
void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw) | |||||
{ | |||||
/* First try to grab the semaphore but we don't need to bother | |||||
* looking to see whether we got the lock or not since we do | |||||
* the same thing regardless of whether we got the lock or not. | |||||
* We got the lock - we release it. | |||||
* We timeout trying to get the lock - we force its release. | |||||
*/ | |||||
ixgbe_get_swfw_sync_semaphore(hw); | |||||
ixgbe_release_swfw_sync_semaphore(hw); | |||||
} | |||||
/** | |||||
* ixgbe_blink_led_start_X540 - Blink LED based on index. | * ixgbe_blink_led_start_X540 - Blink LED based on index. | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @index: led number to blink | * @index: led number to blink | ||||
* | * | ||||
* Devices that implement the version 2 interface: | * Devices that implement the version 2 interface: | ||||
* X540 | * X540 | ||||
**/ | **/ | ||||
s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) | s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) | ||||
{ | { | ||||
u32 macc_reg; | u32 macc_reg; | ||||
u32 ledctl_reg; | u32 ledctl_reg; | ||||
ixgbe_link_speed speed; | ixgbe_link_speed speed; | ||||
bool link_up; | bool link_up; | ||||
DEBUGFUNC("ixgbe_blink_led_start_X540"); | DEBUGFUNC("ixgbe_blink_led_start_X540"); | ||||
if (index > 3) | |||||
return IXGBE_ERR_PARAM; | |||||
/* | /* | ||||
* Link should be up in order for the blink bit in the LED control | * Link should be up in order for the blink bit in the LED control | ||||
* register to work. Force link and speed in the MAC if link is down. | * register to work. Force link and speed in the MAC if link is down. | ||||
* This will be reversed when we stop the blinking. | * This will be reversed when we stop the blinking. | ||||
*/ | */ | ||||
hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); | hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); | ||||
if (link_up == FALSE) { | if (link_up == FALSE) { | ||||
macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); | macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); | ||||
Show All 17 Lines | |||||
* | * | ||||
* Devices that implement the version 2 interface: | * Devices that implement the version 2 interface: | ||||
* X540 | * X540 | ||||
**/ | **/ | ||||
s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) | s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) | ||||
{ | { | ||||
u32 macc_reg; | u32 macc_reg; | ||||
u32 ledctl_reg; | u32 ledctl_reg; | ||||
if (index > 3) | |||||
return IXGBE_ERR_PARAM; | |||||
DEBUGFUNC("ixgbe_blink_led_stop_X540"); | DEBUGFUNC("ixgbe_blink_led_stop_X540"); | ||||
/* Restore the LED to its default value. */ | /* Restore the LED to its default value. */ | ||||
ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | ||||
ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); | ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); | ||||
ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); | ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); | ||||
ledctl_reg &= ~IXGBE_LED_BLINK(index); | ledctl_reg &= ~IXGBE_LED_BLINK(index); | ||||
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