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sys/dev/ixgbe/ixgbe_type.h

/****************************************************************************** /******************************************************************************
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/*$FreeBSD$*/ /*$FreeBSD$*/
#ifndef _IXGBE_TYPE_H_ #ifndef _IXGBE_TYPE_H_
#define _IXGBE_TYPE_H_ #define _IXGBE_TYPE_H_
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#define IXGBE_DEV_ID_82599_CX4 0x10F9 #define IXGBE_DEV_ID_82599_CX4 0x10F9
#define IXGBE_DEV_ID_82599_SFP 0x10FB #define IXGBE_DEV_ID_82599_SFP 0x10FB
#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9 #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
#define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071 #define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071
#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72 #define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72
#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0 #define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470 #define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470
#define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B #define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B
#define IXGBE_SUBDEV_ID_82599_LOM_SFP 0x8976
#define IXGBE_SUBDEV_ID_82599_LOM_SNAP6 0x2159 #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6 0x2159
#define IXGBE_SUBDEV_ID_82599_SFP_1OCP 0x000D #define IXGBE_SUBDEV_ID_82599_SFP_1OCP 0x000D
#define IXGBE_SUBDEV_ID_82599_SFP_2OCP 0x0008 #define IXGBE_SUBDEV_ID_82599_SFP_2OCP 0x0008
#define IXGBE_SUBDEV_ID_82599_SFP_LOM 0x06EE #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1 0x8976
#define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2 0x06EE
#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529 #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
#define IXGBE_DEV_ID_82599_SFP_EM 0x1507 #define IXGBE_DEV_ID_82599_SFP_EM 0x1507
#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D #define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A #define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A
#define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558 #define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558
#define IXGBE_DEV_ID_82599EN_SFP 0x1557 #define IXGBE_DEV_ID_82599EN_SFP 0x1557
#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001 #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001
#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
#define IXGBE_DEV_ID_82599_T3_LOM 0x151C #define IXGBE_DEV_ID_82599_T3_LOM 0x151C
#define IXGBE_DEV_ID_82599_VF 0x10ED #define IXGBE_DEV_ID_82599_VF 0x10ED
#define IXGBE_DEV_ID_82599_VF_HV 0x152E #define IXGBE_DEV_ID_82599_VF_HV 0x152E
#define IXGBE_DEV_ID_82599_BYPASS 0x155D #define IXGBE_DEV_ID_82599_BYPASS 0x155D
#define IXGBE_DEV_ID_X540T 0x1528 #define IXGBE_DEV_ID_X540T 0x1528
#define IXGBE_DEV_ID_X540_VF 0x1515 #define IXGBE_DEV_ID_X540_VF 0x1515
#define IXGBE_DEV_ID_X540_VF_HV 0x1530 #define IXGBE_DEV_ID_X540_VF_HV 0x1530
#define IXGBE_DEV_ID_X540_BYPASS 0x155C #define IXGBE_DEV_ID_X540_BYPASS 0x155C
#define IXGBE_DEV_ID_X540T1 0x1560 #define IXGBE_DEV_ID_X540T1 0x1560
#define IXGBE_DEV_ID_X550T 0x1563 #define IXGBE_DEV_ID_X550T 0x1563
#define IXGBE_DEV_ID_X550T1 0x15D1 #define IXGBE_DEV_ID_X550T1 0x15D1
#define IXGBE_DEV_ID_X550EM_A_KR 0x15C2
#define IXGBE_DEV_ID_X550EM_A_KR_L 0x15C3
#define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4
#define IXGBE_DEV_ID_X550EM_A_SGMII 0x15C6
#define IXGBE_DEV_ID_X550EM_A_SGMII_L 0x15C7
#define IXGBE_DEV_ID_X550EM_A_10G_T 0x15C8
#define IXGBE_DEV_ID_X550EM_A_QSFP 0x15CA
#define IXGBE_DEV_ID_X550EM_A_QSFP_N 0x15CC
#define IXGBE_DEV_ID_X550EM_A_SFP 0x15CE
#define IXGBE_DEV_ID_X550EM_A_1G_T 0x15E4
#define IXGBE_DEV_ID_X550EM_A_1G_T_L 0x15E5
#define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA #define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA
#define IXGBE_DEV_ID_X550EM_X_KR 0x15AB #define IXGBE_DEV_ID_X550EM_X_KR 0x15AB
#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC #define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD #define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE #define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE
#define IXGBE_DEV_ID_X550EM_X_XFI 0x15B0
#define IXGBE_DEV_ID_X550_VF_HV 0x1564 #define IXGBE_DEV_ID_X550_VF_HV 0x1564
#define IXGBE_DEV_ID_X550_VF 0x1565 #define IXGBE_DEV_ID_X550_VF 0x1565
#define IXGBE_DEV_ID_X550EM_A_VF 0x15C5
#define IXGBE_DEV_ID_X550EM_A_VF_HV 0x15B4
#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9 #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
#define IXGBE_CAT(r,m) IXGBE_##r##m #define IXGBE_CAT(r,m) IXGBE_##r##m
#define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)]) #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)])
/* General Registers */ /* General Registers */
#define IXGBE_CTRL 0x00000 #define IXGBE_CTRL 0x00000
#define IXGBE_STATUS 0x00008 #define IXGBE_STATUS 0x00008
#define IXGBE_CTRL_EXT 0x00018 #define IXGBE_CTRL_EXT 0x00018
#define IXGBE_ESDP 0x00020 #define IXGBE_ESDP 0x00020
#define IXGBE_EODSDP 0x00028 #define IXGBE_EODSDP 0x00028
#define IXGBE_I2CCTL_82599 0x00028 #define IXGBE_I2CCTL_82599 0x00028
#define IXGBE_I2CCTL IXGBE_I2CCTL_82599 #define IXGBE_I2CCTL IXGBE_I2CCTL_82599
#define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_82599 #define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_82599
#define IXGBE_I2CCTL_X550 0x15F5C #define IXGBE_I2CCTL_X550 0x15F5C
#define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550 #define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550
#define IXGBE_I2CCTL_X550EM_a IXGBE_I2CCTL_X550
#define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL) #define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL)
#define IXGBE_PHY_GPIO 0x00028 #define IXGBE_PHY_GPIO 0x00028
#define IXGBE_MAC_GPIO 0x00030 #define IXGBE_MAC_GPIO 0x00030
#define IXGBE_PHYINT_STATUS0 0x00100 #define IXGBE_PHYINT_STATUS0 0x00100
#define IXGBE_PHYINT_STATUS1 0x00104 #define IXGBE_PHYINT_STATUS1 0x00104
#define IXGBE_PHYINT_STATUS2 0x00108 #define IXGBE_PHYINT_STATUS2 0x00108
#define IXGBE_LEDCTL 0x00200 #define IXGBE_LEDCTL 0x00200
#define IXGBE_FRTIMER 0x00048 #define IXGBE_FRTIMER 0x00048
#define IXGBE_TCPTIMER 0x0004C #define IXGBE_TCPTIMER 0x0004C
#define IXGBE_CORESPARE 0x00600 #define IXGBE_CORESPARE 0x00600
#define IXGBE_EXVET 0x05078 #define IXGBE_EXVET 0x05078
/* NVM Registers */ /* NVM Registers */
#define IXGBE_EEC 0x10010 #define IXGBE_EEC 0x10010
#define IXGBE_EEC_X540 IXGBE_EEC #define IXGBE_EEC_X540 IXGBE_EEC
#define IXGBE_EEC_X550 IXGBE_EEC #define IXGBE_EEC_X550 IXGBE_EEC
#define IXGBE_EEC_X550EM_x IXGBE_EEC #define IXGBE_EEC_X550EM_x IXGBE_EEC
#define IXGBE_EEC_BY_MAC(_hw) IXGBE_EEC #define IXGBE_EEC_X550EM_a 0x15FF8
#define IXGBE_EEC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EEC)
#define IXGBE_EERD 0x10014 #define IXGBE_EERD 0x10014
#define IXGBE_EEWR 0x10018 #define IXGBE_EEWR 0x10018
#define IXGBE_FLA 0x1001C #define IXGBE_FLA 0x1001C
#define IXGBE_FLA_X540 IXGBE_FLA #define IXGBE_FLA_X540 IXGBE_FLA
#define IXGBE_FLA_X550 IXGBE_FLA #define IXGBE_FLA_X550 IXGBE_FLA
#define IXGBE_FLA_X550EM_x IXGBE_FLA #define IXGBE_FLA_X550EM_x IXGBE_FLA
#define IXGBE_FLA_BY_MAC(_hw) IXGBE_FLA #define IXGBE_FLA_X550EM_a 0x15F68
#define IXGBE_FLA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FLA)
#define IXGBE_EEMNGCTL 0x10110 #define IXGBE_EEMNGCTL 0x10110
#define IXGBE_EEMNGDATA 0x10114 #define IXGBE_EEMNGDATA 0x10114
#define IXGBE_FLMNGCTL 0x10118 #define IXGBE_FLMNGCTL 0x10118
#define IXGBE_FLMNGDATA 0x1011C #define IXGBE_FLMNGDATA 0x1011C
#define IXGBE_FLMNGCNT 0x10120 #define IXGBE_FLMNGCNT 0x10120
#define IXGBE_FLOP 0x1013C #define IXGBE_FLOP 0x1013C
#define IXGBE_GRC 0x10200 #define IXGBE_GRC 0x10200
#define IXGBE_GRC_X540 IXGBE_GRC #define IXGBE_GRC_X540 IXGBE_GRC
#define IXGBE_GRC_X550 IXGBE_GRC #define IXGBE_GRC_X550 IXGBE_GRC
#define IXGBE_GRC_X550EM_x IXGBE_GRC #define IXGBE_GRC_X550EM_x IXGBE_GRC
#define IXGBE_GRC_BY_MAC(_hw) IXGBE_GRC #define IXGBE_GRC_X550EM_a 0x15F64
#define IXGBE_GRC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), GRC)
#define IXGBE_SRAMREL 0x10210 #define IXGBE_SRAMREL 0x10210
#define IXGBE_SRAMREL_X540 IXGBE_SRAMREL #define IXGBE_SRAMREL_X540 IXGBE_SRAMREL
#define IXGBE_SRAMREL_X550 IXGBE_SRAMREL #define IXGBE_SRAMREL_X550 IXGBE_SRAMREL
#define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL #define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL
#define IXGBE_SRAMREL_BY_MAC(_hw) IXGBE_SRAMREL #define IXGBE_SRAMREL_X550EM_a 0x15F6C
#define IXGBE_SRAMREL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SRAMREL)
#define IXGBE_PHYDBG 0x10218 #define IXGBE_PHYDBG 0x10218
/* General Receive Control */ /* General Receive Control */
#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
#define IXGBE_VPDDIAG0 0x10204 #define IXGBE_VPDDIAG0 0x10204
#define IXGBE_VPDDIAG1 0x10208 #define IXGBE_VPDDIAG1 0x10208
/* I2CCTL Bit Masks */ /* I2CCTL Bit Masks */
#define IXGBE_I2C_CLK_IN 0x00000001 #define IXGBE_I2C_CLK_IN 0x00000001
#define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN #define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN
#define IXGBE_I2C_CLK_IN_X550 0x00004000 #define IXGBE_I2C_CLK_IN_X550 0x00004000
#define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550 #define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550
#define IXGBE_I2C_CLK_IN_X550EM_a IXGBE_I2C_CLK_IN_X550
#define IXGBE_I2C_CLK_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN) #define IXGBE_I2C_CLK_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN)
#define IXGBE_I2C_CLK_OUT 0x00000002 #define IXGBE_I2C_CLK_OUT 0x00000002
#define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT #define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT
#define IXGBE_I2C_CLK_OUT_X550 0x00000200 #define IXGBE_I2C_CLK_OUT_X550 0x00000200
#define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550 #define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550
#define IXGBE_I2C_CLK_OUT_X550EM_a IXGBE_I2C_CLK_OUT_X550
#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT) #define IXGBE_I2C_CLK_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
#define IXGBE_I2C_DATA_IN 0x00000004 #define IXGBE_I2C_DATA_IN 0x00000004
#define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN #define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN
#define IXGBE_I2C_DATA_IN_X550 0x00001000 #define IXGBE_I2C_DATA_IN_X550 0x00001000
#define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550 #define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550
#define IXGBE_I2C_DATA_IN_X550EM_a IXGBE_I2C_DATA_IN_X550
#define IXGBE_I2C_DATA_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN) #define IXGBE_I2C_DATA_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN)
#define IXGBE_I2C_DATA_OUT 0x00000008 #define IXGBE_I2C_DATA_OUT 0x00000008
#define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT #define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT
#define IXGBE_I2C_DATA_OUT_X550 0x00000400 #define IXGBE_I2C_DATA_OUT_X550 0x00000400
#define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550 #define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550
#define IXGBE_I2C_DATA_OUT_X550EM_a IXGBE_I2C_DATA_OUT_X550
#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT) #define IXGBE_I2C_DATA_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
#define IXGBE_I2C_DATA_OE_N_EN 0 #define IXGBE_I2C_DATA_OE_N_EN 0
#define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN #define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN
#define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800 #define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800
#define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550
#define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550
#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN) #define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
#define IXGBE_I2C_BB_EN 0 #define IXGBE_I2C_BB_EN 0
#define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN #define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN
#define IXGBE_I2C_BB_EN_X550 0x00000100 #define IXGBE_I2C_BB_EN_X550 0x00000100
#define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550 #define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550
#define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550
#define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN) #define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN)
#define IXGBE_I2C_CLK_OE_N_EN 0 #define IXGBE_I2C_CLK_OE_N_EN 0
#define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN #define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN
#define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000 #define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000
#define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550
#define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550
#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN) #define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
/* Interrupt Registers */ /* Interrupt Registers */
#define IXGBE_EICR 0x00800 #define IXGBE_EICR 0x00800
#define IXGBE_EICS 0x00808 #define IXGBE_EICS 0x00808
#define IXGBE_EIMS 0x00880 #define IXGBE_EIMS 0x00880
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#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
#define IXGBE_WUPL 0x05900 #define IXGBE_WUPL 0x05900
#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
#define IXGBE_PROXYS 0x05F60 /* Proxying Status Register */ #define IXGBE_PROXYS 0x05F60 /* Proxying Status Register */
#define IXGBE_PROXYFC 0x05F64 /* Proxying Filter Control Register */ #define IXGBE_PROXYFC 0x05F64 /* Proxying Filter Control Register */
#define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */ #define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */
/* masks for accessing VXLAN and GENEVE UDP ports */
#define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff /* VXLAN port */
#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000 /* GENEVE port */
#define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff /* GENEVE/VXLAN */
#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16
#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */ #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
/* Ext Flexible Host Filter Table */ /* Ext Flexible Host Filter Table */
#define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) #define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100))
#define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100)) #define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100))
/* Four Flexible Filters are supported */ /* Four Flexible Filters are supported */
#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
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#define IXGBE_MANC2H 0x05860 #define IXGBE_MANC2H 0x05860
#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
#define IXGBE_MIPAF 0x058B0 #define IXGBE_MIPAF 0x058B0
#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
#define IXGBE_LSWFW 0x15014 #define IXGBE_LSWFW 0x15F14
#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */ #define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
#define IXGBE_BMCIPVAL 0x05060 #define IXGBE_BMCIPVAL 0x05060
#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001 #define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
#define IXGBE_BMCIP_IPADDR_VALID 0x00000002 #define IXGBE_BMCIP_IPADDR_VALID 0x00000002
/* Management Bit Fields and Masks */ /* Management Bit Fields and Masks */
#define IXGBE_MANC_MPROXYE 0x40000000 /* Management Proxy Enable */ #define IXGBE_MANC_MPROXYE 0x40000000 /* Management Proxy Enable */
#define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */ #define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */
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#define IXGBE_GCR 0x11000 #define IXGBE_GCR 0x11000
#define IXGBE_GTV 0x11004 #define IXGBE_GTV 0x11004
#define IXGBE_FUNCTAG 0x11008 #define IXGBE_FUNCTAG 0x11008
#define IXGBE_GLT 0x1100C #define IXGBE_GLT 0x1100C
#define IXGBE_PCIEPIPEADR 0x11004 #define IXGBE_PCIEPIPEADR 0x11004
#define IXGBE_PCIEPIPEDAT 0x11008 #define IXGBE_PCIEPIPEDAT 0x11008
#define IXGBE_GSCL_1 0x11010 #define IXGBE_GSCL_1 0x11010
#define IXGBE_GSCL_2 0x11014 #define IXGBE_GSCL_2 0x11014
#define IXGBE_GSCL_1_X540 IXGBE_GSCL_1
#define IXGBE_GSCL_2_X540 IXGBE_GSCL_2
#define IXGBE_GSCL_3 0x11018 #define IXGBE_GSCL_3 0x11018
#define IXGBE_GSCL_4 0x1101C #define IXGBE_GSCL_4 0x1101C
#define IXGBE_GSCN_0 0x11020 #define IXGBE_GSCN_0 0x11020
#define IXGBE_GSCN_1 0x11024 #define IXGBE_GSCN_1 0x11024
#define IXGBE_GSCN_2 0x11028 #define IXGBE_GSCN_2 0x11028
#define IXGBE_GSCN_3 0x1102C #define IXGBE_GSCN_3 0x1102C
#define IXGBE_GSCN_0_X540 IXGBE_GSCN_0
#define IXGBE_GSCN_1_X540 IXGBE_GSCN_1
#define IXGBE_GSCN_2_X540 IXGBE_GSCN_2
#define IXGBE_GSCN_3_X540 IXGBE_GSCN_3
#define IXGBE_FACTPS 0x10150 #define IXGBE_FACTPS 0x10150
#define IXGBE_FACTPS_X540 IXGBE_FACTPS #define IXGBE_FACTPS_X540 IXGBE_FACTPS
#define IXGBE_GSCL_1_X550 0x11800
#define IXGBE_GSCL_2_X550 0x11804
#define IXGBE_GSCL_1_X550EM_x IXGBE_GSCL_1_X550
#define IXGBE_GSCL_2_X550EM_x IXGBE_GSCL_2_X550
#define IXGBE_GSCN_0_X550 0x11820
#define IXGBE_GSCN_1_X550 0x11824
#define IXGBE_GSCN_2_X550 0x11828
#define IXGBE_GSCN_3_X550 0x1182C
#define IXGBE_GSCN_0_X550EM_x IXGBE_GSCN_0_X550
#define IXGBE_GSCN_1_X550EM_x IXGBE_GSCN_1_X550
#define IXGBE_GSCN_2_X550EM_x IXGBE_GSCN_2_X550
#define IXGBE_GSCN_3_X550EM_x IXGBE_GSCN_3_X550
#define IXGBE_FACTPS_X550 IXGBE_FACTPS #define IXGBE_FACTPS_X550 IXGBE_FACTPS
#define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS #define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS
#define IXGBE_FACTPS_BY_MAC(_hw) IXGBE_FACTPS #define IXGBE_GSCL_1_X550EM_a IXGBE_GSCL_1_X550
#define IXGBE_GSCL_2_X550EM_a IXGBE_GSCL_2_X550
#define IXGBE_GSCN_0_X550EM_a IXGBE_GSCN_0_X550
#define IXGBE_GSCN_1_X550EM_a IXGBE_GSCN_1_X550
#define IXGBE_GSCN_2_X550EM_a IXGBE_GSCN_2_X550
#define IXGBE_GSCN_3_X550EM_a IXGBE_GSCN_3_X550
#define IXGBE_FACTPS_X550EM_a 0x15FEC
#define IXGBE_FACTPS_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FACTPS)
#define IXGBE_PCIEANACTL 0x11040 #define IXGBE_PCIEANACTL 0x11040
#define IXGBE_SWSM 0x10140 #define IXGBE_SWSM 0x10140
#define IXGBE_SWSM_X540 IXGBE_SWSM #define IXGBE_SWSM_X540 IXGBE_SWSM
#define IXGBE_SWSM_X550 IXGBE_SWSM #define IXGBE_SWSM_X550 IXGBE_SWSM
#define IXGBE_SWSM_X550EM_x IXGBE_SWSM #define IXGBE_SWSM_X550EM_x IXGBE_SWSM
#define IXGBE_SWSM_BY_MAC(_hw) IXGBE_SWSM #define IXGBE_SWSM_X550EM_a 0x15F70
#define IXGBE_SWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWSM)
#define IXGBE_FWSM 0x10148 #define IXGBE_FWSM 0x10148
#define IXGBE_FWSM_X540 IXGBE_FWSM #define IXGBE_FWSM_X540 IXGBE_FWSM
#define IXGBE_FWSM_X550 IXGBE_FWSM #define IXGBE_FWSM_X550 IXGBE_FWSM
#define IXGBE_FWSM_X550EM_x IXGBE_FWSM #define IXGBE_FWSM_X550EM_x IXGBE_FWSM
#define IXGBE_FWSM_BY_MAC(_hw) IXGBE_FWSM #define IXGBE_FWSM_X550EM_a 0x15F74
#define IXGBE_FWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FWSM)
#define IXGBE_SWFW_SYNC IXGBE_GSSR #define IXGBE_SWFW_SYNC IXGBE_GSSR
#define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC #define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC
#define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC #define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC
#define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC #define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC
#define IXGBE_SWFW_SYNC_BY_MAC(_hw) IXGBE_SWFW_SYNC #define IXGBE_SWFW_SYNC_X550EM_a 0x15F78
#define IXGBE_SWFW_SYNC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWFW_SYNC)
#define IXGBE_GSSR 0x10160 #define IXGBE_GSSR 0x10160
#define IXGBE_MREVID 0x11064 #define IXGBE_MREVID 0x11064
#define IXGBE_DCA_ID 0x11070 #define IXGBE_DCA_ID 0x11070
#define IXGBE_DCA_CTRL 0x11074 #define IXGBE_DCA_CTRL 0x11074
/* PCI-E registers 82599-Specific */ /* PCI-E registers 82599-Specific */
#define IXGBE_GCR_EXT 0x11050 #define IXGBE_GCR_EXT 0x11050
#define IXGBE_GSCL_5_82599 0x11030 #define IXGBE_GSCL_5_82599 0x11030
#define IXGBE_GSCL_6_82599 0x11034 #define IXGBE_GSCL_6_82599 0x11034
#define IXGBE_GSCL_7_82599 0x11038 #define IXGBE_GSCL_7_82599 0x11038
#define IXGBE_GSCL_8_82599 0x1103C #define IXGBE_GSCL_8_82599 0x1103C
#define IXGBE_GSCL_5_X540 IXGBE_GSCL_5_82599
#define IXGBE_GSCL_6_X540 IXGBE_GSCL_6_82599
#define IXGBE_GSCL_7_X540 IXGBE_GSCL_7_82599
#define IXGBE_GSCL_8_X540 IXGBE_GSCL_8_82599
#define IXGBE_PHYADR_82599 0x11040 #define IXGBE_PHYADR_82599 0x11040
#define IXGBE_PHYDAT_82599 0x11044 #define IXGBE_PHYDAT_82599 0x11044
#define IXGBE_PHYCTL_82599 0x11048 #define IXGBE_PHYCTL_82599 0x11048
#define IXGBE_PBACLR_82599 0x11068 #define IXGBE_PBACLR_82599 0x11068
#define IXGBE_CIAA 0x11088 #define IXGBE_CIAA 0x11088
#define IXGBE_CIAD 0x1108C #define IXGBE_CIAD 0x1108C
#define IXGBE_CIAA_82599 IXGBE_CIAA #define IXGBE_CIAA_82599 IXGBE_CIAA
#define IXGBE_CIAD_82599 IXGBE_CIAD #define IXGBE_CIAD_82599 IXGBE_CIAD
#define IXGBE_CIAA_X540 IXGBE_CIAA #define IXGBE_CIAA_X540 IXGBE_CIAA
#define IXGBE_CIAD_X540 IXGBE_CIAD #define IXGBE_CIAD_X540 IXGBE_CIAD
#define IXGBE_GSCL_5_X550 0x11810
#define IXGBE_GSCL_6_X550 0x11814
#define IXGBE_GSCL_7_X550 0x11818
#define IXGBE_GSCL_8_X550 0x1181C
#define IXGBE_GSCL_5_X550EM_x IXGBE_GSCL_5_X550
#define IXGBE_GSCL_6_X550EM_x IXGBE_GSCL_6_X550
#define IXGBE_GSCL_7_X550EM_x IXGBE_GSCL_7_X550
#define IXGBE_GSCL_8_X550EM_x IXGBE_GSCL_8_X550
#define IXGBE_CIAA_X550 0x11508 #define IXGBE_CIAA_X550 0x11508
#define IXGBE_CIAD_X550 0x11510 #define IXGBE_CIAD_X550 0x11510
#define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550 #define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550
#define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550 #define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550
#define IXGBE_GSCL_5_X550EM_a IXGBE_GSCL_5_X550
#define IXGBE_GSCL_6_X550EM_a IXGBE_GSCL_6_X550
#define IXGBE_GSCL_7_X550EM_a IXGBE_GSCL_7_X550
#define IXGBE_GSCL_8_X550EM_a IXGBE_GSCL_8_X550
#define IXGBE_CIAA_X550EM_a IXGBE_CIAA_X550
#define IXGBE_CIAD_X550EM_a IXGBE_CIAD_X550
#define IXGBE_CIAA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAA) #define IXGBE_CIAA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAA)
#define IXGBE_CIAD_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAD) #define IXGBE_CIAD_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAD)
#define IXGBE_PICAUSE 0x110B0 #define IXGBE_PICAUSE 0x110B0
#define IXGBE_PIENA 0x110B8 #define IXGBE_PIENA 0x110B8
#define IXGBE_CDQ_MBR_82599 0x110B4 #define IXGBE_CDQ_MBR_82599 0x110B4
#define IXGBE_PCIESPARE 0x110BC #define IXGBE_PCIESPARE 0x110BC
#define IXGBE_MISC_REG_82599 0x110F0 #define IXGBE_MISC_REG_82599 0x110F0
#define IXGBE_ECC_CTRL_0_82599 0x11100 #define IXGBE_ECC_CTRL_0_82599 0x11100
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#define IXGBE_MHADD 0x04268 #define IXGBE_MHADD 0x04268
#define IXGBE_MAXFRS 0x04268 #define IXGBE_MAXFRS 0x04268
#define IXGBE_TREG 0x0426C #define IXGBE_TREG 0x0426C
#define IXGBE_PCSS1 0x04288 #define IXGBE_PCSS1 0x04288
#define IXGBE_PCSS2 0x0428C #define IXGBE_PCSS2 0x0428C
#define IXGBE_XPCSS 0x04290 #define IXGBE_XPCSS 0x04290
#define IXGBE_MFLCN 0x04294 #define IXGBE_MFLCN 0x04294
#define IXGBE_SERDESC 0x04298 #define IXGBE_SERDESC 0x04298
#define IXGBE_MAC_SGMII_BUSY 0x04298
#define IXGBE_MACS 0x0429C #define IXGBE_MACS 0x0429C
#define IXGBE_AUTOC 0x042A0 #define IXGBE_AUTOC 0x042A0
#define IXGBE_LINKS 0x042A4 #define IXGBE_LINKS 0x042A4
#define IXGBE_LINKS2 0x04324 #define IXGBE_LINKS2 0x04324
#define IXGBE_AUTOC2 0x042A8 #define IXGBE_AUTOC2 0x042A8
#define IXGBE_AUTOC3 0x042AC #define IXGBE_AUTOC3 0x042AC
#define IXGBE_ANLP1 0x042B0 #define IXGBE_ANLP1 0x042B0
#define IXGBE_ANLP2 0x042B4 #define IXGBE_ANLP2 0x042B4
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#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
/* Omer bit masks */ /* Omer bit masks */
#define IXGBE_CORECTL_WRITE_CMD 0x00010000 #define IXGBE_CORECTL_WRITE_CMD 0x00010000
/* Device Type definitions for new protocol MDIO commands */ /* Device Type definitions for new protocol MDIO commands */
#define IXGBE_MDIO_ZERO_DEV_TYPE 0x0
#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
#define IXGBE_MDIO_PCS_DEV_TYPE 0x3 #define IXGBE_MDIO_PCS_DEV_TYPE 0x3
#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 #define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
#define IXGBE_TWINAX_DEV 1 #define IXGBE_TWINAX_DEV 1
#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
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#define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850 /* Global Fault Message */ #define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850 /* Global Fault Message */
#define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007 /* high temp failure */ #define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007 /* high temp failure */
#define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400 /* Global int mask */ #define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400 /* Global int mask */
#define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000 /* autoneg vendor alarm int enable */ #define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000 /* autoneg vendor alarm int enable */
#define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4 /* int in Global alarm 1 */ #define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4 /* int in Global alarm 1 */
#define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1 /* vendor alarm int enable */ #define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1 /* vendor alarm int enable */
#define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200 /* vendor alarm2 int mask */ #define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200 /* vendor alarm2 int mask */
#define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000 /* int high temp enable */ #define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000 /* int high temp enable */
#define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010 /* int dev fault enable */
#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */ #define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */ #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */
#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */ #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */
#define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */ #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */
#define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */ #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */
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#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
#define IXGBE_MAX_PHY_ADDR 32 #define IXGBE_MAX_PHY_ADDR 32
/* PHY IDs*/ /* PHY IDs*/
#define TN1010_PHY_ID 0x00A19410 #define TN1010_PHY_ID 0x00A19410
#define TNX_FW_REV 0xB #define TNX_FW_REV 0xB
#define X540_PHY_ID 0x01540200 #define X540_PHY_ID 0x01540200
#define X550_PHY_ID1 0x01540220
#define X550_PHY_ID2 0x01540223 #define X550_PHY_ID2 0x01540223
#define X550_PHY_ID3 0x01540221 #define X550_PHY_ID3 0x01540221
#define X557_PHY_ID 0x01540240 #define X557_PHY_ID 0x01540240
#define X557_PHY_ID2 0x01540250
#define AQ_FW_REV 0x20 #define AQ_FW_REV 0x20
#define QT2022_PHY_ID 0x0043A400 #define QT2022_PHY_ID 0x0043A400
#define ATH_PHY_ID 0x03429050 #define ATH_PHY_ID 0x03429050
/* PHY Types */ /* PHY Types */
#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 #define IXGBE_M88E1500_E_PHY_ID 0x01410DD0
#define IXGBE_M88E1543_E_PHY_ID 0x01410EA0
/* Special PHY Init Routine */ /* Special PHY Init Routine */
#define IXGBE_PHY_INIT_OFFSET_NL 0x002B #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
#define IXGBE_PHY_INIT_END_NL 0xFFFF #define IXGBE_PHY_INIT_END_NL 0xFFFF
#define IXGBE_CONTROL_MASK_NL 0xF000 #define IXGBE_CONTROL_MASK_NL 0xF000
#define IXGBE_DATA_MASK_NL 0x0FFF #define IXGBE_DATA_MASK_NL 0x0FFF
#define IXGBE_CONTROL_SHIFT_NL 12 #define IXGBE_CONTROL_SHIFT_NL 12
#define IXGBE_DELAY_NL 0 #define IXGBE_DELAY_NL 0
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#define IXGBE_SDP1_GPIEN_X540 0x00000004 /* SDP1 on X540 and X550 */ #define IXGBE_SDP1_GPIEN_X540 0x00000004 /* SDP1 on X540 and X550 */
#define IXGBE_SDP2_GPIEN_X540 0x00000008 /* SDP2 on X540 and X550 */ #define IXGBE_SDP2_GPIEN_X540 0x00000008 /* SDP2 on X540 and X550 */
#define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540 #define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540
#define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540 #define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540
#define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540 #define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540
#define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540 #define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540
#define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540 #define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540
#define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540 #define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540
#define IXGBE_SDP0_GPIEN_X550EM_a IXGBE_SDP0_GPIEN_X540
#define IXGBE_SDP1_GPIEN_X550EM_a IXGBE_SDP1_GPIEN_X540
#define IXGBE_SDP2_GPIEN_X550EM_a IXGBE_SDP2_GPIEN_X540
#define IXGBE_SDP0_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN) #define IXGBE_SDP0_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN)
#define IXGBE_SDP1_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN) #define IXGBE_SDP1_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN)
#define IXGBE_SDP2_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN) #define IXGBE_SDP2_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN)
#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
#define IXGBE_GPIE_EIAME 0x40000000 #define IXGBE_GPIE_EIAME 0x40000000
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/* VT_CTL bitmasks */ /* VT_CTL bitmasks */
#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
#define IXGBE_VT_CTL_POOL_SHIFT 7 #define IXGBE_VT_CTL_POOL_SHIFT 7
#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
/* VMOLR bitmasks */ /* VMOLR bitmasks */
#define IXGBE_VMOLR_UPE 0x00400000 /* unicast promiscuous */
#define IXGBE_VMOLR_VPE 0x00800000 /* VLAN promiscuous */
#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
/* VFRE bitmask */ /* VFRE bitmask */
#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
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#define IXGBE_EICR_GPI_SDP1_X540 0x04000000 /* Gen Purpose Interrupt on SDP1 */ #define IXGBE_EICR_GPI_SDP1_X540 0x04000000 /* Gen Purpose Interrupt on SDP1 */
#define IXGBE_EICR_GPI_SDP2_X540 0x08000000 /* Gen Purpose Interrupt on SDP2 */ #define IXGBE_EICR_GPI_SDP2_X540 0x08000000 /* Gen Purpose Interrupt on SDP2 */
#define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540 #define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540
#define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540 #define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540
#define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540 #define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540
#define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540 #define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540
#define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540 #define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540
#define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540 #define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540
#define IXGBE_EICR_GPI_SDP0_X550EM_a IXGBE_EICR_GPI_SDP0_X540
#define IXGBE_EICR_GPI_SDP1_X550EM_a IXGBE_EICR_GPI_SDP1_X540
#define IXGBE_EICR_GPI_SDP2_X550EM_a IXGBE_EICR_GPI_SDP2_X540
#define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0) #define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
#define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1) #define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
#define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2) #define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
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#define IXGBE_LINKS_TL_FAULT 0x00001000 #define IXGBE_LINKS_TL_FAULT 0x00001000
#define IXGBE_LINKS_SIGNAL 0x00000F00 #define IXGBE_LINKS_SIGNAL 0x00000F00
#define IXGBE_LINKS_SPEED_NON_STD 0x08000000 #define IXGBE_LINKS_SPEED_NON_STD 0x08000000
#define IXGBE_LINKS_SPEED_82599 0x30000000 #define IXGBE_LINKS_SPEED_82599 0x30000000
#define IXGBE_LINKS_SPEED_10G_82599 0x30000000 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
#define IXGBE_LINKS_SPEED_1G_82599 0x20000000 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000
#define IXGBE_LINKS_SPEED_100_82599 0x10000000 #define IXGBE_LINKS_SPEED_100_82599 0x10000000
#define IXGBE_LINKS_SPEED_10_X550EM_A 0x00000000
#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
/* PCS1GLSTA Bit Masks */ /* PCS1GLSTA Bit Masks */
#define IXGBE_PCS1GLSTA_LINK_OK 1 #define IXGBE_PCS1GLSTA_LINK_OK 1
#define IXGBE_PCS1GLSTA_SYNK_OK 0x10 #define IXGBE_PCS1GLSTA_SYNK_OK 0x10
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/* SW_FW_SYNC/GSSR definitions */ /* SW_FW_SYNC/GSSR definitions */
#define IXGBE_GSSR_EEP_SM 0x0001 #define IXGBE_GSSR_EEP_SM 0x0001
#define IXGBE_GSSR_PHY0_SM 0x0002 #define IXGBE_GSSR_PHY0_SM 0x0002
#define IXGBE_GSSR_PHY1_SM 0x0004 #define IXGBE_GSSR_PHY1_SM 0x0004
#define IXGBE_GSSR_MAC_CSR_SM 0x0008 #define IXGBE_GSSR_MAC_CSR_SM 0x0008
#define IXGBE_GSSR_FLASH_SM 0x0010 #define IXGBE_GSSR_FLASH_SM 0x0010
#define IXGBE_GSSR_NVM_UPDATE_SM 0x0200 #define IXGBE_GSSR_NVM_UPDATE_SM 0x0200
#define IXGBE_GSSR_SW_MNG_SM 0x0400 #define IXGBE_GSSR_SW_MNG_SM 0x0400
#define IXGBE_GSSR_TOKEN_SM 0x40000000 /* SW bit for shared access */
#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */ #define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */
#define IXGBE_GSSR_I2C_MASK 0x1800 #define IXGBE_GSSR_I2C_MASK 0x1800
#define IXGBE_GSSR_NVM_PHY_MASK 0xF #define IXGBE_GSSR_NVM_PHY_MASK 0xF
/* FW Status register bitmask */ /* FW Status register bitmask */
#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ #define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */
/* EEC Register */ /* EEC Register */
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/* Part Number String Length */ /* Part Number String Length */
#define IXGBE_PBANUM_LENGTH 11 #define IXGBE_PBANUM_LENGTH 11
/* Checksum and EEPROM pointers */ /* Checksum and EEPROM pointers */
#define IXGBE_PBANUM_PTR_GUARD 0xFAFA #define IXGBE_PBANUM_PTR_GUARD 0xFAFA
#define IXGBE_EEPROM_CHECKSUM 0x3F #define IXGBE_EEPROM_CHECKSUM 0x3F
#define IXGBE_EEPROM_SUM 0xBABA #define IXGBE_EEPROM_SUM 0xBABA
#define IXGBE_EEPROM_CTRL_4 0x45
#define IXGBE_EE_CTRL_4_INST_ID 0x10
#define IXGBE_EE_CTRL_4_INST_ID_SHIFT 4
#define IXGBE_PCIE_ANALOG_PTR 0x03 #define IXGBE_PCIE_ANALOG_PTR 0x03
#define IXGBE_ATLAS0_CONFIG_PTR 0x04 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
#define IXGBE_PHY_PTR 0x04 #define IXGBE_PHY_PTR 0x04
#define IXGBE_ATLAS1_CONFIG_PTR 0x05 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
#define IXGBE_OPTION_ROM_PTR 0x05 #define IXGBE_OPTION_ROM_PTR 0x05
#define IXGBE_PCIE_GENERAL_PTR 0x06 #define IXGBE_PCIE_GENERAL_PTR 0x06
#define IXGBE_PCIE_CONFIG0_PTR 0x07 #define IXGBE_PCIE_CONFIG0_PTR 0x07
#define IXGBE_PCIE_CONFIG1_PTR 0x08 #define IXGBE_PCIE_CONFIG1_PTR 0x08
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#define IXGBE_FW_PTR 0x0F #define IXGBE_FW_PTR 0x0F
#define IXGBE_PBANUM0_PTR 0x15 #define IXGBE_PBANUM0_PTR 0x15
#define IXGBE_PBANUM1_PTR 0x16 #define IXGBE_PBANUM1_PTR 0x16
#define IXGBE_ALT_MAC_ADDR_PTR 0x37 #define IXGBE_ALT_MAC_ADDR_PTR 0x37
#define IXGBE_FREE_SPACE_PTR 0X3E #define IXGBE_FREE_SPACE_PTR 0X3E
#define IXGBE_SAN_MAC_ADDR_PTR 0x28 #define IXGBE_SAN_MAC_ADDR_PTR 0x28
#define IXGBE_DEVICE_CAPS 0x2C #define IXGBE_DEVICE_CAPS 0x2C
#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 #define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR 0x11
#define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR 0x04
#define IXGBE_PCIE_MSIX_82599_CAPS 0x72 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72
#define IXGBE_MAX_MSIX_VECTORS_82599 0x40 #define IXGBE_MAX_MSIX_VECTORS_82599 0x40
#define IXGBE_PCIE_MSIX_82598_CAPS 0x62 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62
#define IXGBE_MAX_MSIX_VECTORS_82598 0x13 #define IXGBE_MAX_MSIX_VECTORS_82598 0x13
/* MSI-X capability fields masks */ /* MSI-X capability fields masks */
#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
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#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ #define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
#define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR (1 << 7)
#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 #define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
#define IXGBE_FW_LESM_STATE_1 0x1 #define IXGBE_FW_LESM_STATE_1 0x1
#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ #define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
#define IXGBE_FW_PATCH_VERSION_4 0x7 #define IXGBE_FW_PATCH_VERSION_4 0x7
#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */ #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */ #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */ #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */
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#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
#define IXGBE_MRQC_L3L4TXSWEN 0x00008000 /* Enable L3/L4 Tx switch */
#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
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#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
#define IXGBE_RXDADV_PKTTYPE_GENEVE 0x00000800 /* GENEVE hdr present */
#define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800 /* VXLAN hdr present */ #define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800 /* VXLAN hdr present */
#define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000 /* Tunnel type */ #define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000 /* Tunnel type */
#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines#define IXGBE_PVFRDT(P) ((P < 64) ? (0x01018 + (0x40 * (P))) \
: (0x0D018 + (0x40 * ((P) - 64)))) : (0x0D018 + (0x40 * ((P) - 64))))
#define IXGBE_PVFRXDCTL(P) ((P < 64) ? (0x01028 + (0x40 * (P))) \ #define IXGBE_PVFRXDCTL(P) ((P < 64) ? (0x01028 + (0x40 * (P))) \
: (0x0D028 + (0x40 * ((P) - 64)))) : (0x0D028 + (0x40 * ((P) - 64))))
#define IXGBE_PVFSRRCTL(P) ((P < 64) ? (0x01014 + (0x40 * (P))) \ #define IXGBE_PVFSRRCTL(P) ((P < 64) ? (0x01014 + (0x40 * (P))) \
: (0x0D014 + (0x40 * ((P) - 64)))) : (0x0D014 + (0x40 * ((P) - 64))))
#define IXGBE_PVFPSRTYPE(P) (0x0EA00 + (4 * (P))) #define IXGBE_PVFPSRTYPE(P) (0x0EA00 + (4 * (P)))
#define IXGBE_PVFTDBAL(P) (0x06000 + (0x40 * (P))) #define IXGBE_PVFTDBAL(P) (0x06000 + (0x40 * (P)))
#define IXGBE_PVFTDBAH(P) (0x06004 + (0x40 * (P))) #define IXGBE_PVFTDBAH(P) (0x06004 + (0x40 * (P)))
#define IXGBE_PVFTTDLEN(P) (0x06008 + (0x40 * (P))) #define IXGBE_PVFTDLEN(P) (0x06008 + (0x40 * (P)))
#define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P))) #define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P)))
#define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P))) #define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P)))
#define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P))) #define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P)))
#define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P))) #define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P)))
#define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P))) #define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P)))
#define IXGBE_PVFDCA_RXCTRL(P) (((P) < 64) ? (0x0100C + (0x40 * (P))) \ #define IXGBE_PVFDCA_RXCTRL(P) (((P) < 64) ? (0x0100C + (0x40 * (P))) \
: (0x0D00C + (0x40 * ((P) - 64)))) : (0x0D00C + (0x40 * ((P) - 64))))
#define IXGBE_PVFDCA_TXCTRL(P) (0x0600C + (0x40 * (P))) #define IXGBE_PVFDCA_TXCTRL(P) (0x0600C + (0x40 * (P)))
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/* CEM Support */ /* CEM Support */
#define FW_CEM_HDR_LEN 0x4 #define FW_CEM_HDR_LEN 0x4
#define FW_CEM_CMD_DRIVER_INFO 0xDD #define FW_CEM_CMD_DRIVER_INFO 0xDD
#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
#define FW_CEM_CMD_RESERVED 0X0 #define FW_CEM_CMD_RESERVED 0X0
#define FW_CEM_UNUSED_VER 0x0 #define FW_CEM_UNUSED_VER 0x0
#define FW_CEM_MAX_RETRIES 3 #define FW_CEM_MAX_RETRIES 3
#define FW_CEM_RESP_STATUS_SUCCESS 0x1 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
#define FW_CEM_DRIVER_VERSION_SIZE 39 /* +9 would send 48 bytes to fw */
#define FW_READ_SHADOW_RAM_CMD 0x31 #define FW_READ_SHADOW_RAM_CMD 0x31
#define FW_READ_SHADOW_RAM_LEN 0x6 #define FW_READ_SHADOW_RAM_LEN 0x6
#define FW_WRITE_SHADOW_RAM_CMD 0x33 #define FW_WRITE_SHADOW_RAM_CMD 0x33
#define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */ #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */
#define FW_SHADOW_RAM_DUMP_CMD 0x36 #define FW_SHADOW_RAM_DUMP_CMD 0x36
#define FW_SHADOW_RAM_DUMP_LEN 0 #define FW_SHADOW_RAM_DUMP_LEN 0
#define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
#define FW_NVM_DATA_OFFSET 3 #define FW_NVM_DATA_OFFSET 3
#define FW_MAX_READ_BUFFER_SIZE 1024 #define FW_MAX_READ_BUFFER_SIZE 1024
#define FW_DISABLE_RXEN_CMD 0xDE #define FW_DISABLE_RXEN_CMD 0xDE
#define FW_DISABLE_RXEN_LEN 0x1 #define FW_DISABLE_RXEN_LEN 0x1
#define FW_PHY_MGMT_REQ_CMD 0x20 #define FW_PHY_MGMT_REQ_CMD 0x20
#define FW_PHY_TOKEN_REQ_CMD 0xA
#define FW_PHY_TOKEN_REQ_LEN 2
#define FW_PHY_TOKEN_REQ 0
#define FW_PHY_TOKEN_REL 1
#define FW_PHY_TOKEN_OK 1
#define FW_PHY_TOKEN_RETRY 0x80
#define FW_PHY_TOKEN_DELAY 5 /* milliseconds */
#define FW_PHY_TOKEN_WAIT 5 /* seconds */
#define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)
#define FW_INT_PHY_REQ_CMD 0xB #define FW_INT_PHY_REQ_CMD 0xB
#define FW_INT_PHY_REQ_LEN 10 #define FW_INT_PHY_REQ_LEN 10
#define FW_INT_PHY_REQ_READ 0 #define FW_INT_PHY_REQ_READ 0
#define FW_INT_PHY_REQ_WRITE 1 #define FW_INT_PHY_REQ_WRITE 1
#define FW_PHY_ACT_REQ_CMD 5
#define FW_PHY_ACT_DATA_COUNT 4
#define FW_PHY_ACT_REQ_LEN (4 + 4 * FW_PHY_ACT_DATA_COUNT)
#define FW_PHY_ACT_INIT_PHY 1
#define FW_PHY_ACT_SETUP_LINK 2
#define FW_PHY_ACT_LINK_SPEED_10 (1u << 0)
#define FW_PHY_ACT_LINK_SPEED_100 (1u << 1)
#define FW_PHY_ACT_LINK_SPEED_1G (1u << 2)
#define FW_PHY_ACT_LINK_SPEED_2_5G (1u << 3)
#define FW_PHY_ACT_LINK_SPEED_5G (1u << 4)
#define FW_PHY_ACT_LINK_SPEED_10G (1u << 5)
#define FW_PHY_ACT_LINK_SPEED_20G (1u << 6)
#define FW_PHY_ACT_LINK_SPEED_25G (1u << 7)
#define FW_PHY_ACT_LINK_SPEED_40G (1u << 8)
#define FW_PHY_ACT_LINK_SPEED_50G (1u << 9)
#define FW_PHY_ACT_LINK_SPEED_100G (1u << 10)
#define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16
#define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3u << \
FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT)
#define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u
#define FW_PHY_ACT_SETUP_LINK_PAUSE_TX 1u
#define FW_PHY_ACT_SETUP_LINK_PAUSE_RX 2u
#define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u
#define FW_PHY_ACT_SETUP_LINK_LP (1u << 18)
#define FW_PHY_ACT_SETUP_LINK_HP (1u << 19)
#define FW_PHY_ACT_SETUP_LINK_EEE (1u << 20)
#define FW_PHY_ACT_SETUP_LINK_AN (1u << 22)
#define FW_PHY_ACT_SETUP_LINK_RSP_DOWN (1u << 0)
#define FW_PHY_ACT_GET_LINK_INFO 3
#define FW_PHY_ACT_GET_LINK_INFO_EEE (1u << 19)
#define FW_PHY_ACT_GET_LINK_INFO_FC_TX (1u << 20)
#define FW_PHY_ACT_GET_LINK_INFO_FC_RX (1u << 21)
#define FW_PHY_ACT_GET_LINK_INFO_POWER (1u << 22)
#define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE (1u << 24)
#define FW_PHY_ACT_GET_LINK_INFO_TEMP (1u << 25)
#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX (1u << 28)
#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX (1u << 29)
#define FW_PHY_ACT_FORCE_LINK_DOWN 4
#define FW_PHY_ACT_FORCE_LINK_DOWN_OFF (1u << 0)
#define FW_PHY_ACT_PHY_SW_RESET 5
#define FW_PHY_ACT_PHY_HW_RESET 6
#define FW_PHY_ACT_GET_PHY_INFO 7
#define FW_PHY_ACT_UD_2 0x1002
#define FW_PHY_ACT_UD_2_10G_KR_EEE (1u << 6)
#define FW_PHY_ACT_UD_2_10G_KX4_EEE (1u << 5)
#define FW_PHY_ACT_UD_2_1G_KX_EEE (1u << 4)
#define FW_PHY_ACT_UD_2_10G_T_EEE (1u << 3)
#define FW_PHY_ACT_UD_2_1G_T_EEE (1u << 2)
#define FW_PHY_ACT_UD_2_100M_TX_EEE (1u << 1)
#define FW_PHY_ACT_RETRIES 50
#define FW_PHY_INFO_SPEED_MASK 0xFFFu
#define FW_PHY_INFO_ID_HI_MASK 0xFFFF0000u
#define FW_PHY_INFO_ID_LO_MASK 0x0000FFFFu
/* Host Interface Command Structures */ /* Host Interface Command Structures */
#pragma pack(push, 1)
struct ixgbe_hic_hdr { struct ixgbe_hic_hdr {
u8 cmd; u8 cmd;
u8 buf_len; u8 buf_len;
union { union {
u8 cmd_resv; u8 cmd_resv;
u8 ret_status; u8 ret_status;
} cmd_or_resp; } cmd_or_resp;
u8 checksum; u8 checksum;
Show All 24 Linesstruct ixgbe_hic_drv_info {
u8 ver_sub; u8 ver_sub;
u8 ver_build; u8 ver_build;
u8 ver_min; u8 ver_min;
u8 ver_maj; u8 ver_maj;
u8 pad; /* end spacing to ensure length is mult. of dword */ u8 pad; /* end spacing to ensure length is mult. of dword */
u16 pad2; /* end spacing to ensure length is mult. of dword2 */ u16 pad2; /* end spacing to ensure length is mult. of dword2 */
}; };
struct ixgbe_hic_drv_info2 {
struct ixgbe_hic_hdr hdr;
u8 port_num;
u8 ver_sub;
u8 ver_build;
u8 ver_min;
u8 ver_maj;
char driver_string[FW_CEM_DRIVER_VERSION_SIZE];
};
/* These need to be dword aligned */ /* These need to be dword aligned */
struct ixgbe_hic_read_shadow_ram { struct ixgbe_hic_read_shadow_ram {
union ixgbe_hic_hdr2 hdr; union ixgbe_hic_hdr2 hdr;
u32 address; u32 address;
u16 length; u16 length;
u16 pad2; u16 pad2;
u16 data; u16 data;
u16 pad3; u16 pad3;
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struct ixgbe_hic_disable_rxen { struct ixgbe_hic_disable_rxen {
struct ixgbe_hic_hdr hdr; struct ixgbe_hic_hdr hdr;
u8 port_number; u8 port_number;
u8 pad2; u8 pad2;
u16 pad3; u16 pad3;
}; };
struct ixgbe_hic_phy_token_req {
struct ixgbe_hic_hdr hdr;
u8 port_number;
u8 command_type;
u16 pad;
};
struct ixgbe_hic_internal_phy_req { struct ixgbe_hic_internal_phy_req {
struct ixgbe_hic_hdr hdr; struct ixgbe_hic_hdr hdr;
u8 port_number; u8 port_number;
u8 command_type; u8 command_type;
u16 address; __be16 address;
u16 rsv1; u16 rsv1;
u32 write_data; __be32 write_data;
u16 pad; u16 pad;
}; };
struct ixgbe_hic_internal_phy_resp { struct ixgbe_hic_internal_phy_resp {
struct ixgbe_hic_hdr hdr; struct ixgbe_hic_hdr hdr;
u32 read_data; __be32 read_data;
}; };
struct ixgbe_hic_phy_activity_req {
struct ixgbe_hic_hdr hdr;
u8 port_number;
u8 pad;
__le16 activity_id;
__be32 data[FW_PHY_ACT_DATA_COUNT];
};
struct ixgbe_hic_phy_activity_resp {
struct ixgbe_hic_hdr hdr;
__be32 data[FW_PHY_ACT_DATA_COUNT];
};
#pragma pack(pop)
/* Transmit Descriptor - Legacy */ /* Transmit Descriptor - Legacy */
struct ixgbe_legacy_tx_desc { struct ixgbe_legacy_tx_desc {
u64 buffer_addr; /* Address of the descriptor's data buffer */ u64 buffer_addr; /* Address of the descriptor's data buffer */
union { union {
__le32 data; __le32 data;
struct { struct {
__le16 length; /* Data buffer length */ __le16 length; /* Data buffer length */
u8 cso; /* Checksum offset */ u8 cso; /* Checksum offset */
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#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
#define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* RSV L4 Packet TYPE */
#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */ #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */
#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ #define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ #define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ #define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */
#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation End */ #define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation End */
#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation Start */ #define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation Start */
#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ #define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */
#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ #define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */
#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ #define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */
#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ #define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */
#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
#define IXGBE_ADVTXD_OUTER_IPLEN 16 /* Adv ctxt OUTERIPLEN shift */ #define IXGBE_ADVTXD_OUTER_IPLEN 16 /* Adv ctxt OUTERIPLEN shift */
#define IXGBE_ADVTXD_TUNNEL_LEN 24 /* Adv ctxt TUNNELLEN shift */ #define IXGBE_ADVTXD_TUNNEL_LEN 24 /* Adv ctxt TUNNELLEN shift */
#define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT 16 /* Adv Tx Desc Tunnel Type shift */ #define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT 16 /* Adv Tx Desc Tunnel Type shift */
#define IXGBE_ADVTXD_OUTERIPCS_SHIFT 17 /* Adv Tx Desc OUTERIPCS Shift */ #define IXGBE_ADVTXD_OUTERIPCS_SHIFT 17 /* Adv Tx Desc OUTERIPCS Shift */
#define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE 1 /* Adv Tx Desc Tunnel Type NVGRE */ #define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE 1 /* Adv Tx Desc Tunnel Type NVGRE */
/* Adv Tx Desc OUTERIPCS Shift for X550EM_a */
#define IXGBE_ADVTXD_OUTERIPCS_SHIFT_X550EM_a 26
/* Autonegotiation advertised speeds */ /* Autonegotiation advertised speeds */
typedef u32 ixgbe_autoneg_advertised; typedef u32 ixgbe_autoneg_advertised;
/* Link speed */ /* Link speed */
typedef u32 ixgbe_link_speed; typedef u32 ixgbe_link_speed;
#define IXGBE_LINK_SPEED_UNKNOWN 0 #define IXGBE_LINK_SPEED_UNKNOWN 0
#define IXGBE_LINK_SPEED_10_FULL 0x0002
#define IXGBE_LINK_SPEED_100_FULL 0x0008 #define IXGBE_LINK_SPEED_100_FULL 0x0008
#define IXGBE_LINK_SPEED_1GB_FULL 0x0020 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020
#define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400 #define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400
#define IXGBE_LINK_SPEED_5GB_FULL 0x0800 #define IXGBE_LINK_SPEED_5GB_FULL 0x0800
#define IXGBE_LINK_SPEED_10GB_FULL 0x0080 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080
#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
IXGBE_LINK_SPEED_10GB_FULL) IXGBE_LINK_SPEED_10GB_FULL)
#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
IXGBE_LINK_SPEED_1GB_FULL | \ IXGBE_LINK_SPEED_1GB_FULL | \
IXGBE_LINK_SPEED_10GB_FULL) IXGBE_LINK_SPEED_10GB_FULL)
/* Physical layer type */ /* Physical layer type */
typedef u32 ixgbe_physical_layer; typedef u64 ixgbe_physical_layer;
#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001 #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001
#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002 #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002
#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004 #define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004
#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008
#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010
#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020
#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040
#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080
#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100
#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200
#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400
#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800
#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000
#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000
#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x4000 #define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000
#define IXGBE_PHYSICAL_LAYER_10BASE_T 0x08000
#define IXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000
/* Flow Control Data Sheet defined values /* Flow Control Data Sheet defined values
* Calculation and defines taken from 802.1bb Annex O * Calculation and defines taken from 802.1bb Annex O
*/ */
/* BitTimes (BT) conversion */ /* BitTimes (BT) conversion */
#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
#define IXGBE_B2BT(BT) (BT * 8) #define IXGBE_B2BT(BT) (BT * 8)
▲ Show 20 Lines • Show All 188 Lines • ▼ Show 20 Linesenum ixgbe_mac_type {
ixgbe_mac_unknown = 0, ixgbe_mac_unknown = 0,
ixgbe_mac_82598EB, ixgbe_mac_82598EB,
ixgbe_mac_82599EB, ixgbe_mac_82599EB,
ixgbe_mac_82599_vf, ixgbe_mac_82599_vf,
ixgbe_mac_X540, ixgbe_mac_X540,
ixgbe_mac_X540_vf, ixgbe_mac_X540_vf,
ixgbe_mac_X550, ixgbe_mac_X550,
ixgbe_mac_X550EM_x, ixgbe_mac_X550EM_x,
ixgbe_mac_X550EM_a,
ixgbe_mac_X550_vf, ixgbe_mac_X550_vf,
ixgbe_mac_X550EM_x_vf, ixgbe_mac_X550EM_x_vf,
ixgbe_mac_X550EM_a_vf,
ixgbe_num_macs ixgbe_num_macs
}; };
enum ixgbe_phy_type { enum ixgbe_phy_type {
ixgbe_phy_unknown = 0, ixgbe_phy_unknown = 0,
ixgbe_phy_none, ixgbe_phy_none,
ixgbe_phy_tn, ixgbe_phy_tn,
ixgbe_phy_aq, ixgbe_phy_aq,
ixgbe_phy_x550em_kr, ixgbe_phy_x550em_kr,
ixgbe_phy_x550em_kx4, ixgbe_phy_x550em_kx4,
ixgbe_phy_x550em_xfi,
ixgbe_phy_x550em_ext_t, ixgbe_phy_x550em_ext_t,
ixgbe_phy_cu_unknown, ixgbe_phy_cu_unknown,
ixgbe_phy_qt, ixgbe_phy_qt,
ixgbe_phy_xaui, ixgbe_phy_xaui,
ixgbe_phy_nl, ixgbe_phy_nl,
ixgbe_phy_sfp_passive_tyco, ixgbe_phy_sfp_passive_tyco,
ixgbe_phy_sfp_passive_unknown, ixgbe_phy_sfp_passive_unknown,
ixgbe_phy_sfp_active_unknown, ixgbe_phy_sfp_active_unknown,
ixgbe_phy_sfp_avago, ixgbe_phy_sfp_avago,
ixgbe_phy_sfp_ftl, ixgbe_phy_sfp_ftl,
ixgbe_phy_sfp_ftl_active, ixgbe_phy_sfp_ftl_active,
ixgbe_phy_sfp_unknown, ixgbe_phy_sfp_unknown,
ixgbe_phy_sfp_intel, ixgbe_phy_sfp_intel,
ixgbe_phy_qsfp_passive_unknown, ixgbe_phy_qsfp_passive_unknown,
ixgbe_phy_qsfp_active_unknown, ixgbe_phy_qsfp_active_unknown,
ixgbe_phy_qsfp_intel, ixgbe_phy_qsfp_intel,
ixgbe_phy_qsfp_unknown, ixgbe_phy_qsfp_unknown,
ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/ ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
ixgbe_phy_sgmii,
ixgbe_phy_fw,
ixgbe_phy_generic ixgbe_phy_generic
}; };
/* /*
* SFP+ module type IDs: * SFP+ module type IDs:
* *
* ID Module Type * ID Module Type
* ============= * =============
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/* Bus parameters */ /* Bus parameters */
struct ixgbe_bus_info { struct ixgbe_bus_info {
enum ixgbe_bus_speed speed; enum ixgbe_bus_speed speed;
enum ixgbe_bus_width width; enum ixgbe_bus_width width;
enum ixgbe_bus_type type; enum ixgbe_bus_type type;
u16 func; u16 func;
u16 lan_id; u8 lan_id;
u16 instance_id;
}; };
/* Flow control parameters */ /* Flow control parameters */
struct ixgbe_fc_info { struct ixgbe_fc_info {
u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */ u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */
u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */ u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */
u16 pause_time; /* Flow Control Pause timer */ u16 pause_time; /* Flow Control Pause timer */
bool send_xon; /* Flow control send XON */ bool send_xon; /* Flow control send XON */
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struct ixgbe_mac_operations { struct ixgbe_mac_operations {
s32 (*init_hw)(struct ixgbe_hw *); s32 (*init_hw)(struct ixgbe_hw *);
s32 (*reset_hw)(struct ixgbe_hw *); s32 (*reset_hw)(struct ixgbe_hw *);
s32 (*start_hw)(struct ixgbe_hw *); s32 (*start_hw)(struct ixgbe_hw *);
s32 (*clear_hw_cntrs)(struct ixgbe_hw *); s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
void (*enable_relaxed_ordering)(struct ixgbe_hw *); void (*enable_relaxed_ordering)(struct ixgbe_hw *);
enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
u32 (*get_supported_physical_layer)(struct ixgbe_hw *); u64 (*get_supported_physical_layer)(struct ixgbe_hw *);
s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *); s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *); s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);
s32 (*stop_adapter)(struct ixgbe_hw *); s32 (*stop_adapter)(struct ixgbe_hw *);
s32 (*get_bus_info)(struct ixgbe_hw *); s32 (*get_bus_info)(struct ixgbe_hw *);
void (*set_lan_id)(struct ixgbe_hw *); void (*set_lan_id)(struct ixgbe_hw *);
s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
s32 (*setup_sfp)(struct ixgbe_hw *); s32 (*setup_sfp)(struct ixgbe_hw *);
s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
s32 (*disable_sec_rx_path)(struct ixgbe_hw *); s32 (*disable_sec_rx_path)(struct ixgbe_hw *);
s32 (*enable_sec_rx_path)(struct ixgbe_hw *); s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32); s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
void (*release_swfw_sync)(struct ixgbe_hw *, u32); void (*release_swfw_sync)(struct ixgbe_hw *, u32);
void (*init_swfw_sync)(struct ixgbe_hw *);
s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *); s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool); s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
/* Link */ /* Link */
void (*disable_tx_laser)(struct ixgbe_hw *); void (*disable_tx_laser)(struct ixgbe_hw *);
void (*enable_tx_laser)(struct ixgbe_hw *); void (*enable_tx_laser)(struct ixgbe_hw *);
void (*flap_tx_laser)(struct ixgbe_hw *); void (*flap_tx_laser)(struct ixgbe_hw *);
s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
bool *); bool *);
void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed); void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed);
/* Packet Buffer manipulation */ /* Packet Buffer manipulation */
void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int); void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);
/* LED */ /* LED */
s32 (*led_on)(struct ixgbe_hw *, u32); s32 (*led_on)(struct ixgbe_hw *, u32);
s32 (*led_off)(struct ixgbe_hw *, u32); s32 (*led_off)(struct ixgbe_hw *, u32);
s32 (*blink_led_start)(struct ixgbe_hw *, u32); s32 (*blink_led_start)(struct ixgbe_hw *, u32);
s32 (*blink_led_stop)(struct ixgbe_hw *, u32); s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
s32 (*init_led_link_act)(struct ixgbe_hw *);
/* RAR, Multicast, VLAN */ /* RAR, Multicast, VLAN */
s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *); s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
s32 (*clear_rar)(struct ixgbe_hw *, u32); s32 (*clear_rar)(struct ixgbe_hw *, u32);
s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32); s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32); s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
s32 (*init_rx_addrs)(struct ixgbe_hw *); s32 (*init_rx_addrs)(struct ixgbe_hw *);
s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32, s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
ixgbe_mc_addr_itr); ixgbe_mc_addr_itr);
s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
ixgbe_mc_addr_itr, bool clear); ixgbe_mc_addr_itr, bool clear);
s32 (*enable_mc)(struct ixgbe_hw *); s32 (*enable_mc)(struct ixgbe_hw *);
s32 (*disable_mc)(struct ixgbe_hw *); s32 (*disable_mc)(struct ixgbe_hw *);
s32 (*clear_vfta)(struct ixgbe_hw *); s32 (*clear_vfta)(struct ixgbe_hw *);
s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool);
s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *); s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, u32 *, u32,
bool);
s32 (*init_uta_tables)(struct ixgbe_hw *); s32 (*init_uta_tables)(struct ixgbe_hw *);
void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int); void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int); void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
/* Flow Control */ /* Flow Control */
s32 (*fc_enable)(struct ixgbe_hw *); s32 (*fc_enable)(struct ixgbe_hw *);
s32 (*setup_fc)(struct ixgbe_hw *); s32 (*setup_fc)(struct ixgbe_hw *);
void (*fc_autoneg)(struct ixgbe_hw *);
/* Manageability interface */ /* Manageability interface */
s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8); s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16,
const char *);
s32 (*bypass_rw) (struct ixgbe_hw *hw, u32 cmd, u32 *status);
bool (*bypass_valid_rd) (u32 in_reg, u32 out_reg);
s32 (*bypass_set) (struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action);
s32 (*bypass_rd_eep) (struct ixgbe_hw *hw, u32 addr, u8 *value);
void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map); void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map);
void (*disable_rx)(struct ixgbe_hw *hw); void (*disable_rx)(struct ixgbe_hw *hw);
void (*enable_rx)(struct ixgbe_hw *hw); void (*enable_rx)(struct ixgbe_hw *hw);
void (*set_source_address_pruning)(struct ixgbe_hw *, bool, void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
unsigned int); unsigned int);
void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int); void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);
s32 (*dmac_update_tcs)(struct ixgbe_hw *hw); s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
s32 (*dmac_config_tcs)(struct ixgbe_hw *hw); s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);
Show All 22 Linesstruct ixgbe_phy_operations {
s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *); s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
void (*i2c_bus_clear)(struct ixgbe_hw *); void (*i2c_bus_clear)(struct ixgbe_hw *);
s32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
s32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
s32 (*check_overtemp)(struct ixgbe_hw *); s32 (*check_overtemp)(struct ixgbe_hw *);
s32 (*set_phy_power)(struct ixgbe_hw *, bool on); s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
s32 (*enter_lplu)(struct ixgbe_hw *); s32 (*enter_lplu)(struct ixgbe_hw *);
s32 (*handle_lasi)(struct ixgbe_hw *hw); s32 (*handle_lasi)(struct ixgbe_hw *hw);
s32 (*read_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
u16 *value);
s32 (*write_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
u16 value);
s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
u8 *value); u8 *value);
s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
u8 value); u8 value);
}; };
struct ixgbe_link_operations {
s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
u16 *val);
s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
u16 val);
};
struct ixgbe_link_info {
struct ixgbe_link_operations ops;
u8 addr;
};
struct ixgbe_eeprom_info { struct ixgbe_eeprom_info {
struct ixgbe_eeprom_operations ops; struct ixgbe_eeprom_operations ops;
enum ixgbe_eeprom_type type; enum ixgbe_eeprom_type type;
u32 semaphore_delay; u32 semaphore_delay;
u16 word_size; u16 word_size;
u16 address_bits; u16 address_bits;
u16 word_page_size; u16 word_page_size;
u16 ctrl_word_3; u16 ctrl_word_3;
Show All 27 Lines#define IXGBE_MAX_MTA 128
u16 max_msix_vectors; u16 max_msix_vectors;
bool arc_subsystem_valid; bool arc_subsystem_valid;
bool orig_link_settings_stored; bool orig_link_settings_stored;
bool autotry_restart; bool autotry_restart;
u8 flags; u8 flags;
struct ixgbe_dmac_config dmac_config; struct ixgbe_dmac_config dmac_config;
bool set_lben; bool set_lben;
u32 max_link_up_time; u32 max_link_up_time;
u8 led_link_act;
}; };
struct ixgbe_phy_info { struct ixgbe_phy_info {
struct ixgbe_phy_operations ops; struct ixgbe_phy_operations ops;
enum ixgbe_phy_type type; enum ixgbe_phy_type type;
u32 addr; u32 addr;
u32 id; u32 id;
enum ixgbe_sfp_type sfp_type; enum ixgbe_sfp_type sfp_type;
bool sfp_setup_needed; bool sfp_setup_needed;
u32 revision; u32 revision;
enum ixgbe_media_type media_type; enum ixgbe_media_type media_type;
u32 phy_semaphore_mask; u32 phy_semaphore_mask;
bool reset_disable; bool reset_disable;
ixgbe_autoneg_advertised autoneg_advertised; ixgbe_autoneg_advertised autoneg_advertised;
ixgbe_link_speed speeds_supported; ixgbe_link_speed speeds_supported;
ixgbe_link_speed eee_speeds_supported;
ixgbe_link_speed eee_speeds_advertised;
enum ixgbe_smart_speed smart_speed; enum ixgbe_smart_speed smart_speed;
bool smart_speed_active; bool smart_speed_active;
bool multispeed_fiber; bool multispeed_fiber;
bool reset_if_overtemp; bool reset_if_overtemp;
bool qsfp_shared_i2c_bus; bool qsfp_shared_i2c_bus;
u32 nw_mng_if_sel; u32 nw_mng_if_sel;
}; };
Show All 30 Lines
struct ixgbe_hw { struct ixgbe_hw {
u8 IOMEM *hw_addr; u8 IOMEM *hw_addr;
void *back; void *back;
struct ixgbe_mac_info mac; struct ixgbe_mac_info mac;
struct ixgbe_addr_filter_info addr_ctrl; struct ixgbe_addr_filter_info addr_ctrl;
struct ixgbe_fc_info fc; struct ixgbe_fc_info fc;
struct ixgbe_phy_info phy; struct ixgbe_phy_info phy;
struct ixgbe_link_info link;
struct ixgbe_eeprom_info eeprom; struct ixgbe_eeprom_info eeprom;
struct ixgbe_bus_info bus; struct ixgbe_bus_info bus;
struct ixgbe_mbx_info mbx; struct ixgbe_mbx_info mbx;
const u32 *mvals; const u32 *mvals;
u16 device_id; u16 device_id;
u16 vendor_id; u16 vendor_id;
u16 subsystem_device_id; u16 subsystem_device_id;
u16 subsystem_vendor_id; u16 subsystem_vendor_id;
u8 revision_id; u8 revision_id;
bool adapter_stopped; bool adapter_stopped;
int api_version; int api_version;
bool force_full_reset; bool force_full_reset;
bool allow_unsupported_sfp; bool allow_unsupported_sfp;
bool wol_enabled; bool wol_enabled;
bool need_crosstalk_fix;
}; };
#define ixgbe_call_func(hw, func, params, error) \ #define ixgbe_call_func(hw, func, params, error) \
(func != NULL) ? func params : error (func != NULL) ? func params : error
/* Error Codes */ /* Error Codes */
#define IXGBE_SUCCESS 0 #define IXGBE_SUCCESS 0
Show All 25 Lines
#define IXGBE_ERR_OVERTEMP -26 #define IXGBE_ERR_OVERTEMP -26
#define IXGBE_ERR_FC_NOT_NEGOTIATED -27 #define IXGBE_ERR_FC_NOT_NEGOTIATED -27
#define IXGBE_ERR_FC_NOT_SUPPORTED -28 #define IXGBE_ERR_FC_NOT_SUPPORTED -28
#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
#define IXGBE_ERR_PBA_SECTION -31 #define IXGBE_ERR_PBA_SECTION -31
#define IXGBE_ERR_INVALID_ARGUMENT -32 #define IXGBE_ERR_INVALID_ARGUMENT -32
#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33 #define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
#define IXGBE_ERR_OUT_OF_MEM -34 #define IXGBE_ERR_OUT_OF_MEM -34
#define IXGBE_BYPASS_FW_WRITE_FAILURE -35
#define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36 #define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36
#define IXGBE_ERR_EEPROM_PROTECTED_REGION -37 #define IXGBE_ERR_EEPROM_PROTECTED_REGION -37
#define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38 #define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38
#define IXGBE_ERR_FW_RESP_INVALID -39
#define IXGBE_ERR_TOKEN_RETRY -40
#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
#define BYPASS_PAGE_CTL0 0x00000000
#define BYPASS_PAGE_CTL1 0x40000000
#define BYPASS_PAGE_CTL2 0x80000000
#define BYPASS_PAGE_M 0xc0000000
#define BYPASS_WE 0x20000000
#define BYPASS_AUTO 0x0
#define BYPASS_NOP 0x0
#define BYPASS_NORM 0x1
#define BYPASS_BYPASS 0x2
#define BYPASS_ISOLATE 0x3
#define BYPASS_EVENT_MAIN_ON 0x1
#define BYPASS_EVENT_AUX_ON 0x2
#define BYPASS_EVENT_MAIN_OFF 0x3
#define BYPASS_EVENT_AUX_OFF 0x4
#define BYPASS_EVENT_WDT_TO 0x5
#define BYPASS_EVENT_USR 0x6
#define BYPASS_MODE_OFF_M 0x00000003
#define BYPASS_STATUS_OFF_M 0x0000000c
#define BYPASS_AUX_ON_M 0x00000030
#define BYPASS_MAIN_ON_M 0x000000c0
#define BYPASS_MAIN_OFF_M 0x00000300
#define BYPASS_AUX_OFF_M 0x00000c00
#define BYPASS_WDTIMEOUT_M 0x00003000
#define BYPASS_WDT_ENABLE_M 0x00004000
#define BYPASS_WDT_VALUE_M 0x00070000
#define BYPASS_MODE_OFF_SHIFT 0
#define BYPASS_STATUS_OFF_SHIFT 2
#define BYPASS_AUX_ON_SHIFT 4
#define BYPASS_MAIN_ON_SHIFT 6
#define BYPASS_MAIN_OFF_SHIFT 8
#define BYPASS_AUX_OFF_SHIFT 10
#define BYPASS_WDTIMEOUT_SHIFT 12
#define BYPASS_WDT_ENABLE_SHIFT 14
#define BYPASS_WDT_TIME_SHIFT 16
#define BYPASS_WDT_1 0x0
#define BYPASS_WDT_1_5 0x1
#define BYPASS_WDT_2 0x2
#define BYPASS_WDT_3 0x3
#define BYPASS_WDT_4 0x4
#define BYPASS_WDT_8 0x5
#define BYPASS_WDT_16 0x6
#define BYPASS_WDT_32 0x7
#define BYPASS_WDT_OFF 0xffff
#define BYPASS_CTL1_TIME_M 0x01ffffff
#define BYPASS_CTL1_VALID_M 0x02000000
#define BYPASS_CTL1_OFFTRST_M 0x04000000
#define BYPASS_CTL1_WDT_PET_M 0x08000000
#define BYPASS_CTL1_VALID 0x02000000
#define BYPASS_CTL1_OFFTRST 0x04000000
#define BYPASS_CTL1_WDT_PET 0x08000000
#define BYPASS_CTL2_DATA_M 0x000000ff
#define BYPASS_CTL2_OFFSET_M 0x0000ff00
#define BYPASS_CTL2_RW_M 0x00010000
#define BYPASS_CTL2_HEAD_M 0x0ff00000
#define BYPASS_CTL2_OFFSET_SHIFT 8
#define BYPASS_CTL2_HEAD_SHIFT 20
#define BYPASS_CTL2_RW 0x00010000
struct ixgbe_bypass_eeprom {
u32 logs;
u32 clear_off;
u8 actions;
};
#define BYPASS_MAX_LOGS 43
#define BYPASS_LOG_SIZE 5
#define BYPASS_LOG_LINE_SIZE 37
#define BYPASS_EEPROM_VER_ADD 0x02
#define BYPASS_LOG_TIME_M 0x01ffffff
#define BYPASS_LOG_TIME_VALID_M 0x02000000
#define BYPASS_LOG_HEAD_M 0x04000000
#define BYPASS_LOG_CLEAR_M 0x08000000
#define BYPASS_LOG_EVENT_M 0xf0000000
#define BYPASS_LOG_ACTION_M 0x03
#define BYPASS_LOG_EVENT_SHIFT 28
#define BYPASS_LOG_CLEAR_SHIFT 24 /* bit offset */
#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4)) #define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
#define IXGBE_FUSES0_300MHZ (1 << 5) #define IXGBE_FUSES0_300MHZ (1 << 5)
#define IXGBE_FUSES0_REV1 (1 << 6) #define IXGBE_FUSES0_REV_MASK (3 << 6)
#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010) #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
#define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200)
#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C) #define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
#define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C) #define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C)
#define IXGBE_KRM_AN_CNTL_4(P) ((P) ? 0x8238 : 0x4238)
#define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248)
#define IXGBE_KRM_PCS_KX_AN(P) ((P) ? 0x9918 : 0x5918)
#define IXGBE_KRM_PCS_KX_AN_LP(P) ((P) ? 0x991C : 0x591C)
#define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0)
#define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C)
#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634) #define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638) #define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00) #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00) #define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00)
#define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054)
#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520) #define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)
#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00) #define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA ~(0x3 << 20)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR (1u << 20)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR (0x2 << 20)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN (1u << 25)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN (1u << 26)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN (1u << 27)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M ~(0x7 << 28)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M (1u << 28)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G (0x2 << 28)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G (0x3 << 28)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN (0x4 << 28)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G (0x7 << 28)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK (0x7 << 28)
#define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART (1u << 31)
#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9) #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9)
#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11) #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11)
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8) #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8) #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8)
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8) #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN (1 << 12)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN (1 << 13)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14) #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15) #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16) #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18) #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18)
#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24) #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24)
#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26) #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26)
#define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE (1 << 28)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29) #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31) #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31)
#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28) #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28)
#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29) #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29)
#define IXGBE_KRM_PCS_KX_AN_SYM_PAUSE (1 << 1)
#define IXGBE_KRM_PCS_KX_AN_ASM_PAUSE (1 << 2)
#define IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE (1 << 2)
#define IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE (1 << 3)
#define IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73 (1 << 29)
#define IXGBE_KRM_AN_CNTL_8_LINEAR (1 << 0)
#define IXGBE_KRM_AN_CNTL_8_LIMITING (1 << 1)
#define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE (1 << 10)
#define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE (1 << 11)
#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D (1 << 12)
#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D (1 << 19)
#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6) #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6)
#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15) #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15)
#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16) #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16)
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4) #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4)
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2) #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2)
#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16) #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16)
Show All 16 Lines#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \
(0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT) (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28
#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7
#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31 #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31
#define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT) #define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
#define IXGBE_SB_IOSF_TARGET_KR_PHY 0 #define IXGBE_SB_IOSF_TARGET_KR_PHY 0
#define IXGBE_NW_MNG_IF_SEL 0x00011178 #define IXGBE_NW_MNG_IF_SEL 0x00011178
#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT (1u << 1)
#define IXGBE_NW_MNG_IF_SEL_MDIO_IF_MODE (1u << 2)
#define IXGBE_NW_MNG_IF_SEL_EN_SHARED_MDIO (1u << 13)
#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M (1u << 17)
#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M (1u << 18)
#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G (1u << 19)
#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G (1u << 20)
#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G (1u << 21)
#define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE (1u << 25)
#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) /* X552 reg field only */
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \
(0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
#endif /* _IXGBE_TYPE_H_ */ #endif /* _IXGBE_TYPE_H_ */