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sys/dev/ixgbe/ixgbe_82599.c
| /****************************************************************************** | /****************************************************************************** | ||||
| Copyright (c) 2001-2015, Intel Corporation | Copyright (c) 2001-2017, Intel Corporation | ||||
| All rights reserved. | All rights reserved. | ||||
| Redistribution and use in source and binary forms, with or without | Redistribution and use in source and binary forms, with or without | ||||
| modification, are permitted provided that the following conditions are met: | modification, are permitted provided that the following conditions are met: | ||||
| 1. Redistributions of source code must retain the above copyright notice, | 1. Redistributions of source code must retain the above copyright notice, | ||||
| this list of conditions and the following disclaimer. | this list of conditions and the following disclaimer. | ||||
| 2. Redistributions in binary form must reproduce the above copyright | 2. Redistributions in binary form must reproduce the above copyright | ||||
| notice, this list of conditions and the following disclaimer in the | notice, this list of conditions and the following disclaimer in the | ||||
| documentation and/or other materials provided with the distribution. | documentation and/or other materials provided with the distribution. | ||||
| 3. Neither the name of the Intel Corporation nor the names of its | 3. Neither the name of the Intel Corporation nor the names of its | ||||
| contributors may be used to endorse or promote products derived from | contributors may be used to endorse or promote products derived from | ||||
| this software without specific prior written permission. | this software without specific prior written permission. | ||||
| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||||
| AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||||
| IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||||
| ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | ||||
| LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||||
| CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||||
| SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | ||||
| INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | ||||
| CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | ||||
| ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ||||
| POSSIBILITY OF SUCH DAMAGE. | POSSIBILITY OF SUCH DAMAGE. | ||||
| ******************************************************************************/ | ******************************************************************************/ | ||||
| /*$FreeBSD$*/ | /*$FreeBSD$*/ | ||||
| #include "ixgbe_type.h" | #include "ixgbe_type.h" | ||||
| #include "ixgbe_82599.h" | #include "ixgbe_82599.h" | ||||
| ▲ Show 20 Lines • Show All 352 Lines • ▼ Show 20 Lines | s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) | ||||
| /* EEPROM */ | /* EEPROM */ | ||||
| eeprom->ops.read = ixgbe_read_eeprom_82599; | eeprom->ops.read = ixgbe_read_eeprom_82599; | ||||
| eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599; | eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599; | ||||
| /* Manageability interface */ | /* Manageability interface */ | ||||
| mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; | mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; | ||||
| mac->ops.bypass_rw = ixgbe_bypass_rw_generic; | |||||
| mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; | |||||
| mac->ops.bypass_set = ixgbe_bypass_set_generic; | |||||
| mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; | |||||
| mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; | mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; | ||||
| return ret_val; | return ret_val; | ||||
| } | } | ||||
| /** | /** | ||||
| * ixgbe_get_link_capabilities_82599 - Determines link capabilities | * ixgbe_get_link_capabilities_82599 - Determines link capabilities | ||||
| ▲ Show 20 Lines • Show All 767 Lines • ▼ Show 20 Lines | mac_reset_top: | ||||
| hw->mac.num_rar_entries = 128; | hw->mac.num_rar_entries = 128; | ||||
| hw->mac.ops.init_rx_addrs(hw); | hw->mac.ops.init_rx_addrs(hw); | ||||
| /* Store the permanent SAN mac address */ | /* Store the permanent SAN mac address */ | ||||
| hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); | hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); | ||||
| /* Add the SAN MAC address to the RAR only if it's a valid address */ | /* Add the SAN MAC address to the RAR only if it's a valid address */ | ||||
| if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { | if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { | ||||
| hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, | |||||
| hw->mac.san_addr, 0, IXGBE_RAH_AV); | |||||
| /* Save the SAN MAC RAR index */ | /* Save the SAN MAC RAR index */ | ||||
| hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; | hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; | ||||
| hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, | |||||
| hw->mac.san_addr, 0, IXGBE_RAH_AV); | |||||
| /* clear VMDq pool/queue selection for this RAR */ | |||||
| hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, | |||||
| IXGBE_CLEAR_VMDQ_ALL); | |||||
| /* Reserve the last RAR for the SAN MAC address */ | /* Reserve the last RAR for the SAN MAC address */ | ||||
| hw->mac.num_rar_entries--; | hw->mac.num_rar_entries--; | ||||
| } | } | ||||
| /* Store the alternative WWNN/WWPN prefix */ | /* Store the alternative WWNN/WWPN prefix */ | ||||
| hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, | hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, | ||||
| &hw->mac.wwpn_prefix); | &hw->mac.wwpn_prefix); | ||||
| ▲ Show 20 Lines • Show All 182 Lines • ▼ Show 20 Lines | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl, | ||||
| * Send interrupt when 64 (0x4 * 16) filters are left | * Send interrupt when 64 (0x4 * 16) filters are left | ||||
| */ | */ | ||||
| fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | | fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | | ||||
| IXGBE_FDIRCTRL_REPORT_STATUS | | IXGBE_FDIRCTRL_REPORT_STATUS | | ||||
| (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | | (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | | ||||
| (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | | (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | | ||||
| (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | | (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | | ||||
| (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); | (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); | ||||
| if ((hw->mac.type == ixgbe_mac_X550) || | |||||
| (hw->mac.type == ixgbe_mac_X550EM_x)) | |||||
| fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH; | |||||
| if (cloud_mode) | if (cloud_mode) | ||||
| fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD << | fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD << | ||||
| IXGBE_FDIRCTRL_FILTERMODE_SHIFT); | IXGBE_FDIRCTRL_FILTERMODE_SHIFT); | ||||
| /* write hashes and fdirctrl register, poll for completion */ | /* write hashes and fdirctrl register, poll for completion */ | ||||
| ixgbe_fdir_enable_82599(hw, fdirctrl); | ixgbe_fdir_enable_82599(hw, fdirctrl); | ||||
| Show All 12 Lines | void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue) | ||||
| DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599"); | DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599"); | ||||
| /* Clear init done bit and drop queue field */ | /* Clear init done bit and drop queue field */ | ||||
| fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); | fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); | ||||
| fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE); | fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE); | ||||
| /* Set drop queue */ | /* Set drop queue */ | ||||
| fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT); | fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT); | ||||
| if ((hw->mac.type == ixgbe_mac_X550) || | if ((hw->mac.type == ixgbe_mac_X550) || | ||||
| (hw->mac.type == ixgbe_mac_X550EM_x)) | (hw->mac.type == ixgbe_mac_X550EM_x) || | ||||
| (hw->mac.type == ixgbe_mac_X550EM_a)) | |||||
| fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH; | fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH; | ||||
| IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, | ||||
| (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | | (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | | ||||
| IXGBE_FDIRCMD_CLEARHT)); | IXGBE_FDIRCMD_CLEARHT)); | ||||
| IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
| IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, | ||||
| (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & | (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & | ||||
| ▲ Show 20 Lines • Show All 380 Lines • ▼ Show 20 Lines | if (cloud_mode) { | ||||
| case 0xFFFF: | case 0xFFFF: | ||||
| break; | break; | ||||
| default: | default: | ||||
| DEBUGOUT(" Error on tunnel type byte mask\n"); | DEBUGOUT(" Error on tunnel type byte mask\n"); | ||||
| return IXGBE_ERR_CONFIG; | return IXGBE_ERR_CONFIG; | ||||
| } | } | ||||
| IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m); | IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m); | ||||
| /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and | /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM, | ||||
| * FDIRDIP4M in cloud mode to allow L3/L3 packets to | * FDIRSIP4M and FDIRDIP4M in cloud mode to allow | ||||
| * tunnel. | * L3/L3 packets to tunnel. | ||||
| */ | */ | ||||
| IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF); | IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF); | ||||
| IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF); | IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF); | ||||
| IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF); | IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF); | ||||
| IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF); | IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF); | ||||
| switch (hw->mac.type) { | |||||
| case ixgbe_mac_X550: | |||||
| case ixgbe_mac_X550EM_x: | |||||
| case ixgbe_mac_X550EM_a: | |||||
| IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF); | |||||
| break; | |||||
| default: | |||||
| break; | |||||
| } | } | ||||
| } | |||||
| /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ | /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ | ||||
| IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); | IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); | ||||
| if (!cloud_mode) { | if (!cloud_mode) { | ||||
| /* store the TCP/UDP port masks, bit reversed from port | /* store the TCP/UDP port masks, bit reversed from port | ||||
| * layout */ | * layout */ | ||||
| fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); | fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); | ||||
| /* write both the same so that UDP and TCP use the same mask */ | /* write both the same so that UDP and TCP use the same mask */ | ||||
| IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); | IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); | ||||
| IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); | IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); | ||||
| /* also use it for SCTP */ | /* also use it for SCTP */ | ||||
| switch (hw->mac.type) { | switch (hw->mac.type) { | ||||
| case ixgbe_mac_X550: | case ixgbe_mac_X550: | ||||
| case ixgbe_mac_X550EM_x: | case ixgbe_mac_X550EM_x: | ||||
| case ixgbe_mac_X550EM_a: | |||||
| IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); | IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); | ||||
| break; | break; | ||||
| default: | default: | ||||
| break; | break; | ||||
| } | } | ||||
| /* store source and destination IP masks (big-enian) */ | /* store source and destination IP masks (big-enian) */ | ||||
| IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, | IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, | ||||
| ▲ Show 20 Lines • Show All 766 Lines • Show Last 20 Lines | |||||