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sys/arm/arm/gic.c
Show First 20 Lines • Show All 137 Lines • ▼ Show 20 Lines | |||||
static struct resource_spec arm_gic_spec[] = { | static struct resource_spec arm_gic_spec[] = { | ||||
{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */ | { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */ | ||||
{ SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */ | { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */ | ||||
#ifdef INTRNG | #ifdef INTRNG | ||||
{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, /* Parent interrupt */ | { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, /* Parent interrupt */ | ||||
#endif | #endif | ||||
{ -1, 0 } | { -1, 0 } | ||||
}; | }; | ||||
wblock: There is a tab after a space here, after `SYS_RES_IRQ,` | |||||
static u_int arm_gic_map[MAXCPU]; | static u_int arm_gic_map[MAXCPU]; | ||||
static struct arm_gic_softc *gic_sc = NULL; | static struct arm_gic_softc *gic_sc = NULL; | ||||
#define gic_c_read_4(_sc, _reg) \ | #define gic_c_read_4(_sc, _reg) \ | ||||
bus_space_read_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg)) | bus_space_read_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg)) | ||||
#define gic_c_write_4(_sc, _reg, _val) \ | #define gic_c_write_4(_sc, _reg, _val) \ | ||||
Show All 22 Lines | |||||
static inline void | static inline void | ||||
gic_irq_mask(struct arm_gic_softc *sc, u_int irq) | gic_irq_mask(struct arm_gic_softc *sc, u_int irq) | ||||
{ | { | ||||
gic_d_write_4(sc, GICD_ICENABLER(irq), GICD_I_MASK(irq)); | gic_d_write_4(sc, GICD_ICENABLER(irq), GICD_I_MASK(irq)); | ||||
} | } | ||||
#endif | #endif | ||||
struct arm_gic_softc * | |||||
get_arm_gic_sc(void) | |||||
{ | |||||
return gic_sc; | |||||
} | |||||
static uint8_t | static uint8_t | ||||
gic_cpu_mask(struct arm_gic_softc *sc) | gic_cpu_mask(struct arm_gic_softc *sc) | ||||
{ | { | ||||
uint32_t mask; | uint32_t mask; | ||||
int i; | int i; | ||||
/* Read the current cpuid mask by reading ITARGETSR{0..7} */ | /* Read the current cpuid mask by reading ITARGETSR{0..7} */ | ||||
for (i = 0; i < 8; i++) { | for (i = 0; i < 8; i++) { | ||||
▲ Show 20 Lines • Show All 901 Lines • ▼ Show 20 Lines | arm_gic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, | ||||
struct arm_gic_softc *sc = device_get_softc(dev); | struct arm_gic_softc *sc = device_get_softc(dev); | ||||
struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc; | struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc; | ||||
uint32_t val = 0, i; | uint32_t val = 0, i; | ||||
for (i = 0; i < MAXCPU; i++) | for (i = 0; i < MAXCPU; i++) | ||||
if (CPU_ISSET(i, &cpus)) | if (CPU_ISSET(i, &cpus)) | ||||
val |= arm_gic_map[i] << GICD_SGI_TARGET_SHIFT; | val |= arm_gic_map[i] << GICD_SGI_TARGET_SHIFT; | ||||
gic_d_write_4(sc, GICD_SGIR, val | gi->gi_irq); | gic_d_write_4(sc, GICD_SGIR(0), val | gi->gi_irq); | ||||
} | } | ||||
static int | static int | ||||
arm_gic_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp) | arm_gic_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp) | ||||
{ | { | ||||
struct intr_irqsrc *isrc; | struct intr_irqsrc *isrc; | ||||
struct arm_gic_softc *sc = device_get_softc(dev); | struct arm_gic_softc *sc = device_get_softc(dev); | ||||
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines | |||||
{ | { | ||||
struct arm_gic_softc *sc = device_get_softc(dev); | struct arm_gic_softc *sc = device_get_softc(dev); | ||||
uint32_t val = 0, i; | uint32_t val = 0, i; | ||||
for (i = 0; i < MAXCPU; i++) | for (i = 0; i < MAXCPU; i++) | ||||
if (CPU_ISSET(i, &cpus)) | if (CPU_ISSET(i, &cpus)) | ||||
val |= arm_gic_map[i] << GICD_SGI_TARGET_SHIFT; | val |= arm_gic_map[i] << GICD_SGI_TARGET_SHIFT; | ||||
gic_d_write_4(sc, GICD_SGIR, val | ipi); | gic_d_write_4(sc, GICD_SGIR(0), val | ipi); | ||||
} | } | ||||
static int | static int | ||||
arm_gic_ipi_read(device_t dev, int i) | arm_gic_ipi_read(device_t dev, int i) | ||||
{ | { | ||||
if (i != -1) { | if (i != -1) { | ||||
/* | /* | ||||
▲ Show 20 Lines • Show All 346 Lines • Show Last 20 Lines |
There is a tab after a space here, after SYS_RES_IRQ,