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Differential D10045 Diff 26441 sys/arm/include/armreg.h

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sys/arm/include/armreg.h

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#define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */ #define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */
#define FAULT_ICACHE 0x004 /* Instruction cache maintenance */ #define FAULT_ICACHE 0x004 /* Instruction cache maintenance */
#define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */ #define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */
#define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */ #define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */
#define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */ #define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */
#define FAULT_EA_PREC 0x008 /* External Abort */ #define FAULT_EA_PREC 0x008 /* External Abort */
#define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */ #define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */
#define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */ #define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */
#define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */
#define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */
#define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */
#define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */ #define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */
#define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */ #define FAULT_TLB_CONFLICT 0x010 /* TLB Conflict Abort */
#define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */ #define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */
#define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */ #define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */
#define FAULT_TLB_CONFLICT 0x010 /* TLB Conflict Abort */ #define FAULT_PARITY 0x019 /* Parity Error */
#define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */ #define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */
#define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */ #define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */
#define FAULT_PARITY 0x019 /* Parity Error */
#define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */ #define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \
#define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */ ((((fsr) & (1 << 10)) >> (10 - 4))))
#define FSR_LPAE (1 << 9) /* LPAE indicator */
#define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \ #define FSR_WNR (1 << 11) /* Write-not-Read access */
((((fsr) & (1 << 10)) >> (10 - 4)))) #define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/
#define FSR_LPAE (1 << 9) /* LPAE indicator */ #define FSR_CM (1 << 13) /* Cache maintenance fault */
#define FSR_WNR (1 << 11) /* Write-not-Read access */ #endif /* !__ARM_ARCH < 6 */
#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/
#define FSR_CM (1 << 13) /* Cache maintenance fault */ /*
#endif /* !__ARM_ARCH < 6 */ * Address of the vector page, low and high versions.
*/
/* #ifndef __ASSEMBLER__
* Address of the vector page, low and high versions. #define ARM_VECTORS_LOW 0x00000000U
*/ #define ARM_VECTORS_HIGH 0xffff0000U
#ifndef __ASSEMBLER__ #else
#define ARM_VECTORS_LOW 0x00000000U #define ARM_VECTORS_LOW 0
#define ARM_VECTORS_HIGH 0xffff0000U #define ARM_VECTORS_HIGH 0xffff0000
#else #endif
#define ARM_VECTORS_LOW 0
#define ARM_VECTORS_HIGH 0xffff0000 /*
#endif * ARM Instructions
*
/* * 3 3 2 2 2
* ARM Instructions * 1 0 9 8 7 0
* * +-------+-------------------------------------------------------+
* 3 3 2 2 2 * | cond | instruction dependant |
* 1 0 9 8 7 0 * |c c c c| |
* +-------+-------------------------------------------------------+ * +-------+-------------------------------------------------------+
* | cond | instruction dependant | */
* |c c c c| |
* +-------+-------------------------------------------------------+ #define INSN_SIZE 4 /* Always 4 bytes */
*/ #define INSN_COND_MASK 0xf0000000 /* Condition mask */
#define INSN_COND_AL 0xe0000000 /* Always condition */
#define INSN_SIZE 4 /* Always 4 bytes */
#define INSN_COND_MASK 0xf0000000 /* Condition mask */ /* ARM register defines */
#define INSN_COND_AL 0xe0000000 /* Always condition */ #define ARM_REG_SIZE 4
#define ARM_REG_NUM_PC 15
/* ARM register defines */ #define ARM_REG_NUM_LR 14
#define ARM_REG_SIZE 4 #define ARM_REG_NUM_SP 13
#define ARM_REG_NUM_PC 15
#define ARM_REG_NUM_LR 14 #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */
#define ARM_REG_NUM_SP 13
/* ARM Hypervisor Related Defines */
#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ #define ARM_CP15_HDCR_HPMN 0x0000001f
#endif /* !MACHINE_ARMREG_H */ #endif /* !MACHINE_ARMREG_H */