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Differential D9836 Diff 25802 head/sys/arm/altera/socfpga/socfpga_mp.c

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head/sys/arm/altera/socfpga/socfpga_mp.c

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
#define SCU_NONSECURE_ACCESS_REG 0x54 #define SCU_NONSECURE_ACCESS_REG 0x54
#define RSTMGR_PHYSBASE 0xFFD05000 #define RSTMGR_PHYSBASE 0xFFD05000
#define RSTMGR_SIZE 0x100 #define RSTMGR_SIZE 0x100
#define RAM_PHYSBASE 0x0 #define RAM_PHYSBASE 0x0
#define RAM_SIZE 0x1000 #define RAM_SIZE 0x1000
#define SOCFPGA_SOCKIT 1 #define SOCFPGA_ARRIA10 1
#define SOCFPGA_SOCDK 2 #define SOCFPGA_CYCLONE5 2
extern char *mpentry_addr; extern char *mpentry_addr;
static void socfpga_trampoline(void); static void socfpga_trampoline(void);
static void static void
socfpga_trampoline(void) socfpga_trampoline(void)
{ {
Show All 19 Linessocfpga_mp_setmaxid(platform_t plat)
TUNABLE_INT_FETCH("hw.ncpu", &ncpu); TUNABLE_INT_FETCH("hw.ncpu", &ncpu);
if (ncpu < 1 || ncpu > hwcpu) if (ncpu < 1 || ncpu > hwcpu)
ncpu = hwcpu; ncpu = hwcpu;
mp_ncpus = ncpu; mp_ncpus = ncpu;
mp_maxid = ncpu - 1; mp_maxid = ncpu - 1;
} }
static void static void
_socfpga_mp_start_ap(platform_t plat, uint32_t platid) _socfpga_mp_start_ap(uint32_t platid)
{ {
bus_space_handle_t scu, rst, ram; bus_space_handle_t scu, rst, ram;
int reg; int reg;
if (platid == SOCFPGA_SOCDK) { switch (platid) {
#if defined(SOC_ALTERA_ARRIA10)
case SOCFPGA_ARRIA10:
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10, if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10,
SCU_SIZE, 0, &scu) != 0) SCU_SIZE, 0, &scu) != 0)
panic("Couldn't map the SCU\n"); panic("Couldn't map the SCU\n");
} else { break;
#endif
#if defined(SOC_ALTERA_CYCLONE5)
case SOCFPGA_CYCLONE5:
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
SCU_SIZE, 0, &scu) != 0) SCU_SIZE, 0, &scu) != 0)
panic("Couldn't map the SCU\n"); panic("Couldn't map the SCU\n");
break;
#endif
default:
panic("Unknown platform id %d\n", platid);
} }
if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE, if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE,
RSTMGR_SIZE, 0, &rst) != 0) RSTMGR_SIZE, 0, &rst) != 0)
panic("Couldn't map the reset manager (RSTMGR)\n"); panic("Couldn't map the reset manager (RSTMGR)\n");
if (bus_space_map(fdtbus_bs_tag, RAM_PHYSBASE, if (bus_space_map(fdtbus_bs_tag, RAM_PHYSBASE,
RAM_SIZE, 0, &ram) != 0) RAM_SIZE, 0, &ram) != 0)
panic("Couldn't map the first physram page\n"); panic("Couldn't map the first physram page\n");
/* Invalidate SCU cache tags */ /* Invalidate SCU cache tags */
bus_space_write_4(fdtbus_bs_tag, scu, bus_space_write_4(fdtbus_bs_tag, scu,
SCU_INV_TAGS_REG, 0x0000ffff); SCU_INV_TAGS_REG, 0x0000ffff);
/* /*
* Erratum ARM/MP: 764369 (problems with cache maintenance). * Erratum ARM/MP: 764369 (problems with cache maintenance).
* Setting the "disable-migratory bit" in the undocumented SCU * Setting the "disable-migratory bit" in the undocumented SCU
* Diagnostic Control Register helps work around the problem. * Diagnostic Control Register helps work around the problem.
*/ */
reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL); reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
reg |= (SCU_DIAG_DISABLE_MIGBIT); reg |= (SCU_DIAG_DISABLE_MIGBIT);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg); bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg);
/* Put CPU1 to reset state */ /* Put CPU1 to reset state */
if (platid == SOCFPGA_SOCDK) { switch (platid) {
#if defined(SOC_ALTERA_ARRIA10)
case SOCFPGA_ARRIA10:
bus_space_write_4(fdtbus_bs_tag, rst, bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1); RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1);
} else { break;
#endif
#if defined(SOC_ALTERA_CYCLONE5)
case SOCFPGA_CYCLONE5:
bus_space_write_4(fdtbus_bs_tag, rst, bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_MPUMODRST, MPUMODRST_CPU1); RSTMGR_MPUMODRST, MPUMODRST_CPU1);
break;
#endif
default:
panic("Unknown platform id %d\n", platid);
} }
/* Enable the SCU, then clean the cache on this core */ /* Enable the SCU, then clean the cache on this core */
reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
reg |= (SCU_CONTROL_ENABLE); reg |= (SCU_CONTROL_ENABLE);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, reg); bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, reg);
/* Set up trampoline code */ /* Set up trampoline code */
mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry); mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry);
bus_space_write_region_4(fdtbus_bs_tag, ram, 0, bus_space_write_region_4(fdtbus_bs_tag, ram, 0,
(uint32_t *)&socfpga_trampoline, 8); (uint32_t *)&socfpga_trampoline, 8);
dcache_wbinv_poc_all(); dcache_wbinv_poc_all();
/* Put CPU1 out from reset */ /* Put CPU1 out from reset */
if (platid == SOCFPGA_SOCDK) { switch (platid) {
#if defined(SOC_ALTERA_ARRIA10)
case SOCFPGA_ARRIA10:
bus_space_write_4(fdtbus_bs_tag, rst, bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_A10_MPUMODRST, 0); RSTMGR_A10_MPUMODRST, 0);
} else { break;
#endif
#if defined(SOC_ALTERA_CYCLONE5)
case SOCFPGA_CYCLONE5:
bus_space_write_4(fdtbus_bs_tag, rst, bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_MPUMODRST, 0); RSTMGR_MPUMODRST, 0);
break;
#endif
default:
panic("Unknown platform id %d\n", platid);
} }
dsb(); dsb();
sev(); sev();
bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE); bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE);
bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE); bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE);
} }
#if defined(SOC_ALTERA_ARRIA10)
void void
socfpga_a10_mp_start_ap(platform_t plat) socfpga_a10_mp_start_ap(platform_t plat)
{ {
_socfpga_mp_start_ap(plat, SOCFPGA_SOCDK); _socfpga_mp_start_ap(SOCFPGA_ARRIA10);
} }
#endif
#if defined(SOC_ALTERA_CYCLONE5)
void void
socfpga_mp_start_ap(platform_t plat) socfpga_mp_start_ap(platform_t plat)
{ {
_socfpga_mp_start_ap(plat, SOCFPGA_SOCKIT); _socfpga_mp_start_ap(SOCFPGA_CYCLONE5);
} }
#endif