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Differential D9407 Diff 24701 sys/mips/mips/exception.S

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sys/mips/mips/exception.S

Show First 20 Lines • Show All 184 Lines • ▼ Show 20 Lines and k0, k0, MIPS_SR_KSU_USER # test for user mode
# with us........ # with us........
sll k0, k0, 3 # shift user bit for cause index sll k0, k0, 3 # shift user bit for cause index
and k1, k1, MIPS_CR_EXC_CODE # Mask out the cause bits. and k1, k1, MIPS_CR_EXC_CODE # Mask out the cause bits.
or k1, k1, k0 # change index to user table or k1, k1, k0 # change index to user table
#if defined(__mips_n64) #if defined(__mips_n64)
PTR_SLL k1, k1, 1 # shift to get 8-byte offset PTR_SLL k1, k1, 1 # shift to get 8-byte offset
#endif #endif
1: 1:
.set at
PTR_LA k0, _C_LABEL(machExceptionTable) # get base of the jump table PTR_LA k0, _C_LABEL(machExceptionTable) # get base of the jump table
.set noat
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PTR_ADDU k0, k0, k1 # Get the address of the PTR_ADDU k0, k0, k1 # Get the address of the
# function entry. Note that # function entry. Note that
# the cause is already # the cause is already
# shifted left by 2 bits so # shifted left by 2 bits so
# we dont have to shift. # we dont have to shift.
PTR_L k0, 0(k0) # Get the function address PTR_L k0, 0(k0) # Get the function address
nop nop
j k0 # Jump to the function. j k0 # Jump to the function.
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#if defined(__mips_n64) #if defined(__mips_n64)
or t1, t0, MIPS_SR_COP_1_BIT | MIPS_SR_FR or t1, t0, MIPS_SR_COP_1_BIT | MIPS_SR_FR
#else #else
or t1, t0, MIPS_SR_COP_1_BIT or t1, t0, MIPS_SR_COP_1_BIT
#endif #endif
mtc0 t1, MIPS_COP_0_STATUS mtc0 t1, MIPS_COP_0_STATUS
HAZARD_DELAY HAZARD_DELAY
ITLBNOPFIX ITLBNOPFIX
.set push
.set hardfloat
cfc1 t1, MIPS_FPU_CSR # stall til FP done cfc1 t1, MIPS_FPU_CSR # stall til FP done
cfc1 t1, MIPS_FPU_CSR # now get status cfc1 t1, MIPS_FPU_CSR # now get status
.set pop
nop nop
sll t2, t1, (31 - 17) # unimplemented operation? sll t2, t1, (31 - 17) # unimplemented operation?
bgez t2, 3f # no, normal trap bgez t2, 3f # no, normal trap
nop nop
/* /*
* We got an unimplemented operation trap so * We got an unimplemented operation trap so
* fetch the instruction, compute the next PC and emulate the instruction. * fetch the instruction, compute the next PC and emulate the instruction.
*/ */
Show All 40 Lines */
beq a3, MIPS_OPCODE_C1, 4f # this should never fail beq a3, MIPS_OPCODE_C1, 4f # this should never fail
nop nop
/* /*
* Send a floating point exception signal to the current process. * Send a floating point exception signal to the current process.
*/ */
3: 3:
GET_CPU_PCPU(a0) GET_CPU_PCPU(a0)
PTR_L a0, PC_CURTHREAD(a0) # get current thread PTR_L a0, PC_CURTHREAD(a0) # get current thread
.set push
.set hardfloat
cfc1 a2, MIPS_FPU_CSR # code = FP execptions cfc1 a2, MIPS_FPU_CSR # code = FP execptions
ctc1 zero, MIPS_FPU_CSR # Clear exceptions ctc1 zero, MIPS_FPU_CSR # Clear exceptions
.set pop
PTR_LA t3, _C_LABEL(trapsignal) PTR_LA t3, _C_LABEL(trapsignal)
jalr t3 jalr t3
li a1, SIGFPE li a1, SIGFPE
b FPReturn b FPReturn
nop nop
/* /*
* Finally, we can call MipsEmulateFP() where a0 is the instruction to emulate. * Finally, we can call MipsEmulateFP() where a0 is the instruction to emulate.
▲ Show 20 Lines • Show All 91 Lines • Show Last 20 Lines