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head/sys/mips/ingenic/jz4780_codec.h
| Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines | |||||
| #define CR_ADC 0x18 /* ADC Control Register */ | #define CR_ADC 0x18 /* ADC Control Register */ | ||||
| #define CR_MIX 0x19 /* Digital Mixer Control Register */ | #define CR_MIX 0x19 /* Digital Mixer Control Register */ | ||||
| #define DR_MIX 0x1A /* Digital Mixer Data Register */ | #define DR_MIX 0x1A /* Digital Mixer Data Register */ | ||||
| #define CR_VIC 0x1B /* Control Register for the ViC */ | #define CR_VIC 0x1B /* Control Register for the ViC */ | ||||
| #define VIC_SB_SLEEP (1 << 1) /* sleep mode */ | #define VIC_SB_SLEEP (1 << 1) /* sleep mode */ | ||||
| #define VIC_SB (1 << 0) /* complete power-down */ | #define VIC_SB (1 << 0) /* complete power-down */ | ||||
| #define CR_CK 0x1C /* Clock Control Register */ | #define CR_CK 0x1C /* Clock Control Register */ | ||||
| #define FCR_DAC 0x1D /* DAC Frequency Control Register */ | #define FCR_DAC 0x1D /* DAC Frequency Control Register */ | ||||
| #define FCR_DAC_48 8 /* 48 kHz. */ | |||||
| #define FCR_DAC_96 10 /* 96 kHz. */ | #define FCR_DAC_96 10 /* 96 kHz. */ | ||||
| #define FCR_ADC 0x20 /* ADC Frequency Control Register */ | #define FCR_ADC 0x20 /* ADC Frequency Control Register */ | ||||
| #define CR_TIMER_MSB 0x21 /* MSB of programmable counter */ | #define CR_TIMER_MSB 0x21 /* MSB of programmable counter */ | ||||
| #define CR_TIMER_LSB 0x22 /* LSB of programmable counter */ | #define CR_TIMER_LSB 0x22 /* LSB of programmable counter */ | ||||
| #define ICR 0x23 /* Interrupt Control Register */ | #define ICR 0x23 /* Interrupt Control Register */ | ||||
| #define IMR 0x24 /* Interrupt Mask Register */ | #define IMR 0x24 /* Interrupt Mask Register */ | ||||
| #define IFR 0x25 /* Interrupt Flag Register */ | #define IFR 0x25 /* Interrupt Flag Register */ | ||||
| #define IMR2 0x26 /* Interrupt Mask Register 2 */ | #define IMR2 0x26 /* Interrupt Mask Register 2 */ | ||||
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