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Differential D8804 Diff 23183 head/sys/dev/iwn/if_iwn.c

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head/sys/dev/iwn/if_iwn.c

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{ {
/* Disable interrupts. */ /* Disable interrupts. */
IWN_WRITE(sc, IWN_INT_MASK, 0); IWN_WRITE(sc, IWN_INT_MASK, 0);
/* Reset ICT table. */ /* Reset ICT table. */
memset(sc->ict, 0, IWN_ICT_SIZE); memset(sc->ict, 0, IWN_ICT_SIZE);
sc->ict_cur = 0; sc->ict_cur = 0;
bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map,
BUS_DMASYNC_PREWRITE);
/* Set physical address of ICT table (4KB aligned). */ /* Set physical address of ICT table (4KB aligned). */
DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__);
IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE |
IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12);
/* Enable periodic RX interrupt. */ /* Enable periodic RX interrupt. */
sc->int_mask |= IWN_INT_RX_PERIODIC; sc->int_mask |= IWN_INT_RX_PERIODIC;
/* Switch to ICT interrupt mode in driver. */ /* Switch to ICT interrupt mode in driver. */
▲ Show 20 Lines • Show All 1,964 Lines • ▼ Show 20 Linesiwn_intr(void *arg)
IWN_LOCK(sc); IWN_LOCK(sc);
/* Disable interrupts. */ /* Disable interrupts. */
IWN_WRITE(sc, IWN_INT_MASK, 0); IWN_WRITE(sc, IWN_INT_MASK, 0);
/* Read interrupts from ICT (fast) or from registers (slow). */ /* Read interrupts from ICT (fast) or from registers (slow). */
if (sc->sc_flags & IWN_FLAG_USE_ICT) { if (sc->sc_flags & IWN_FLAG_USE_ICT) {
bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map,
BUS_DMASYNC_POSTREAD);
tmp = 0; tmp = 0;
while (sc->ict[sc->ict_cur] != 0) { while (sc->ict[sc->ict_cur] != 0) {
tmp |= sc->ict[sc->ict_cur]; tmp |= sc->ict[sc->ict_cur];
sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ sc->ict[sc->ict_cur] = 0; /* Acknowledge. */
sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT;
} }
tmp = le32toh(tmp); tmp = le32toh(tmp);
if (tmp == 0xffffffff) /* Shouldn't happen. */ if (tmp == 0xffffffff) /* Shouldn't happen. */
▲ Show 20 Lines • Show All 519 Lines • ▼ Show 20 Linesiwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
for (i = 1; i <= nsegs; i++) { for (i = 1; i <= nsegs; i++) {
desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) |
seg->ds_len << 4); seg->ds_len << 4);
seg++; seg++;
} }
bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map,
BUS_DMASYNC_PREWRITE); BUS_DMASYNC_PREWRITE);
bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
BUS_DMASYNC_PREWRITE); BUS_DMASYNC_PREWRITE);
/* Update TX scheduler. */ /* Update TX scheduler. */
if (ring->qid >= sc->firstaggqueue) if (ring->qid >= sc->firstaggqueue)
ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
▲ Show 20 Lines • Show All 176 Lines • ▼ Show 20 Linesiwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m,
for (i = 1; i <= nsegs; i++) { for (i = 1; i <= nsegs; i++) {
desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) |
seg->ds_len << 4); seg->ds_len << 4);
seg++; seg++;
} }
bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map,
BUS_DMASYNC_PREWRITE); BUS_DMASYNC_PREWRITE);
bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
BUS_DMASYNC_PREWRITE); BUS_DMASYNC_PREWRITE);
/* Update TX scheduler. */ /* Update TX scheduler. */
if (ring->qid >= sc->firstaggqueue) if (ring->qid >= sc->firstaggqueue)
ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
▲ Show 20 Lines • Show All 316 Lines • ▼ Show 20 Linesiwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async)
DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n",
__func__, iwn_intr_str(cmd->code), cmd->code, __func__, iwn_intr_str(cmd->code), cmd->code,
cmd->flags, cmd->qid, cmd->idx); cmd->flags, cmd->qid, cmd->idx);
if (size > sizeof cmd->data) { if (size > sizeof cmd->data) {
bus_dmamap_sync(ring->data_dmat, data->map, bus_dmamap_sync(ring->data_dmat, data->map,
BUS_DMASYNC_PREWRITE); BUS_DMASYNC_PREWRITE);
} else { } else {
bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map,
BUS_DMASYNC_PREWRITE); BUS_DMASYNC_PREWRITE);
} }
bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
BUS_DMASYNC_PREWRITE); BUS_DMASYNC_PREWRITE);
/* Kick command ring. */ /* Kick command ring. */
ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
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