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Differential D8802 Diff 22943 sys/dev/etherswitch/infineon/adm6996fc.c

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sys/dev/etherswitch/infineon/adm6996fc.c

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*/ */
/* /*
* This is Infineon ADM6996FC/M/MX driver code on etherswitch framework. * This is Infineon ADM6996FC/M/MX driver code on etherswitch framework.
* Support PORT and DOT1Q VLAN. * Support PORT and DOT1Q VLAN.
* This code suppose ADM6996FC SDC/SDIO connect to SOC network interface * This code suppose ADM6996FC SDC/SDIO connect to SOC network interface
* MDC/MDIO. * MDC/MDIO.
* This code development on Netgear WGR614Cv7. * This code development on Netgear WGR614Cv7.
* etherswitchcfg command port option support addtag.
*/ */
#include <sys/param.h> #include <sys/param.h>
#include <sys/bus.h> #include <sys/bus.h>
#include <sys/errno.h> #include <sys/errno.h>
#include <sys/kernel.h> #include <sys/kernel.h>
#include <sys/lock.h> #include <sys/lock.h>
#include <sys/malloc.h> #include <sys/malloc.h>
▲ Show 20 Lines • Show All 411 Lines • ▼ Show 20 Lines if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
if (p->es_port == 4) if (p->es_port == 4)
data2 = (data2 >> 8) & 0xff; data2 = (data2 >> 8) & 0xff;
else else
data2 = data2 & 0xff; data2 = data2 & 0xff;
p->es_pvid = ADM6996FC_PVIDBYDATA(data1, data2); p->es_pvid = ADM6996FC_PVIDBYDATA(data1, data2);
if (((data1 >> ADM6996FC_OPTE_SHIFT) & 0x01) == 1) if (((data1 >> ADM6996FC_OPTE_SHIFT) & 0x01) == 1)
p->es_flags |= ETHERSWITCH_PORT_ADDTAG; p->es_flags |= ETHERSWITCH_PORT_ADDTAG;
else
p->es_flags |= ETHERSWITCH_PORT_STRIPTAG;
} else { } else {
p->es_pvid = 0; p->es_pvid = 0;
} }
phy = sc->portphy[p->es_port]; phy = sc->portphy[p->es_port];
mii = adm6996fc_miiforport(sc, p->es_port); mii = adm6996fc_miiforport(sc, p->es_port);
if (sc->cpuport != -1 && phy == sc->cpuport) { if (sc->cpuport != -1 && phy == sc->cpuport) {
/* fill in fixed values for CPU port */ /* fill in fixed values for CPU port */
Show All 37 Linesadm6996fc_setport(device_t dev, etherswitch_port_t *p)
if (p->es_port < 0 || p->es_port >= sc->numports) if (p->es_port < 0 || p->es_port >= sc->numports)
return (ENXIO); return (ENXIO);
if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
data = ADM6996FC_READREG(parent, bcaddr[p->es_port]); data = ADM6996FC_READREG(parent, bcaddr[p->es_port]);
data &= ~(0xf << 10); data &= ~(0xf << 10);
data |= (p->es_pvid & 0xf) << ADM6996FC_PVID_SHIFT; data |= (p->es_pvid & 0xf) << ADM6996FC_PVID_SHIFT;
if (p->es_flags & ETHERSWITCH_PORT_ADDTAG)
data |= 1 << ADM6996FC_OPTE_SHIFT;
else
data &= ~(1 << ADM6996FC_OPTE_SHIFT);
ADM6996FC_WRITEREG(parent, bcaddr[p->es_port], data); ADM6996FC_WRITEREG(parent, bcaddr[p->es_port], data);
data = ADM6996FC_READREG(parent, vidaddr[p->es_port]); data = ADM6996FC_READREG(parent, vidaddr[p->es_port]);
/* only port 4 is hi bit */ /* only port 4 is hi bit */
if (p->es_port == 4) { if (p->es_port == 4) {
data &= ~(0xff << 8); data &= ~(0xff << 8);
data = data | (((p->es_pvid >> 4) & 0xff) << 8); data = data | (((p->es_pvid >> 4) & 0xff) << 8);
} else { } else {
data &= ~0xff; data &= ~0xff;
▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines if (conf->vlan_mode == ETHERSWITCH_VLAN_PORT) {
data = ADM6996FC_READREG(parent, ADM6996FC_SC3); data = ADM6996FC_READREG(parent, ADM6996FC_SC3);
data |= (1 << ADM6996FC_TBV_SHIFT); data |= (1 << ADM6996FC_TBV_SHIFT);
ADM6996FC_WRITEREG(parent, ADM6996FC_SC3, data); ADM6996FC_WRITEREG(parent, ADM6996FC_SC3, data);
for (i = 0;i <= 5; ++i) { for (i = 0;i <= 5; ++i) {
data = ADM6996FC_READREG(parent, bcaddr[i]); data = ADM6996FC_READREG(parent, bcaddr[i]);
/* Private VID set 1 */ /* Private VID set 1 */
data &= ~(0xf << 10); data &= ~(0xf << 10);
data |= (1 << 10); data |= (1 << 10);
/* Output Packet Tagging Enable */
if (i == 5)
data |= (1 << 4);
ADM6996FC_WRITEREG(parent, bcaddr[i], data); ADM6996FC_WRITEREG(parent, bcaddr[i], data);
} }
for (i = 2;i <= 15; ++i) { for (i = 2;i <= 15; ++i) {
ADM6996FC_WRITEREG(parent, ADM6996FC_VF0H + 2 * i, ADM6996FC_WRITEREG(parent, ADM6996FC_VF0H + 2 * i,
0x0000); 0x0000);
} }
} else { } else {
/* /*
▲ Show 20 Lines • Show All 175 Lines • Show Last 20 Lines