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sys/dev/mvs/mvs.c
Show First 20 Lines • Show All 1,409 Lines • ▼ Show 20 Lines | if (ch->basic_dma) { | ||||
ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd); | ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd); | ||||
ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16); | ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16); | ||||
ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START | | ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START | | ||||
(((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ? | (((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ? | ||||
DMA_C_READ : 0)); | DMA_C_READ : 0)); | ||||
} | } | ||||
} | } | ||||
/* Start command execution timeout */ | /* Start command execution timeout */ | ||||
callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, | callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout, 0, | ||||
(timeout_t*)mvs_timeout, slot); | (timeout_t*)mvs_timeout, slot, 0); | ||||
} | } | ||||
/* Must be called with channel locked. */ | /* Must be called with channel locked. */ | ||||
static void | static void | ||||
mvs_execute_transaction(struct mvs_slot *slot) | mvs_execute_transaction(struct mvs_slot *slot) | ||||
{ | { | ||||
device_t dev = slot->dev; | device_t dev = slot->dev; | ||||
struct mvs_channel *ch = device_get_softc(dev); | struct mvs_channel *ch = device_get_softc(dev); | ||||
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines | bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, | ||||
BUS_DMASYNC_PREREAD); | BUS_DMASYNC_PREREAD); | ||||
slot->state = MVS_SLOT_RUNNING; | slot->state = MVS_SLOT_RUNNING; | ||||
ch->rslots |= (1 << slot->slot); | ch->rslots |= (1 << slot->slot); | ||||
/* Issue command to the controller. */ | /* Issue command to the controller. */ | ||||
ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1); | ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1); | ||||
ATA_OUTL(ch->r_mem, EDMA_REQQIP, | ATA_OUTL(ch->r_mem, EDMA_REQQIP, | ||||
ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); | ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); | ||||
/* Start command execution timeout */ | /* Start command execution timeout */ | ||||
callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, | callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout, 0, | ||||
(timeout_t*)mvs_timeout, slot); | (timeout_t*)mvs_timeout, slot, 0); | ||||
return; | return; | ||||
} | } | ||||
/* Must be called with channel locked. */ | /* Must be called with channel locked. */ | ||||
static void | static void | ||||
mvs_process_timeout(device_t dev) | mvs_process_timeout(device_t dev) | ||||
{ | { | ||||
struct mvs_channel *ch = device_get_softc(dev); | struct mvs_channel *ch = device_get_softc(dev); | ||||
Show All 20 Lines | mvs_rearm_timeout(device_t dev) | ||||
for (i = 0; i < MVS_MAX_SLOTS; i++) { | for (i = 0; i < MVS_MAX_SLOTS; i++) { | ||||
struct mvs_slot *slot = &ch->slot[i]; | struct mvs_slot *slot = &ch->slot[i]; | ||||
/* Do we have a running request on slot? */ | /* Do we have a running request on slot? */ | ||||
if (slot->state < MVS_SLOT_RUNNING) | if (slot->state < MVS_SLOT_RUNNING) | ||||
continue; | continue; | ||||
if ((ch->toslots & (1 << i)) == 0) | if ((ch->toslots & (1 << i)) == 0) | ||||
continue; | continue; | ||||
callout_reset(&slot->timeout, | callout_reset_sbt(&slot->timeout, | ||||
(int)slot->ccb->ccb_h.timeout * hz / 2000, | SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, | ||||
(timeout_t*)mvs_timeout, slot); | (timeout_t*)mvs_timeout, slot, 0); | ||||
} | } | ||||
} | } | ||||
/* Locked by callout mechanism. */ | /* Locked by callout mechanism. */ | ||||
static void | static void | ||||
mvs_timeout(struct mvs_slot *slot) | mvs_timeout(struct mvs_slot *slot) | ||||
{ | { | ||||
device_t dev = slot->dev; | device_t dev = slot->dev; | ||||
▲ Show 20 Lines • Show All 874 Lines • Show Last 20 Lines |