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sys/dev/e1000/if_igb.h
Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines | |||||
#include <net/bpf.h> | #include <net/bpf.h> | ||||
#include <net/ethernet.h> | #include <net/ethernet.h> | ||||
#include <net/if.h> | #include <net/if.h> | ||||
#include <net/if_var.h> | #include <net/if_var.h> | ||||
#include <net/if_arp.h> | #include <net/if_arp.h> | ||||
#include <net/if_dl.h> | #include <net/if_dl.h> | ||||
#include <net/if_media.h> | #include <net/if_media.h> | ||||
#include <net/iflib.h> | |||||
#ifdef RSS | #ifdef RSS | ||||
#include <net/rss_config.h> | #include <net/rss_config.h> | ||||
#include <netinet/in_rss.h> | #include <netinet/in_rss.h> | ||||
#endif | #endif | ||||
#include <net/if_types.h> | #include <net/if_types.h> | ||||
#include <net/if_vlan_var.h> | #include <net/if_vlan_var.h> | ||||
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/* Tunables */ | /* Tunables */ | ||||
/* | /* | ||||
* IGB_TXD: Maximum number of Transmit Descriptors | * IGB_TXD: Maximum number of Transmit Descriptors | ||||
* | * | ||||
* This value is the number of transmit descriptors allocated by the driver. | * This value is the number of transmit descriptors allocated by the driver. | ||||
* Increasing this value allows the driver to queue more transmits. Each | * Increasing this value allows the driver to queue more transmits. Each | ||||
* descriptor is 16 bytes. | * descriptor is 16 bytes. | ||||
* Since TDLEN should be multiple of 128bytes, the number of transmit | * Since TDLEN should be multiple of 128bytes, the number of transmit | ||||
* desscriptors should meet the following condition. | * descriptors should meet the following condition. | ||||
* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 | * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 | ||||
*/ | */ | ||||
#define IGB_MIN_TXD 256 | #define IGB_MIN_TXD 128 | ||||
#define IGB_DEFAULT_TXD 1024 | #define IGB_DEFAULT_TXD 1024 | ||||
#define IGB_MAX_TXD 4096 | #define IGB_MAX_TXD 4096 | ||||
/* | /* | ||||
* IGB_RXD: Maximum number of Receive Descriptors | * IGB_RXD: Maximum number of Receive Descriptors | ||||
* | * | ||||
* This value is the number of receive descriptors allocated by the driver. | * This value is the number of receive descriptors allocated by the driver. | ||||
* Increasing this value allows the driver to buffer more incoming packets. | * Increasing this value allows the driver to buffer more incoming packets. | ||||
* Each descriptor is 16 bytes. A receive buffer is also allocated for each | * Each descriptor is 16 bytes. A receive buffer is also allocated for each | ||||
* descriptor. The maximum MTU size is 16110. | * descriptor. The maximum MTU size is 16110. | ||||
* Since TDLEN should be multiple of 128bytes, the number of transmit | * Since TDLEN should be multiple of 128bytes, the number of transmit | ||||
* desscriptors should meet the following condition. | * descriptors should meet the following condition. | ||||
* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 | * (num_rx_desc * sizeof(struct e1000_rx_desc)) % 128 == 0 | ||||
*/ | */ | ||||
#define IGB_MIN_RXD 256 | #define IGB_MIN_RXD 128 | ||||
#define IGB_DEFAULT_RXD 1024 | #define IGB_DEFAULT_RXD 1024 | ||||
#define IGB_MAX_RXD 4096 | #define IGB_MAX_RXD 4096 | ||||
/* | /* | ||||
* IGB_TIDV - Transmit Interrupt Delay Value | * IGB_TIDV - Transmit Interrupt Delay Value | ||||
* Valid Range: 0-65535 (0=off) | * Valid Range: 0-65535 (0=off) | ||||
* Default Value: 64 | * Default Value: 64 | ||||
* This value delays the generation of transmit interrupts in units of | * This value delays the generation of transmit interrupts in units of | ||||
* 1.024 microseconds. Transmit interrupt reduction can improve CPU | * 1.024 microseconds. Transmit interrupt reduction can improve CPU | ||||
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#define IGB_SMARTSPEED_DOWNSHIFT 3 | #define IGB_SMARTSPEED_DOWNSHIFT 3 | ||||
#define IGB_SMARTSPEED_MAX 15 | #define IGB_SMARTSPEED_MAX 15 | ||||
#define IGB_MAX_LOOP 10 | #define IGB_MAX_LOOP 10 | ||||
#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ | #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ | ||||
((hw->mac.type <= e1000_82576) ? 16 : 8)) | ((hw->mac.type <= e1000_82576) ? 16 : 8)) | ||||
#define IGB_RX_HTHRESH 8 | #define IGB_RX_HTHRESH 8 | ||||
#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ | #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ | ||||
adapter->msix_mem) ? 1 : 4) | (adapter->intr_type == IFLIB_INTR_MSIX)) ? 1 : 4) | ||||
#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) | #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) | ||||
#define IGB_TX_HTHRESH 1 | #define IGB_TX_HTHRESH 1 | ||||
#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ | #define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ | ||||
adapter->msix_mem) ? 1 : 16) | (adapter->msix_mem) ? 1 : 16) | ||||
#define MAX_NUM_MULTICAST_ADDRESSES 128 | #define MAX_NUM_MULTICAST_ADDRESSES 128 | ||||
#define PCI_ANY_ID (~0U) | #define PCI_ANY_ID (~0U) | ||||
#define ETHER_ALIGN 2 | #define ETHER_ALIGN 2 | ||||
#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) | #define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) | ||||
#define IGB_FC_PAUSE_TIME 0x0680 | #define IGB_FC_PAUSE_TIME 0x0680 | ||||
#define IGB_EEPROM_APME 0x400; | #define IGB_EEPROM_APME 0x400; | ||||
/* Queue minimum free for use */ | /* Queue minimum free for use */ | ||||
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines | struct igb_dma_alloc { | ||||
bus_addr_t dma_paddr; | bus_addr_t dma_paddr; | ||||
caddr_t dma_vaddr; | caddr_t dma_vaddr; | ||||
bus_dma_tag_t dma_tag; | bus_dma_tag_t dma_tag; | ||||
bus_dmamap_t dma_map; | bus_dmamap_t dma_map; | ||||
bus_dma_segment_t dma_seg; | bus_dma_segment_t dma_seg; | ||||
int dma_nseg; | int dma_nseg; | ||||
}; | }; | ||||
/* | /* | ||||
** Driver queue struct: this is the interrupt container | |||||
** for the associated tx and rx ring. | |||||
*/ | |||||
struct igb_queue { | |||||
struct adapter *adapter; | |||||
u32 msix; /* This queue's MSIX vector */ | |||||
u32 eims; /* This queue's EIMS bit */ | |||||
u32 eitr_setting; | |||||
struct resource *res; | |||||
void *tag; | |||||
struct tx_ring *txr; | |||||
struct rx_ring *rxr; | |||||
struct task que_task; | |||||
struct taskqueue *tq; | |||||
u64 irqs; | |||||
}; | |||||
/* | |||||
* The transmit ring, one per queue | * The transmit ring, one per queue | ||||
*/ | */ | ||||
struct tx_ring { | struct tx_ring { | ||||
struct adapter *adapter; | struct adapter *adapter; | ||||
struct mtx tx_mtx; | struct igb_tx_queue *que; | ||||
u32 me; | u32 me; | ||||
u32 tail; | |||||
int watchdog_time; | int watchdog_time; | ||||
union e1000_adv_tx_desc *tx_base; | union e1000_adv_tx_desc *tx_base; | ||||
struct igb_tx_buf *tx_buffers; | struct igb_tx_buf *tx_buffers; | ||||
struct igb_dma_alloc txdma; | uint64_t tx_paddr; | ||||
volatile u16 tx_avail; | volatile u16 tx_avail; | ||||
u16 next_avail_desc; | |||||
u16 next_to_clean; | |||||
u16 num_desc; | |||||
enum { | enum { | ||||
IGB_QUEUE_IDLE = 1, | IGB_QUEUE_IDLE = 1, | ||||
IGB_QUEUE_WORKING = 2, | IGB_QUEUE_WORKING = 2, | ||||
IGB_QUEUE_HUNG = 4, | IGB_QUEUE_HUNG = 4, | ||||
IGB_QUEUE_DEPLETED = 8, | IGB_QUEUE_DEPLETED = 8, | ||||
} queue_status; | } queue_status; | ||||
u32 txd_cmd; | u32 txd_cmd; | ||||
bus_dma_tag_t txtag; | |||||
char mtx_name[16]; | |||||
#ifndef IGB_LEGACY_TX | |||||
struct buf_ring *br; | |||||
struct task txq_task; | |||||
#endif | |||||
u32 bytes; /* used for AIM */ | u32 bytes; /* used for AIM */ | ||||
u32 packets; | u32 packets; | ||||
/* Soft Stats */ | /* Soft Stats */ | ||||
unsigned long tso_tx; | unsigned long tso_tx; | ||||
unsigned long no_tx_map_avail; | unsigned long no_tx_map_avail; | ||||
unsigned long no_tx_dma_setup; | unsigned long no_tx_dma_setup; | ||||
u64 no_desc_avail; | u64 no_desc_avail; | ||||
u64 total_packets; | u64 total_packets; | ||||
}; | }; | ||||
/* | /* | ||||
* Receive ring: one per queue | * Receive ring: one per queue | ||||
*/ | */ | ||||
struct rx_ring { | struct rx_ring { | ||||
struct adapter *adapter; | struct adapter *adapter; | ||||
struct igb_rx_queue *que; | |||||
u32 me; | u32 me; | ||||
struct igb_dma_alloc rxdma; | u32 tail; | ||||
union e1000_adv_rx_desc *rx_base; | union e1000_adv_rx_desc *rx_base; | ||||
uint64_t rx_paddr; | |||||
struct lro_ctrl lro; | struct lro_ctrl lro; | ||||
bool lro_enabled; | bool lro_enabled; | ||||
bool hdr_split; | bool hdr_split; | ||||
struct mtx rx_mtx; | |||||
char mtx_name[16]; | |||||
u32 next_to_refresh; | |||||
u32 next_to_check; | |||||
struct igb_rx_buf *rx_buffers; | struct igb_rx_buf *rx_buffers; | ||||
bus_dma_tag_t htag; /* dma tag for rx head */ | |||||
bus_dma_tag_t ptag; /* dma tag for rx packet */ | |||||
/* | |||||
* First/last mbuf pointers, for | |||||
* collecting multisegment RX packets. | |||||
*/ | |||||
struct mbuf *fmp; | |||||
struct mbuf *lmp; | |||||
u32 bytes; | u32 bytes; | ||||
u32 packets; | u32 packets; | ||||
int rdt; | int rdt; | ||||
int rdh; | int rdh; | ||||
/* Soft stats */ | /* Soft stats */ | ||||
u64 rx_split_packets; | u64 rx_split_packets; | ||||
u64 rx_discarded; | u64 rx_discarded; | ||||
u64 rx_packets; | u64 rx_packets; | ||||
u64 rx_bytes; | u64 rx_bytes; | ||||
}; | }; | ||||
/* | |||||
** Driver queue struct: this is the interrupt container | |||||
** for the associated tx and rx ring. | |||||
*/ | |||||
struct igb_tx_queue { | |||||
struct adapter *adapter; | |||||
struct tx_ring txr; | |||||
u32 me; | |||||
u32 eims; | |||||
u32 msix; | |||||
}; | |||||
struct igb_rx_queue { | |||||
struct adapter *adapter; | |||||
u32 msix; /* This queue's MSIX vector */ | |||||
u32 eims; /* This queue's EIMS bit */ | |||||
u32 eitr_setting; | |||||
u32 me; | |||||
struct resource *res; | |||||
void *tag; | |||||
struct rx_ring rxr; | |||||
u64 irqs; | |||||
struct if_irq que_irq; | |||||
}; | |||||
struct adapter { | struct adapter { | ||||
if_softc_ctx_t shared; | |||||
if_ctx_t ctx; | |||||
#define tx_num_queues shared->isc_ntxqsets | |||||
#define rx_num_queues shared->isc_nrxqsets | |||||
#define max_frame_size shared->isc_max_frame_size | |||||
#define intr_type shared->isc_intr | |||||
struct ifnet *ifp; | struct ifnet *ifp; | ||||
struct e1000_hw hw; | struct e1000_hw hw; | ||||
struct e1000_osdep osdep; | struct e1000_osdep osdep; | ||||
device_t dev; | struct device *dev; | ||||
struct cdev *led_dev; | struct cdev *led_dev; | ||||
struct if_irq irq; | |||||
struct resource *pci_mem; | struct resource *pci_mem; | ||||
struct resource *msix_mem; | |||||
int memrid; | int memrid; | ||||
struct igb_tx_queue *tx_queues; | |||||
struct igb_rx_queue *rx_queues; | |||||
/* | /* | ||||
* Interrupt resources: this set is | * Interrupt resources: this set is | ||||
* either used for legacy, or for Link | * either used for legacy, or for Link | ||||
* when doing MSIX | * when doing MSIX | ||||
*/ | */ | ||||
void *tag; | void *tag; | ||||
struct resource *res; | struct resource *res; | ||||
struct ifmedia media; | struct ifmedia *media; | ||||
struct callout timer; | |||||
int msix; | |||||
int if_flags; | int if_flags; | ||||
int pause_frames; | int pause_frames; | ||||
struct mtx core_mtx; | |||||
eventhandler_tag vlan_attach; | |||||
eventhandler_tag vlan_detach; | |||||
u16 num_vlans; | |||||
u16 num_queues; | |||||
/* | /* | ||||
** Shadow VFTA table, this is needed because | ** Shadow VFTA table, this is needed because | ||||
** the real vlan filter table gets cleared during | ** the real vlan filter table gets cleared during | ||||
** a soft reset and the driver needs to be able | ** a soft reset and the driver needs to be able | ||||
** to repopulate it. | ** to repopulate it. | ||||
*/ | */ | ||||
u32 shadow_vfta[IGB_VFTA_SIZE]; | u32 shadow_vfta[IGB_VFTA_SIZE]; | ||||
/* Info about the interface */ | /* Info about the interface */ | ||||
u32 optics; | u32 optics; | ||||
u32 fc; /* local flow ctrl setting */ | u32 fc; /* local flow ctrl setting */ | ||||
int advertise; /* link speeds */ | int advertise; /* link speeds */ | ||||
bool link_active; | bool link_active; | ||||
u16 max_frame_size; | |||||
u16 num_segs; | u16 num_segs; | ||||
u16 link_speed; | u16 link_speed; | ||||
bool link_up; | bool link_up; | ||||
u32 linkvec; | u32 linkvec; | ||||
u16 link_duplex; | u16 link_duplex; | ||||
u32 dmac; | u32 dmac; | ||||
int link_mask; | int link_mask; | ||||
/* Flags */ | /* Flags */ | ||||
u32 flags; | u32 flags; | ||||
/* Mbuf cluster size */ | /* Mbuf cluster size */ | ||||
u32 rx_mbuf_sz; | u32 rx_mbuf_sz; | ||||
/* Support for pluggable optics */ | /* Support for pluggable optics */ | ||||
bool sfp_probe; | bool sfp_probe; | ||||
struct task link_task; /* Link tasklet */ | |||||
struct task mod_task; /* SFP tasklet */ | |||||
struct task msf_task; /* Multispeed Fiber */ | |||||
struct taskqueue *tq; | |||||
/* | struct grouptask mod_task; /* SFP tasklet */ | ||||
** Queues: | struct grouptask msf_task; /* Multispeed Fiber */ | ||||
** This is the irq holder, it has | |||||
** and RX/TX pair or rings associated | |||||
** with it. | |||||
*/ | |||||
struct igb_queue *queues; | |||||
/* | |||||
* Transmit rings: | |||||
* Allocated at run time, an array of rings. | |||||
*/ | |||||
struct tx_ring *tx_rings; | |||||
u32 num_tx_desc; | |||||
/* | |||||
* Receive rings: | |||||
* Allocated at run time, an array of rings. | |||||
*/ | |||||
struct rx_ring *rx_rings; | |||||
u64 que_mask; | u64 que_mask; | ||||
u32 num_rx_desc; | |||||
/* Multicast array memory */ | /* Multicast array memory */ | ||||
u8 *mta; | u8 *mta; | ||||
/* Misc stats maintained by the driver */ | /* Misc stats maintained by the driver */ | ||||
unsigned long device_control; | unsigned long device_control; | ||||
unsigned long dropped_pkts; | unsigned long dropped_pkts; | ||||
unsigned long eint_mask; | unsigned long eint_mask; | ||||
unsigned long int_mask; | unsigned long int_mask; | ||||
unsigned long link_irq; | |||||
unsigned long mbuf_defrag_failed; | |||||
unsigned long no_tx_dma_setup; | |||||
unsigned long packet_buf_alloc_rx; | unsigned long packet_buf_alloc_rx; | ||||
unsigned long packet_buf_alloc_tx; | unsigned long packet_buf_alloc_tx; | ||||
unsigned long rx_control; | unsigned long rx_control; | ||||
unsigned long rx_overruns; | unsigned long rx_overruns; | ||||
unsigned long watchdog_events; | unsigned long watchdog_events; | ||||
/* Used in pf and vf */ | /* Used in pf and vf */ | ||||
void *stats; | void *stats; | ||||
Show All 19 Lines | typedef struct _igb_vendor_info_t { | ||||
unsigned int vendor_id; | unsigned int vendor_id; | ||||
unsigned int device_id; | unsigned int device_id; | ||||
unsigned int subvendor_id; | unsigned int subvendor_id; | ||||
unsigned int subdevice_id; | unsigned int subdevice_id; | ||||
unsigned int index; | unsigned int index; | ||||
} igb_vendor_info_t; | } igb_vendor_info_t; | ||||
struct igb_tx_buf { | struct igb_tx_buf { | ||||
union e1000_adv_tx_desc *eop; | union e1000_adv_tx_desc *eop; | ||||
struct mbuf *m_head; | |||||
bus_dmamap_t map; | |||||
}; | }; | ||||
struct igb_rx_buf { | struct igb_rx_buf { | ||||
struct mbuf *m_head; | struct mbuf *m_head; | ||||
struct mbuf *m_pack; | struct mbuf *m_pack; | ||||
bus_dmamap_t hmap; /* bus_dma map for header */ | bus_dmamap_t hmap; /* bus_dma map for header */ | ||||
bus_dmamap_t pmap; /* bus_dma map for packet */ | bus_dmamap_t pmap; /* bus_dma map for packet */ | ||||
}; | }; | ||||
/* | |||||
** Find the number of unrefreshed RX descriptors | |||||
*/ | |||||
static inline u16 | |||||
igb_rx_unrefreshed(struct rx_ring *rxr) | |||||
{ | |||||
struct adapter *adapter = rxr->adapter; | |||||
if (rxr->next_to_check > rxr->next_to_refresh) | |||||
return (rxr->next_to_check - rxr->next_to_refresh - 1); | |||||
else | |||||
return ((adapter->num_rx_desc + rxr->next_to_check) - | |||||
rxr->next_to_refresh - 1); | |||||
} | |||||
#define IGB_CORE_LOCK_INIT(_sc, _name) \ | #define IGB_CORE_LOCK_INIT(_sc, _name) \ | ||||
mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) | mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) | ||||
#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) | #define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) | ||||
#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) | #define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) | ||||
#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) | #define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) | ||||
#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) | #define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) | ||||
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