Page MenuHomeFreeBSD
Differential D8138 Diff 21018 head/sys/arm/arm/cpufunc.c

Changeset View

Standalone View

View Options

head/sys/arm/arm/cpufunc.c

Show First 20 Lines • Show All 432 Lines • ▼ Show 20 Linesstruct cpu_functions arm1176_cpufuncs = {
.cf_drain_writebuf = arm11_drain_writebuf, .cf_drain_writebuf = arm11_drain_writebuf,
.cf_sleep = arm11x6_sleep, .cf_sleep = arm11x6_sleep,
/* Soft functions */ /* Soft functions */
.cf_setup = arm11x6_setup .cf_setup = arm11x6_setup
}; };
#endif /*CPU_ARM1176 */ #endif /*CPU_ARM1176 */
#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) #if defined(CPU_CORTEXA8) || defined(CPU_CORTEXA_MP) || defined(CPU_KRAIT)
struct cpu_functions cortexa_cpufuncs = { struct cpu_functions cortexa_cpufuncs = {
/* MMU functions */ /* MMU functions */
.cf_control = cpufunc_control, .cf_control = cpufunc_control,
.cf_setttb = armv7_setttb, .cf_setttb = armv7_setttb,
/* Cache operations */ /* Cache operations */
/* /*
* Note: For CPUs using the PL310 the L2 ops are filled in when the * Note: For CPUs using the PL310 the L2 ops are filled in when the
* L2 cache controller is actually enabled. * L2 cache controller is actually enabled.
*/ */
.cf_l2cache_wbinv_all = cpufunc_nullop, .cf_l2cache_wbinv_all = cpufunc_nullop,
.cf_l2cache_wbinv_range = (void *)cpufunc_nullop, .cf_l2cache_wbinv_range = (void *)cpufunc_nullop,
.cf_l2cache_inv_range = (void *)cpufunc_nullop, .cf_l2cache_inv_range = (void *)cpufunc_nullop,
.cf_l2cache_wb_range = (void *)cpufunc_nullop, .cf_l2cache_wb_range = (void *)cpufunc_nullop,
.cf_l2cache_drain_writebuf = (void *)cpufunc_nullop, .cf_l2cache_drain_writebuf = (void *)cpufunc_nullop,
/* Other functions */ /* Other functions */
.cf_drain_writebuf = armv7_drain_writebuf, .cf_drain_writebuf = armv7_drain_writebuf,
.cf_sleep = armv7_cpu_sleep, .cf_sleep = armv7_cpu_sleep,
/* Soft functions */ /* Soft functions */
.cf_setup = cortexa_setup .cf_setup = cortexa_setup
}; };
#endif /* CPU_CORTEXA */ #endif /* CPU_CORTEXA8 || CPU_CORTEXA_MP || CPU_KRAIT */
/* /*
* Global constants also used by locore.s * Global constants also used by locore.s
*/ */
struct cpu_functions cpufuncs; struct cpu_functions cpufuncs;
u_int cputype; u_int cputype;
#if __ARM_ARCH <= 5 #if __ARM_ARCH <= 5
u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore-v4.s */ u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore-v4.s */
#endif #endif
#if defined(CPU_ARM9) || \ #if defined(CPU_ARM9) || \
defined (CPU_ARM9E) || \ defined (CPU_ARM9E) || \
defined(CPU_ARM1176) || \ defined(CPU_ARM1176) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_FA526) || defined(CPU_MV_PJ4B) || \ defined(CPU_FA526) || defined(CPU_MV_PJ4B) || \
defined(CPU_XSCALE_81342) || \ defined(CPU_XSCALE_81342) || \
defined(CPU_CORTEXA) || defined(CPU_KRAIT) defined(CPU_CORTEXA8) || defined(CPU_CORTEXA_MP) || defined(CPU_KRAIT)
/* Global cache line sizes, use 32 as default */ /* Global cache line sizes, use 32 as default */
int arm_dcache_min_line_size = 32; int arm_dcache_min_line_size = 32;
int arm_icache_min_line_size = 32; int arm_icache_min_line_size = 32;
int arm_idcache_min_line_size = 32; int arm_idcache_min_line_size = 32;
static void get_cachetype_cp15(void); static void get_cachetype_cp15(void);
▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Lines
#endif /* CPU_ARM9E */ #endif /* CPU_ARM9E */
#if defined(CPU_ARM1176) #if defined(CPU_ARM1176)
if (cputype == CPU_ID_ARM1176JZS) { if (cputype == CPU_ID_ARM1176JZS) {
cpufuncs = arm1176_cpufuncs; cpufuncs = arm1176_cpufuncs;
get_cachetype_cp15(); get_cachetype_cp15();
goto out; goto out;
} }
#endif /* CPU_ARM1176 */ #endif /* CPU_ARM1176 */
#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) #if defined(CPU_CORTEXA8) || defined(CPU_CORTEXA_MP) || defined(CPU_KRAIT)
switch(cputype & CPU_ID_SCHEME_MASK) { switch(cputype & CPU_ID_SCHEME_MASK) {
case CPU_ID_CORTEXA5: case CPU_ID_CORTEXA5:
case CPU_ID_CORTEXA7: case CPU_ID_CORTEXA7:
case CPU_ID_CORTEXA8: case CPU_ID_CORTEXA8:
case CPU_ID_CORTEXA9: case CPU_ID_CORTEXA9:
case CPU_ID_CORTEXA12: case CPU_ID_CORTEXA12:
case CPU_ID_CORTEXA15: case CPU_ID_CORTEXA15:
case CPU_ID_CORTEXA53: case CPU_ID_CORTEXA53:
case CPU_ID_CORTEXA57: case CPU_ID_CORTEXA57:
case CPU_ID_CORTEXA72: case CPU_ID_CORTEXA72:
case CPU_ID_KRAIT300: case CPU_ID_KRAIT300:
cpufuncs = cortexa_cpufuncs; cpufuncs = cortexa_cpufuncs;
get_cachetype_cp15(); get_cachetype_cp15();
goto out; goto out;
default: default:
break; break;
} }
#endif /* CPU_CORTEXA */ #endif /* CPU_CORTEXA8 || CPU_CORTEXA_MP || CPU_KRAIT */
#if defined(CPU_MV_PJ4B) #if defined(CPU_MV_PJ4B)
if (cputype == CPU_ID_MV88SV581X_V7 || if (cputype == CPU_ID_MV88SV581X_V7 ||
cputype == CPU_ID_MV88SV584X_V7 || cputype == CPU_ID_MV88SV584X_V7 ||
cputype == CPU_ID_ARM_88SV581X_V7) { cputype == CPU_ID_ARM_88SV581X_V7) {
cpufuncs = pj4bv7_cpufuncs; cpufuncs = pj4bv7_cpufuncs;
get_cachetype_cp15(); get_cachetype_cp15();
goto out; goto out;
▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines#endif
/* And again. */ /* And again. */
cpu_idcache_wbinv_all(); cpu_idcache_wbinv_all();
} }
#endif /* CPU_ARM9E || CPU_ARM10 */ #endif /* CPU_ARM9E || CPU_ARM10 */
#if defined(CPU_ARM1176) \ #if defined(CPU_ARM1176) \
|| defined(CPU_MV_PJ4B) \ || defined(CPU_MV_PJ4B) \
|| defined(CPU_CORTEXA) || defined(CPU_KRAIT) || defined(CPU_CORTEXA8) || defined(CPU_CORTEXA_MP) || defined(CPU_KRAIT)
static __inline void static __inline void
cpu_scc_setup_ccnt(void) cpu_scc_setup_ccnt(void)
{ {
/* This is how you give userland access to the CCNT and PMCn /* This is how you give userland access to the CCNT and PMCn
* registers. * registers.
* BEWARE! This gives write access also, which may not be what * BEWARE! This gives write access also, which may not be what
* you want! * you want!
*/ */
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
pj4bv7_setup(void) pj4bv7_setup(void)
{ {
pj4b_config(); pj4b_config();
cpu_scc_setup_ccnt(); cpu_scc_setup_ccnt();
} }
#endif /* CPU_MV_PJ4B */ #endif /* CPU_MV_PJ4B */
#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) #if defined(CPU_CORTEXA8) || defined(CPU_CORTEXA_MP) || defined(CPU_KRAIT)
void void
cortexa_setup(void) cortexa_setup(void)
{ {
cpu_scc_setup_ccnt(); cpu_scc_setup_ccnt();
} }
#endif /* CPU_CORTEXA */ #endif /* CPU_CORTEXA8 || CPU_CORTEXA_MP || CPU_KRAIT */
#if defined(CPU_FA526) #if defined(CPU_FA526)
void void
fa526_setup(void) fa526_setup(void)
{ {
int cpuctrl, cpuctrlmask; int cpuctrl, cpuctrlmask;
cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
▲ Show 20 Lines • Show All 99 Lines • Show Last 20 Lines