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sys/arm/include/cpufunc.h
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void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); | void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); | ||||
void sheeva_l2cache_wbinv_all (void); | void sheeva_l2cache_wbinv_all (void); | ||||
#endif | #endif | ||||
#if defined(CPU_MV_PJ4B) | #if defined(CPU_MV_PJ4B) | ||||
void armv6_idcache_wbinv_all (void); | void armv6_idcache_wbinv_all (void); | ||||
#endif | #endif | ||||
#if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) | #if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) | ||||
void armv7_setttb (u_int); | void armv7_setttb_up (u_int); | ||||
void armv7_tlb_flushID (void); | void armv7_setttb_smp (u_int); | ||||
void armv7_tlb_flushID_SE (u_int); | void armv7_tlb_flushID_up (void); | ||||
void armv7_tlb_flushID_smp (void); | |||||
void armv7_tlb_flushID_SE_up (u_int); | |||||
void armv7_tlb_flushID_SE_smp (u_int); | |||||
void armv7_icache_sync_range (vm_offset_t, vm_size_t); | void armv7_icache_sync_range (vm_offset_t, vm_size_t); | ||||
void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); | void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); | ||||
void armv7_idcache_inv_all (void); | void armv7_idcache_inv_all (void); | ||||
void armv7_dcache_wbinv_all (void); | void armv7_dcache_wbinv_all (void); | ||||
void armv7_idcache_wbinv_all (void); | void armv7_idcache_wbinv_all_up (void); | ||||
void armv7_idcache_wbinv_all_smp (void); | |||||
void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); | void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); | ||||
void armv7_dcache_inv_range (vm_offset_t, vm_size_t); | void armv7_dcache_inv_range (vm_offset_t, vm_size_t); | ||||
void armv7_dcache_wb_range (vm_offset_t, vm_size_t); | void armv7_dcache_wb_range (vm_offset_t, vm_size_t); | ||||
void armv7_cpu_sleep (int); | void armv7_cpu_sleep (int); | ||||
void armv7_setup (void); | void armv7_setup (void); | ||||
void armv7_context_switch (void); | void armv7_context_switch_up (void); | ||||
void armv7_context_switch_smp (void); | |||||
void armv7_drain_writebuf (void); | void armv7_drain_writebuf (void); | ||||
void armv7_sev (void); | void armv7_sev (void); | ||||
u_int armv7_auxctrl (u_int, u_int); | u_int armv7_auxctrl (u_int, u_int); | ||||
void armadaxp_idcache_wbinv_all (void); | void armadaxp_idcache_wbinv_all (void); | ||||
void cortexa_setup (void); | void cortexa_setup (void); | ||||
#endif | #endif | ||||
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