Differential D8094 Diff 20867 sys/arm/arm/cpufunc_asm_armv7_common.S

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sys/arm/arm/cpufunc_asm_armv7_common.S

This file was copied from sys/arm/arm/cpufunc_asm_armv7.S.

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.Larmv7_icache_line_size:		.Larmv7_icache_line_size:
.word _C_LABEL(arm_icache_min_line_size)		.word _C_LABEL(arm_icache_min_line_size)
.Larmv7_idcache_line_size:		.Larmv7_idcache_line_size:
.word _C_LABEL(arm_idcache_min_line_size)		.word _C_LABEL(arm_idcache_min_line_size)
.Lway_mask:		.Lway_mask:
.word 0x3ff		.word 0x3ff
.Lmax_index:		.Lmax_index:
.word 0x7fff		.word 0x7fff
.Lpage_mask:
.word 0xfff

#define PT_NOS (1 << 5)
#define PT_S (1 << 1)
#define PT_INNER_NC 0
#define PT_INNER_WT (1 << 0)
#define PT_INNER_WB ((1 << 0) \| (1 << 6))
#define PT_INNER_WBWA (1 << 6)
#define PT_OUTER_NC 0
#define PT_OUTER_WT (2 << 3)
#define PT_OUTER_WB (3 << 3)
#define PT_OUTER_WBWA (1 << 3)

#ifdef SMP
#define PT_ATTR (PT_S\|PT_INNER_WBWA\|PT_OUTER_WBWA\|PT_NOS)
#else
#define PT_ATTR (PT_INNER_WBWA\|PT_OUTER_WBWA)
#endif

ENTRY(armv7_setttb)
dsb
orr r0, r0, #PT_ATTR
mcr CP15_TTBR0(r0)
isb
#ifdef SMP
mcr CP15_TLBIALLIS
#else
mcr CP15_TLBIALL
#endif
dsb
isb
RET
END(armv7_setttb)

ENTRY(armv7_tlb_flushID)
dsb
#ifdef SMP
mcr CP15_TLBIALLIS
mcr CP15_BPIALLIS
#else
mcr CP15_TLBIALL
mcr CP15_BPIALL
#endif
dsb
isb
mov pc, lr
END(armv7_tlb_flushID)

ENTRY(armv7_tlb_flushID_SE)
ldr r1, .Lpage_mask
bic r0, r0, r1
#ifdef SMP
mcr CP15_TLBIMVAAIS(r0)
mcr CP15_BPIALLIS
#else
mcr CP15_TLBIMVA(r0)
mcr CP15_BPIALL
#endif
dsb
isb
mov pc, lr
END(armv7_tlb_flushID_SE)

/* Based on algorithm from ARM Architecture Reference Manual */		/* Based on algorithm from ARM Architecture Reference Manual */
ENTRY(armv7_dcache_wbinv_all)		ENTRY(armv7_dcache_wbinv_all)
stmdb sp!, {r4, r5, r6, r7, r8, r9}		stmdb sp!, {r4, r5, r6, r7, r8, r9}

/* Get cache level */		/* Get cache level */
ldr r0, .Lcoherency_level		ldr r0, .Lcoherency_level
ldr r3, [r0]		ldr r3, [r0]
cmp r3, #0		cmp r3, #0
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cmp r3, r8		cmp r3, r8
bne Loop1		bne Loop1
Finished:		Finished:
dsb		dsb
ldmia sp!, {r4, r5, r6, r7, r8, r9}		ldmia sp!, {r4, r5, r6, r7, r8, r9}
RET		RET
END(armv7_dcache_wbinv_all)		END(armv7_dcache_wbinv_all)

ENTRY(armv7_idcache_wbinv_all)
stmdb sp!, {lr}
bl armv7_dcache_wbinv_all
#ifdef SMP
mcr CP15_ICIALLUIS
#else
mcr CP15_ICIALLU
#endif
dsb
isb
ldmia sp!, {lr}
RET
END(armv7_idcache_wbinv_all)

ENTRY(armv7_dcache_wb_range)		ENTRY(armv7_dcache_wb_range)
ldr ip, .Larmv7_dcache_line_size		ldr ip, .Larmv7_dcache_line_size
ldr ip, [ip]		ldr ip, [ip]
sub r3, ip, #1		sub r3, ip, #1
and r2, r0, r3		and r2, r0, r3
add r1, r1, r2		add r1, r1, r2
bic r0, r0, r3		bic r0, r0, r3
.Larmv7_wb_next:		.Larmv7_wb_next:
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines	.Larmv7_sync_next:
RET		RET
END(armv7_icache_sync_range)		END(armv7_icache_sync_range)

ENTRY(armv7_cpu_sleep)		ENTRY(armv7_cpu_sleep)
dsb /* data synchronization barrier */		dsb /* data synchronization barrier */
wfi /* wait for interrupt */		wfi /* wait for interrupt */
RET		RET
END(armv7_cpu_sleep)		END(armv7_cpu_sleep)

ENTRY(armv7_context_switch)
dsb
orr r0, r0, #PT_ATTR

mcr CP15_TTBR0(r0)
isb
#ifdef SMP
mcr CP15_TLBIALLIS
#else
mcr CP15_TLBIALL
#endif
dsb
isb
RET
END(armv7_context_switch)

ENTRY(armv7_drain_writebuf)		ENTRY(armv7_drain_writebuf)
dsb		dsb
RET		RET
END(armv7_drain_writebuf)		END(armv7_drain_writebuf)

ENTRY(armv7_sev)		ENTRY(armv7_sev)
dsb		dsb
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