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sys/arm/arm/cpufunc.c
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struct cpu_functions pj4bv7_cpufuncs = { | struct cpu_functions pj4bv7_cpufuncs = { | ||||
/* CPU functions */ | /* CPU functions */ | ||||
armv7_drain_writebuf, /* cpwait */ | armv7_drain_writebuf, /* cpwait */ | ||||
/* MMU functions */ | /* MMU functions */ | ||||
cpufunc_control, /* control */ | cpufunc_control, /* control */ | ||||
armv7_setttb, /* Setttb */ | armv7_setttb_smp, /* Setttb */ | ||||
/* TLB functions */ | /* TLB functions */ | ||||
armv7_tlb_flushID, /* tlb_flushID */ | armv7_tlb_flushID_smp, /* tlb_flushID */ | ||||
armv7_tlb_flushID_SE, /* tlb_flushID_SE */ | armv7_tlb_flushID_SE_smp, /* tlb_flushID_SE */ | ||||
armv7_tlb_flushID, /* tlb_flushD */ | armv7_tlb_flushID_smp, /* tlb_flushD */ | ||||
armv7_tlb_flushID_SE, /* tlb_flushD_SE */ | armv7_tlb_flushID_SE_smp, /* tlb_flushD_SE */ | ||||
/* Cache operations */ | /* Cache operations */ | ||||
armv7_icache_sync_range, /* icache_sync_range */ | armv7_icache_sync_range, /* icache_sync_range */ | ||||
armv7_dcache_wbinv_all, /* dcache_wbinv_all */ | armv7_dcache_wbinv_all, /* dcache_wbinv_all */ | ||||
armv7_dcache_wbinv_range, /* dcache_wbinv_range */ | armv7_dcache_wbinv_range, /* dcache_wbinv_range */ | ||||
armv7_dcache_inv_range, /* dcache_inv_range */ | armv7_dcache_inv_range, /* dcache_inv_range */ | ||||
armv7_dcache_wb_range, /* dcache_wb_range */ | armv7_dcache_wb_range, /* dcache_wb_range */ | ||||
armv7_idcache_inv_all, /* idcache_inv_all */ | armv7_idcache_inv_all, /* idcache_inv_all */ | ||||
armv7_idcache_wbinv_all, /* idcache_wbinv_all */ | armv7_idcache_wbinv_all_smp, /* idcache_wbinv_all */ | ||||
armv7_idcache_wbinv_range, /* idcache_wbinv_all */ | armv7_idcache_wbinv_range, /* idcache_wbinv_all */ | ||||
(void *)cpufunc_nullop, /* l2cache_wbinv_all */ | (void *)cpufunc_nullop, /* l2cache_wbinv_all */ | ||||
(void *)cpufunc_nullop, /* l2cache_wbinv_range */ | (void *)cpufunc_nullop, /* l2cache_wbinv_range */ | ||||
(void *)cpufunc_nullop, /* l2cache_inv_range */ | (void *)cpufunc_nullop, /* l2cache_inv_range */ | ||||
(void *)cpufunc_nullop, /* l2cache_wb_range */ | (void *)cpufunc_nullop, /* l2cache_wb_range */ | ||||
(void *)cpufunc_nullop, /* l2cache_drain_writebuf */ | (void *)cpufunc_nullop, /* l2cache_drain_writebuf */ | ||||
/* Other functions */ | /* Other functions */ | ||||
armv7_drain_writebuf, /* drain_writebuf */ | armv7_drain_writebuf, /* drain_writebuf */ | ||||
(void *)cpufunc_nullop, /* sleep */ | (void *)cpufunc_nullop, /* sleep */ | ||||
/* Soft functions */ | /* Soft functions */ | ||||
armv7_context_switch, /* context_switch */ | armv7_context_switch_smp, /* context_switch */ | ||||
pj4bv7_setup /* cpu setup */ | pj4bv7_setup /* cpu setup */ | ||||
}; | }; | ||||
#endif /* CPU_MV_PJ4B */ | #endif /* CPU_MV_PJ4B */ | ||||
#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) | #if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) | ||||
struct cpu_functions xscale_cpufuncs = { | struct cpu_functions xscale_cpufuncs = { | ||||
▲ Show 20 Lines • Show All 195 Lines • ▼ Show 20 Lines | struct cpu_functions arm1176_cpufuncs = { | ||||
arm11_context_switch, /* context_switch */ | arm11_context_switch, /* context_switch */ | ||||
arm11x6_setup /* cpu setup */ | arm11x6_setup /* cpu setup */ | ||||
}; | }; | ||||
#endif /*CPU_ARM1176 */ | #endif /*CPU_ARM1176 */ | ||||
#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) | #if defined(CPU_CORTEXA) || defined(CPU_KRAIT) | ||||
struct cpu_functions cortexa_cpufuncs = { | struct cpu_functions cortexa_up_cpufuncs = { | ||||
/* CPU functions */ | /* CPU functions */ | ||||
cpufunc_nullop, /* cpwait */ | cpufunc_nullop, /* cpwait */ | ||||
/* MMU functions */ | /* MMU functions */ | ||||
cpufunc_control, /* control */ | cpufunc_control, /* control */ | ||||
armv7_setttb, /* Setttb */ | armv7_setttb_up, /* Setttb */ | ||||
/* | /* | ||||
* TLB functions. ARMv7 does all TLB ops based on a unified TLB model | * TLB functions. ARMv7 does all TLB ops based on a unified TLB model | ||||
* whether the hardware implements separate I+D or not, so we use the | * whether the hardware implements separate I+D or not, so we use the | ||||
* same 'ID' functions for all 3 variations. | * same 'ID' functions for all 3 variations. | ||||
*/ | */ | ||||
armv7_tlb_flushID, /* tlb_flushID */ | armv7_tlb_flushID_up, /* tlb_flushID */ | ||||
armv7_tlb_flushID_SE, /* tlb_flushID_SE */ | armv7_tlb_flushID_SE_up, /* tlb_flushID_SE */ | ||||
armv7_tlb_flushID, /* tlb_flushD */ | armv7_tlb_flushID_up, /* tlb_flushD */ | ||||
armv7_tlb_flushID_SE, /* tlb_flushD_SE */ | armv7_tlb_flushID_SE_up, /* tlb_flushD_SE */ | ||||
/* Cache operations */ | /* Cache operations */ | ||||
armv7_icache_sync_range, /* icache_sync_range */ | armv7_icache_sync_range, /* icache_sync_range */ | ||||
armv7_dcache_wbinv_all, /* dcache_wbinv_all */ | armv7_dcache_wbinv_all, /* dcache_wbinv_all */ | ||||
armv7_dcache_wbinv_range, /* dcache_wbinv_range */ | armv7_dcache_wbinv_range, /* dcache_wbinv_range */ | ||||
armv7_dcache_inv_range, /* dcache_inv_range */ | armv7_dcache_inv_range, /* dcache_inv_range */ | ||||
armv7_dcache_wb_range, /* dcache_wb_range */ | armv7_dcache_wb_range, /* dcache_wb_range */ | ||||
armv7_idcache_inv_all, /* idcache_inv_all */ | armv7_idcache_inv_all, /* idcache_inv_all */ | ||||
armv7_idcache_wbinv_all, /* idcache_wbinv_all */ | armv7_idcache_wbinv_all_up, /* idcache_wbinv_all */ | ||||
armv7_idcache_wbinv_range, /* idcache_wbinv_range */ | armv7_idcache_wbinv_range, /* idcache_wbinv_range */ | ||||
/* | /* | ||||
* Note: For CPUs using the PL310 the L2 ops are filled in when the | * Note: For CPUs using the PL310 the L2 ops are filled in when the | ||||
* L2 cache controller is actually enabled. | * L2 cache controller is actually enabled. | ||||
*/ | */ | ||||
cpufunc_nullop, /* l2cache_wbinv_all */ | cpufunc_nullop, /* l2cache_wbinv_all */ | ||||
(void *)cpufunc_nullop, /* l2cache_wbinv_range */ | (void *)cpufunc_nullop, /* l2cache_wbinv_range */ | ||||
(void *)cpufunc_nullop, /* l2cache_inv_range */ | (void *)cpufunc_nullop, /* l2cache_inv_range */ | ||||
(void *)cpufunc_nullop, /* l2cache_wb_range */ | (void *)cpufunc_nullop, /* l2cache_wb_range */ | ||||
(void *)cpufunc_nullop, /* l2cache_drain_writebuf */ | (void *)cpufunc_nullop, /* l2cache_drain_writebuf */ | ||||
/* Other functions */ | /* Other functions */ | ||||
armv7_drain_writebuf, /* drain_writebuf */ | armv7_drain_writebuf, /* drain_writebuf */ | ||||
armv7_cpu_sleep, /* sleep */ | armv7_cpu_sleep, /* sleep */ | ||||
/* Soft functions */ | /* Soft functions */ | ||||
armv7_context_switch, /* context_switch */ | armv7_context_switch_up, /* context_switch */ | ||||
cortexa_setup /* cpu setup */ | cortexa_setup /* cpu setup */ | ||||
}; | }; | ||||
#ifdef SMP | |||||
struct cpu_functions cortexa_smp_cpufuncs = { | |||||
/* CPU functions */ | |||||
cpufunc_nullop, /* cpwait */ | |||||
/* MMU functions */ | |||||
cpufunc_control, /* control */ | |||||
armv7_setttb_smp, /* Setttb */ | |||||
/* | |||||
* TLB functions. ARMv7 does all TLB ops based on a unified TLB model | |||||
* whether the hardware implements separate I+D or not, so we use the | |||||
* same 'ID' functions for all 3 variations. | |||||
*/ | |||||
armv7_tlb_flushID_smp, /* tlb_flushID */ | |||||
armv7_tlb_flushID_SE_smp, /* tlb_flushID_SE */ | |||||
armv7_tlb_flushID_smp, /* tlb_flushD */ | |||||
armv7_tlb_flushID_SE_smp, /* tlb_flushD_SE */ | |||||
/* Cache operations */ | |||||
armv7_icache_sync_range, /* icache_sync_range */ | |||||
armv7_dcache_wbinv_all, /* dcache_wbinv_all */ | |||||
armv7_dcache_wbinv_range, /* dcache_wbinv_range */ | |||||
armv7_dcache_inv_range, /* dcache_inv_range */ | |||||
armv7_dcache_wb_range, /* dcache_wb_range */ | |||||
armv7_idcache_inv_all, /* idcache_inv_all */ | |||||
armv7_idcache_wbinv_all_smp, /* idcache_wbinv_all */ | |||||
armv7_idcache_wbinv_range, /* idcache_wbinv_range */ | |||||
/* | |||||
* Note: For CPUs using the PL310 the L2 ops are filled in when the | |||||
* L2 cache controller is actually enabled. | |||||
*/ | |||||
cpufunc_nullop, /* l2cache_wbinv_all */ | |||||
(void *)cpufunc_nullop, /* l2cache_wbinv_range */ | |||||
(void *)cpufunc_nullop, /* l2cache_inv_range */ | |||||
(void *)cpufunc_nullop, /* l2cache_wb_range */ | |||||
(void *)cpufunc_nullop, /* l2cache_drain_writebuf */ | |||||
/* Other functions */ | |||||
armv7_drain_writebuf, /* drain_writebuf */ | |||||
armv7_cpu_sleep, /* sleep */ | |||||
/* Soft functions */ | |||||
armv7_context_switch_smp, /* context_switch */ | |||||
cortexa_setup /* cpu setup */ | |||||
}; | |||||
#endif | |||||
#endif /* CPU_CORTEXA */ | #endif /* CPU_CORTEXA */ | ||||
/* | /* | ||||
* Global constants also used by locore.s | * Global constants also used by locore.s | ||||
*/ | */ | ||||
struct cpu_functions cpufuncs; | struct cpu_functions cpufuncs; | ||||
u_int cputype; | u_int cputype; | ||||
▲ Show 20 Lines • Show All 195 Lines • ▼ Show 20 Lines | #if defined(CPU_ARM1176) | ||||
if (cputype == CPU_ID_ARM1176JZS) { | if (cputype == CPU_ID_ARM1176JZS) { | ||||
cpufuncs = arm1176_cpufuncs; | cpufuncs = arm1176_cpufuncs; | ||||
get_cachetype_cp15(); | get_cachetype_cp15(); | ||||
goto out; | goto out; | ||||
} | } | ||||
#endif /* CPU_ARM1176 */ | #endif /* CPU_ARM1176 */ | ||||
#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) | #if defined(CPU_CORTEXA) || defined(CPU_KRAIT) | ||||
switch(cputype & CPU_ID_SCHEME_MASK) { | switch(cputype & CPU_ID_SCHEME_MASK) { | ||||
case CPU_ID_CORTEXA8: | |||||
cpufuncs = cortexa_up_cpufuncs; | |||||
get_cachetype_cp15(); | |||||
break; | |||||
case CPU_ID_CORTEXA5: | case CPU_ID_CORTEXA5: | ||||
case CPU_ID_CORTEXA7: | case CPU_ID_CORTEXA7: | ||||
case CPU_ID_CORTEXA8: | |||||
case CPU_ID_CORTEXA9: | case CPU_ID_CORTEXA9: | ||||
case CPU_ID_CORTEXA12: | case CPU_ID_CORTEXA12: | ||||
case CPU_ID_CORTEXA15: | case CPU_ID_CORTEXA15: | ||||
case CPU_ID_KRAIT300: | case CPU_ID_KRAIT300: | ||||
cpufuncs = cortexa_cpufuncs; | #ifdef SMP | ||||
cpufuncs = cortexa_smp_cpufuncs; | |||||
#else | |||||
cpufuncs = cortexa_up_cpufuncs; | |||||
#endif | |||||
get_cachetype_cp15(); | get_cachetype_cp15(); | ||||
goto out; | goto out; | ||||
default: | default: | ||||
break; | break; | ||||
} | } | ||||
#endif /* CPU_CORTEXA */ | #endif /* CPU_CORTEXA */ | ||||
#if defined(CPU_MV_PJ4B) | #if defined(CPU_MV_PJ4B) | ||||
▲ Show 20 Lines • Show All 336 Lines • Show Last 20 Lines |