Changeset View
Changeset View
Standalone View
Standalone View
lib/libkvm/kvm_mips.h
Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines | |||||
#define MIPS32_KSEG1_START 0xa0000000 | #define MIPS32_KSEG1_START 0xa0000000 | ||||
#define MIPS32_KSEG1_END 0xbfffffff | #define MIPS32_KSEG1_END 0xbfffffff | ||||
#define MIPS64_KSEG0_START 0xffffffff80000000 | #define MIPS64_KSEG0_START 0xffffffff80000000 | ||||
#define MIPS64_KSEG0_END 0xffffffff9fffffff | #define MIPS64_KSEG0_END 0xffffffff9fffffff | ||||
#define MIPS64_KSEG1_START 0xffffffffa0000000 | #define MIPS64_KSEG1_START 0xffffffffa0000000 | ||||
#define MIPS64_KSEG1_END 0xffffffffbfffffff | #define MIPS64_KSEG1_END 0xffffffffbfffffff | ||||
#define MIPS32_PFN_MASK (0x1FFFFFC0) | #define MIPS32_PFN_MASK (0x1FFFFFC0) | ||||
#define MIPS64_PFN_MASK 0x3FFFFFFC0 | #define MIPS64_PFN_MASK 0xFFFFFFC0 | ||||
jmallett: In this and the PFN mask changes in the kernel headers, I really wonder whether we can safely… | |||||
#define MIPS_PFN_SHIFT (6) | #define MIPS_PFN_SHIFT (6) | ||||
#define MIPS_PFN_TO_PA(pfn) (((pfn) >> MIPS_PFN_SHIFT) << MIPS_PAGE_SHIFT) | #define MIPS_PFN_TO_PA(pfn) (((pfn) >> MIPS_PFN_SHIFT) << MIPS_PAGE_SHIFT) | ||||
#define MIPS32_PTE_TO_PFN(pte) ((pte) & MIPS32_PFN_MASK) | #define MIPS32_PTE_TO_PFN(pte) ((pte) & MIPS32_PFN_MASK) | ||||
#define MIPS32_PTE_TO_PA(pte) (MIPS_PFN_TO_PA(MIPS32_PTE_TO_PFN((pte)))) | #define MIPS32_PTE_TO_PA(pte) (MIPS_PFN_TO_PA(MIPS32_PTE_TO_PFN((pte)))) | ||||
#define MIPS64_PTE_TO_PFN(pte) ((pte) & MIPS64_PFN_MASK) | #define MIPS64_PTE_TO_PFN(pte) ((pte) & MIPS64_PFN_MASK) | ||||
#define MIPS64_PTE_TO_PA(pte) (MIPS_PFN_TO_PA(MIPS64_PTE_TO_PFN((pte)))) | #define MIPS64_PTE_TO_PA(pte) (MIPS_PFN_TO_PA(MIPS64_PTE_TO_PFN((pte)))) | ||||
Show All 33 Lines |
In this and the PFN mask changes in the kernel headers, I really wonder whether we can safely make these changes. I understand they give us more upper software bits, and that on CHERI these are safe because the software and hardware are harmonized here, but are we quite sure that there's no real hardware where the physical address layout might require being able to decode these bits of the PFN?